I, Julie Carlson, declare as follows:
`
`1.
`
`I have personal knowledge of the facts set forth herein, and if called to
`
`testify, I could and would competently testify to the same.
`
`2.
`
`I have been involved in semiconductor standardization and
`
`publication services for over twenty years. For nearly all of this time, I have
`
`worked at JEDEC, a standards-setting organization for the microelectronics
`
`industry, to edit, publish, and maintain JEDEC business records and standards
`
`developed by its numerous committees and subcommittees.
`
`3.
`
`I have been involved with the standardization and publication
`
`activities of JEDEC continuously since 1997. I was the Manager of Standards and
`
`Publications at JEDEC from February 1997 through June 2005. Since June 2005, I
`
`have continued to work for JEDEC as a Consultant where my responsibilities
`
`include the maintenance and publication of JEDEC documents and standards. In
`
`addition, I am familiar with JEDEC’s historical record-keeping and publication
`
`practices since at least 1992, based on my review of JEDEC’s business records
`
`since that time and my regular discussions with JEDEC employees and members.
`
`4.
`
`For over 50 years, JEDEC has been the global leader in developing
`
`and publishing open standards for the microelectronics industry. JEDEC’s
`
`membership consists of more than 3,000 volunteers representing nearly 300
`
`1
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 1
`
`

`

`member companies, and includes key technical individuals from most device,
`
`assembly, system and testing companies. JEDEC publications and standards are
`
`adopted worldwide. JEDEC is accredited by ANSI and maintains liaisons with
`
`numerous standards bodies throughout the world.
`
`5.
`
`Since at least 2000, JEDEC standards have been publicly available for
`
`download from the JEDEC website (https://www.jedec.org), where they are
`
`cataloged and indexed by keyword and technological subject matter. By 2000, the
`
`JEDEC website was publicly available and commonly used by manufactures,
`
`companies in the microelectronics industry, and other interested parties to access
`
`and obtain standards information pertaining to that industry. Anyone interested can
`
`join JEDEC online, at JEDEC.org.
`
`6.
`
`This declaration concerns JEDEC STANDARD, DDR3 SDRAM
`
`Specification, JESD79-3C (November 2008) (hereinafter, “JESD79-3C Standard”),
`
`which is a standard published by JEDEC. I have reviewed the JESD79-3C
`
`Standard. The copy of the JESD79-3C Standard attached to this declaration as
`
`Exhibits A is identical to the copy of the JESD79-3C Standard in JEDEC’s files.
`
`7.
`
`The following statements on the public availability of the JESD79-3C
`
`Standard as of November 2008 are based on personal knowledge. The
`
`development of all JEDEC documents follows the process set forth in JM21:
`
`JEDEC Manual of Organization and Procedure. According to that process, the
`
`2
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`Micron Technology Inc. et al.
`Ex. 1019, p. 2
`
`

`

`date on the cover of a JEDEC document is the month the document was finalized,
`
`approved by legal, and posted to the website. For the JESD79-3C Standard, the
`
`date on the cover (and thus the date it was posted to JEDEC’s website) is
`
`November 2008.
`
`8.
`
`I am familiar with the circulation and publication procedures used by
`
`JEDEC. Upon approval of the Board of Directors, the JEDEC publications
`
`department prepares documents for publication, and seeks final review and
`
`approval to publish from the JEDEC legal department. Once legal approval is
`
`received, the JEDEC publications department uploads the approved document to
`
`the JEDEC website with a brief description. An email announcement is then sent
`
`to the sponsoring committee and any approved resellers. By 2000, JEDEC made
`
`its published standards available for download from www.jedec.org, as mentioned
`
`above.
`
`9.
`
`Based on my personal knowledge of JEDEC’s policies, the JESD79-
`
`3C Standard was made publicly available in November 2008 for download from
`
`the JEDEC website (https://www.jedec.org), consistent with the date on the cover
`
`page of the JESD79-3C Standard. My knowledge of the procedures surrounding
`
`the creation of the date notation and publication is based on JEDEC’s policies and
`
`practices as I understand them through my work at JEDEC. I rely on these policies
`
`and practices in the course of my work. I have no reason to believe that JEDEC’s
`
`3
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 3
`
`

`

`typical practice was not followed. I have no reason to believe that the JESD79-3C
`
`Standard was not made publicly accessible in November 2008.
`
`10. To further confirm my statements above, I have visited the Internet
`
`Archive to look at the first capture of the online catalog at www.jedec.org after
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`November 2008, which occurred on December 7, 2008:
`
`<http://web.archive.org/web/20081207190024/http://www.jedec.org/Catalog/displ
`
`ay.cfm>. A printout of this capture is attached as Exhibit B and is consistent with
`
`my personal recollection of the JEDEC website. As can be seen from this capture
`
`on December 7, 2008, the JESD79-3C Standard was cataloged, indexed under the
`
`“RAM Memories” technical subject matter and under the keywords “SDRAM”
`
`and “DDR3,” and was available to the public by that date, consistent with my
`
`statements above. See Exhibit B at pages 24, 61, 70, 93.
`
`11. Exhibit C is a printout of
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`<http://web.archive.org/web/20081201234333/http://jedec.org/service_members/N
`
`ew_Members/memberco.cfm>, which is a capture on December 1, 2008, of the list
`
`of member companies on JEDEC’s website as of that date, which is consistent with
`
`my personal recollection of JEDEC’s membership. All of those member
`
`companies would have had access to the JESD79-3C Standard attached as Exhibit
`
`A no later than that date.
`
`4
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`Micron Technology Inc. et al.
`Ex. 1019, p. 4
`
`

`

`I, Julie Carlson, do hereby declare and state, that all statements made herein of my
`
`own knowledge are true and that all statements made on information and belief are
`
`believed to be true; and further that these statements were made with the knowledge
`
`that willful false statements and the like so made are punishable by fine or
`
`imprisonment, under Section 1001 of Title 18 of the United States Code.
`
`Executed on
`
`___________
`
`___________________________________
`
`Julie D. Carlson
`
`5
`
`2021/09/16
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 5
`
`

`

`Exhibit A
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 6
`
`

`

`JEDEC
`STANDARD
`
`
`
`
`DDR3 SDRAM
`
`
`
`JESD79-3C
`
`(Revision of Jesd79-3B, April 2008)
`
`
`
`
`
`NOVEMBER 2008
`
`
`
`JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
`
`
`
`
`
`
`
`
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 7
`
`

`

`NOTICE
`
`JEDEC standards and publications contain material that has been prepared, reviewed, and
`approved through the JEDEC Board of Directors level and subsequently reviewed and approved
`by the JEDEC legal counsel.
`
`JEDEC standards and publications are designed to serve the public interest through eliminating
`misunderstandings between manufacturers and purchasers, facilitating interchangeability and
`improvement of products, and assisting the purchaser in selecting and obtaining with minimum
`delay the proper product for use by those other than JEDEC members, whether the standard is to
`be used either domestically or internationally.
`
`JEDEC standards and publications are adopted without regard to whether or not their adoption
`may involve patents or articles, materials, or processes. By such action JEDEC does not assume
`any liability to any patent owner, nor does it assume any obligation whatever to parties adopting
`the JEDEC standards or publications.
`
`The information included in JEDEC standards and publications represents a sound approach to
`product specification and application, principally from the solid state device manufacturer
`viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or
`publication may be further processed and ultimately become an ANSI standard.
`
`No claims to be in conformance with this standard may be made unless all requirements stated in
`the standard are met.
`
`Inquiries, comments, and suggestions relative to the content of this JEDEC standard or
`publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or
`www.jedec.org
`
`Published by
`©JEDEC Solid State Technology Association 2008
`3103 North 10th Street
`Suite 240 South
`Arlington, VA 22201-2107
`
`This document may be downloaded free of charge; however JEDEC retains the
`copyright on this material. By downloading this file the individual agrees not to
`charge for or resell the resulting material.
`
`PRICE: Please refer to the current
`Catalog of JEDEC Engineering Standards and Publications online at
`http://www.jedec.org/Catalog/catalog.cfm
`
`
`Printed in the U.S.A.
`All rights reserved
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 8
`
`

`

`
`
`
`
`
`
`
`
`PLEASE!
`
`
`DON’T VIOLATE
`THE
`LAW!
`
`
`
`This document is copyrighted by JEDEC and may not be
`reproduced without permission.
`
`Organizations may obtain permission to reproduce a limited number of copies
`through entering into a license agreement. For information, contact:
`
`
`
`JEDEC Solid State Technology Association
`3103 North 10th Street
`Suite 240 South
`Arlington, VA 22201-2107
`or call (703) 907-7559
`
`
`
`
`
`
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`
`
`
`
`
`
`
`
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 9
`
`

`

`Micron TechnologyInc.et al.
`Ex. 1019, p. 10
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 10
`
`

`

`Micron TechnologyInc.et al.
`Ex. 1019, p. 11
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 11
`
`

`

`JEDEC Standard No. 79-3C
`
`Contents
`1 Scope..........................................................................................................................................1
`2 DDR3 SDRAM Package Pinout and Addressing ......................................................................3
`2.1 DDR3 SDRAM x4 Ballout using MO-207........................................................................3
`2.2 DDR3 SDRAM x8 Ballout using MO-207........................................................................4
`2.3 DDR3 SDRAM x16 Ballout using MO-207......................................................................5
`2.4 Stacked / dual-die DDR3 SDRAM x4 Ballout using MO-207 ..........................................6
`2.5 Stacked / dual-die DDR3 SDRAM x8 Ballout using MO-207 ..........................................7
`2.6 Stacked / dual-die DDR3 SDRAM x16 Ballout using MO-207 ........................................8
`2.7 Quad-stacked / Quad-die DDR3 SDRAM x4 Ballout using MO-207...............................9
`2.8 Quad-stacked / Quad-die DDR3 SDRAM x8 Ballout using MO-207.............................10
`2.9 Quad-stacked / Quad-die DDR3 SDRAM x16 Ballout using MO-207...........................11
`2.10 Pinout Description..........................................................................................................13
`2.11 DDR3 SDRAM Addressing...........................................................................................15
`2.11.1 512Mb ....................................................................................................................15
`2.11.2 1Gb..........................................................................................................................15
`2.11.3 2Gb .........................................................................................................................15
`2.11.4 4Gb .........................................................................................................................15
`2.11.5 8Gb .........................................................................................................................16
`3 Functional Description.............................................................................................................17
`3.1 Simplified State Diagram.................................................................................................17
`3.2 Basic Functionality...........................................................................................................18
`3.3 RESET and Initialization Procedure ................................................................................19
`3.3.1 Power-up Initialization Sequence .............................................................................19
`3.3.2 Reset Initialization with Stable Power......................................................................21
`3.4 Register Definition ...........................................................................................................22
`3.4.1 Programming the Mode Registers.............................................................................22
`3.4.2 Mode Register MR0..................................................................................................23
`3.4.3 Mode Register MR1..................................................................................................26
`3.4.4 Mode Register MR2..................................................................................................29
`3.4.5 Mode Register MR3..................................................................................................31
`4 DDR3 SDRAM Command Description and Operation...........................................................33
`4.1 Command Truth Table .....................................................................................................33
`4.2 CKE Truth Table..............................................................................................................35
`4.3 No OPeration (NOP) Command ......................................................................................36
`4.4 Deselect Command ..........................................................................................................36
`4.5 DLL-off Mode..................................................................................................................37
`4.6 DLL on/off switching procedure......................................................................................38
`4.6.1 DLL “on” to DLL “off” Procedure...........................................................................38
`4.6.2 DLL “off” to DLL “on” Procedure...........................................................................39
`4.7 Input clock frequency change ..........................................................................................40
`4.8 Write Leveling .................................................................................................................42
`4.8.1 DRAM setting for write leveling & DRAM termination function in that mode ......43
`4.8.2 Procedure Description...............................................................................................43
`4.8.3 Write Leveling Mode Exit ........................................................................................45
`4.9 Extended Temperature Usage ..........................................................................................46
`
`i
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 12
`
`

`

`JEDEC Standard No. 79-3C
`
`Contents
`
`4.9.1 Self-Refresh Temperature Range - SRT ...................................................................46
`4.10 Multi Purpose Register...................................................................................................48
`4.10.1 MPR Functional Description ..................................................................................49
`4.10.2 MPR Register Address Definition ..........................................................................50
`4.10.3 Relevant Timing Parameters...................................................................................50
`4.10.4 Protocol Example....................................................................................................50
`4.11 ACTIVE Command .......................................................................................................55
`4.12 PRECHARGE Command ..............................................................................................55
`4.13 READ Operation............................................................................................................56
`4.13.1 READ Burst Operation ...........................................................................................56
`4.13.2 READ Timing Definitions
`57
`4.13.3 Burst Read Operation followed by a Precharge......................................................66
`4.14 WRITE Operation ..........................................................................................................68
`4.14.1 DDR3 Burst Operation............................................................................................68
`4.14.2 WRITE Timing Violations......................................................................................68
`4.14.3 Write Data Mask .....................................................................................................69
`4.14.4 tWPRE Calculation.................................................................................................70
`4.14.5 tWPST Calculation .................................................................................................70
`4.15 Refresh Command..........................................................................................................77
`4.16 Self-Refresh Operation...................................................................................................79
`4.17 Power-Down Modes.......................................................................................................81
`4.17.1 Power-Down Entry and Exit...................................................................................81
`4.17.2 Power-Down clarifications - Case 1 .......................................................................86
`4.17.3 Power-Down clarifications - Case 2 .......................................................................87
`4.17.4 Power-Down clarifications - Case 3 .......................................................................88
`4.18 ZQ Calibration Commands ............................................................................................89
`4.18.1 ZQ Calibration Description.....................................................................................89
`4.18.2 ZQ Calibration Timing............................................................................................90
`4.18.3 ZQ External Resistor Value, Tolerance, and Capacitive loading ...........................90
`5 On-Die Termination (ODT).....................................................................................................91
`5.1 ODT Mode Register and ODT Truth Table.....................................................................91
`5.2 Synchronous ODT Mode .................................................................................................92
`5.2.1 ODT Latency and Posted ODT.................................................................................92
`5.2.2 Timing Parameters ....................................................................................................92
`5.2.3 ODT during Reads ....................................................................................................94
`5.3 Dynamic ODT..................................................................................................................96
`5.3.1 Functional Description:.............................................................................................96
`5.3.2 ODT Timing Diagrams .............................................................................................97
`5.4 Asynchronous ODT Mode .............................................................................................102
`5.4.1 Synchronous to Asynchronous ODT Mode Transitions.........................................103
`5.4.2 Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry103
`5.4.3 Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit .106
`5.4.4 Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low
`periods.....................................................................................................................107
`
`ii
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 13
`
`

`

`JEDEC Standard No. 79-3C
`
`Contents
`6 Absolute Maximum Ratings ..................................................................................................109
`6.1 Absolute Maximum DC Ratings....................................................................................109
`6.2 DRAM Component Operating Temperature Range ......................................................109
`7 AC & DC Operating Conditions............................................................................................111
`7.1 Recommended DC Operating Conditions......................................................................111
`8 AC and DC Input Measurement Levels.................................................................................113
`8.1 AC and DC Logic Input Levels for Single-Ended Signals ............................................113
`8.1.1 AC and DC Input Levels for Single-Ended Command and Address Signals.........113
`8.1.2 AC and DC Input Levels for Single-Ended Data Signals.......................................113
`8.2 Vref Tolerances..............................................................................................................114
`8.3 AC and DC Logic Input Levels for Differential Signals ...............................................115
`8.3.1 Differential signal definition...................................................................................115
`8.3.2 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)115
`8.3.3 Single-ended requirements for differential signals .................................................116
`8.4 Differential Input Cross Point Voltage ..........................................................................117
`8.5 Slew Rate Definitions for Single-Ended Input Signals..................................................119
`8.6 Slew Rate Definitions for Differential Input Signals.....................................................119
`9 AC and DC Output Measurement Levels ..............................................................................121
`9.1 Single Ended AC and DC Output Levels.......................................................................121
`9.2 Differential AC and DC Output Levels .........................................................................121
`9.3 Single Ended Output Slew Rate.....................................................................................122
`9.4 Differential Output Slew Rate........................................................................................123
`9.5 Reference Load for AC Timing and Output Slew Rate .................................................124
`9.6 Overshoot and Undershoot Specifications .....................................................................125
`9.6.1 Address and Control Overshoot and Undershoot Specifications............................125
`9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications.............126
`9.7 34 ohm Output Driver DC Electrical Characteristics ....................................................127
`9.7.1 Output Driver Temperature and Voltage sensitivity...............................................128
`9.8 On-Die Termination (ODT) Levels and I-V Characteristics .........................................130
`9.8.1 On-Die Termination (ODT) Levels and I-V Characteristics ..................................130
`9.8.2 ODT DC Electrical Characteristics.........................................................................131
`9.8.3 ODT Temperature and Voltage sensitivity .............................................................134
`9.9 ODT Timing Definitions................................................................................................134
`9.9.1 Test Load for ODT Timings ...................................................................................134
`9.9.2 ODT Timing Definitions.........................................................................................135
`10 IDD and IDDQ Specification Parameters and Test Conditions...........................................139
`10.1 IDD and IDDQ Measurement Conditions....................................................................139
`10.2 IDD Specifications .......................................................................................................150
`11 Input/Output Capacitance ....................................................................................................153
`11.1 Input/Output Capacitance.............................................................................................153
`12 Electrical Characteristics & AC Timing for DDR3-800 to DDR3-1600.............................155
`12.1 Clock Specification ......................................................................................................155
`12.1.1 Definition for tCK(avg) ........................................................................................155
`12.1.2 Definition for tCK(abs).........................................................................................155
`12.1.3 Definition for tCH(avg) and tCL(avg)..................................................................155
`
`iii
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 14
`
`

`

`JEDEC Standard No. 79-3C
`
`Contents
`
`12.1.4 Definition for tJIT(per) and tJIT(per,lck) .............................................................155
`12.1.5 Definition for tJIT(cc) and tJIT(cc,lck).................................................................156
`12.1.6 Definition for tERR(nper).....................................................................................156
`12.2 Refresh parameters by device density..........................................................................156
`12.3 Standard Speed Bins ....................................................................................................157
`12.3.1 Speed Bin Table Notes..........................................................................................161
`13 Electrical Characteristics and AC Timing ...........................................................................163
`13.1 Jitter Notes ...................................................................................................................170
`13.2 Timing Parameter Notes ..............................................................................................171
`13.3 Address / Command Setup, Hold and Derating ...........................................................173
`13.4 Data Setup, Hold and Slew Rate Derating ...................................................................180
`
`Annex A (informative) Differences between JESD79-3C, and JESD79-3B............................A1
`
`iv
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 15
`
`

`

`JEDEC Standard No. 79-3C
`
`List of Figures
`Figure 1 —Qual-stacked / Quad-die DDR3 SDRAM x4 rank association . . . . . . . . . . . . . . . . . 12
`Figure 2 —Qual-stacked / Quad-die DDR3 SDRAM x8 rank association . . . . . . . . . . . . . . . . . 12
`Figure 3 —Qual-stacked / Quad-die DDR3 SDRAM x16 rank association . . . . . . . . . . . . . . . . 12
`Figure 4 —Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`Figure 5 —Reset and Initialization Sequence at Power-on Ramping . . . . . . . . . . . . . . . . . . . . . 20
`Figure 6 —Reset Procedure at Power Stable Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
`Figure 7 —tMRD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
`Figure 8 —tMOD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
`Figure 9 —MR0 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
`Figure 10 —MR1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
`Figure 11 —MR2 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
`Figure 12 —MR3 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
`Figure 13 —DLL-off mode READ Timing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
`Figure 14 — DLL Switch Sequence from DLL-on to DLL-off . . . . . . . . . . . . . . . . . . . . . . . . . 38
`Figure 15 —DLL Switch Sequence from DLL Off to DLL On . . . . . . . . . . . . . . . . . . . . . . . . . 39
`Figure 16 —Change Frequency during Precharge Power-down . . . . . . . . . . . . . . . . . . . . . . . . . 41
`Figure 17 —Write Leveling Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
`Figure 18 —Timing details of Write leveling sequence [DQS - DQS# is capturing CK - CK# low
`at T1 and CK - CK# high at T2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
`Figure 19 —Timing details of Write leveling exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
`Figure 20 —MPR Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
`Figure 21 —MPR Readout of predefined pattern, BL8 fixed burst order, single readout . . . . . . 51
`Figure 22 —MPR Readout of predefined pattern, BL8 fixed burst order, back-to-back readout 52
`Figure 23 —MPR Readout predefined pattern, BC4, lower nibble then upper nibble . . . . . . . . 53
`Figure 24 —MPR Readout of predefined pattern, BC4, upper nibble then lower nibble . . . . . . 54
`Figure 25 —READ Burst Operation RL = 5 (AL = 0, CL = 5, BL8) . . . . . . . . . . . . . . . . . . . . . 56
`Figure 26 —READ Burst Operation RL = 9 (AL = 4, CL = 5, BL8) . . . . . . . . . . . . . . . . . . . . . 56
`Figure 27 —READ Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`Figure 28 —Clock to Data Strobe Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`Figure 29 —Data Strobe to Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
`Figure 30 —tLZ and tHZ method for calculating transitions and endpoints . . . . . . . . . . . . . . . . 60
`Figure 31 —Method for calculating tRPRE transitions and endpoints . . . . . . . . . . . . . . . . . . . . 61
`Figure 32 —Method for calculating tRPST transitions and endpoints . . . . . . . . . . . . . . . . . . . . 61
`Figure 33 —READ (BL8) to READ (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Figure 34 —READ (BC4) to READ (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Figure 35 —READ (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Figure 36 —READ (BC4) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Figure 37 —READ (BL8) to READ (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
`Figure 38 —READ (BC4) to READ (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
`Figure 39 —READ (BC4) to WRITE (BL8) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
`Figure 40 —READ (BL8) to WRITE (BC4) OTF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
`Figure 41 —READ to PRECHARGE, RL = 5, AL = 0, CL = 5, tRTP = 4, tRP = 5 . . . . . . . . . 66
`Figure 42 —READ to PRECHARGE, RL = 8, AL = CL-2, CL = 5, tRTP = 6, tRP = 5 . . . . . . 67
`Figure 43 —Write Timing Definition and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
`Figure 44 —Method for calculating tWPRE transitions and endpoints . . . . . . . . . . . . . . . . . . . 70
`Figure 45 —Method for calculating tWPST transitions and endpoints . . . . . . . . . . . . . . . . . . . . 70
`Figure 46 —WRITE Burst Operation WL = 5 (AL = 0, CWL = 5, BL8) . . . . . . . . . . . . . . . . . . 71
`Figure 47 —WRITE Burst Operation WL = 9 (AL = CL-1, CWL = 5, BL8) . . . . . . . . . . . . . . 71
`
`v
`
`Micron Technology Inc. et al.
`Ex. 1019, p. 16
`
`

`

`JEDEC Standard No. 79-3C
`
`List of Figures
`
`Figure