I, Julie Carlson, declare as follows:
`
`1.
`
`I have personal knowledge of the facts set forth herein, and if called to
`
`testify, I could and would competently testify to the same.
`
`2.
`
`I have been involved in semiconductor standardization and
`
`publication services for over twenty years. For nearly all of this time, I have
`
`worked at JEDEC, a standards-setting organization for the microelectronics
`
`industry, to edit, publish, and maintain JEDEC business records and standards
`
`developed by its numerous committees and subcommittees.
`
`3.
`
`I have been involved with the standardization and publication
`
`activities of JEDEC continuously since 1997. I was the Manager of Standards and
`
`Publications at JEDEC from February 1997 through June 2005. Since June 2005, I
`
`have continued to work for JEDEC as a Consultant where my responsibilities
`
`include the maintenance and publication of JEDEC documents and standards. In
`
`addition, I am familiar with JEDEC’s historical record-keeping and publication
`
`practices since at least 1992, based on my review of JEDEC’s business records
`
`since that time and my regular discussions with JEDEC employees and members.
`
`4.
`
`For over 50 years, JEDEC has been the global leader in developing
`
`and publishing open standards for the microelectronics industry. JEDEC’s
`
`membership consists of more than 3,000 volunteers representing nearly 300
`
`1
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 1
`
`

`

`member companies, and includes key technical individuals from most device,
`
`assembly, system and testing companies. JEDEC publications and standards are
`
`adopted worldwide. JEDEC is accredited by ANSI and maintains liaisons with
`
`numerous standards bodies throughout the world.
`
`5.
`
`Since at least 2000, JEDEC standards have been publicly available for
`
`download from the JEDEC website (https://www.jedec.org), where they are
`
`cataloged and indexed by keyword and technological subject matter. By 2000, the
`
`JEDEC website was publicly available and commonly used by manufactures,
`
`companies in the microelectronics industry, and other interested parties to access
`
`and obtain standards information pertaining to that industry. Anyone interested can
`
`join JEDEC online, at JEDEC.org.
`
`6.
`
`This declaration concerns JEDEC Standard No. 21-C, PC2100 and
`
`PC1600 DDR SDRAM Registered DIMM Design Specification (January 2002),
`
`Page 4.20.4-1 to -82 (hereinafter, “JESD21-C”). The copy of JESD21-C attached
`
`to this declaration as Exhibit A is identical to the copy of JESD21-C in JEDEC’s
`
`files.
`
`7.
`
`The following statements on the public availability of JESD21-C as of
`
`January 2002 and October 2003 are based on personal knowledge. The
`
`development of all JEDEC documents follows the process set forth in JM21:
`
`JEDEC Manual of Organization and Procedure. According to that process, the
`
`2
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 2
`
`

`

`date on the cover of a JEDEC document is the month the document was finalized,
`
`approved by legal, and posted to the website. For JESD21-C, the date on the cover
`
`is January 2002. However, JESD21-C was part of JEDEC Standard No. 21-C, for
`
`which JEDEC provided an update service where specific pages could be updated
`
`as part of a periodic “Release.” In the copy of JESD21-C attached as Exhibit A,
`
`most pages (like the cover page dated January 2002) were published in January
`
`2002. A few pages were updated as part of Release 12, see Exhibit A at pages
`
`4.20.4-6 to -9, -22, and one page was updated as part of Release 13 in October
`
`2003, see Exhibit A at page 4.20.4-71.
`
`8.
`
`I am familiar with the circulation and publication procedures used by
`
`JEDEC. Upon approval of the Board of Directors, the JEDEC publications
`
`department prepares documents for publication, and seeks final review and
`
`approval to publish from the JEDEC legal department. Once legal approval is
`
`received, the JEDEC publications department uploads the approved document to
`
`the JEDEC website with a brief description. An email announcement is then sent
`
`to the sponsoring committee and any approved resellers. By 2000, JEDEC made
`
`its published standards available for download from www.jedec.org, as mentioned
`
`above.
`
`9.
`
`Based on my personal knowledge of JEDEC’s policies, most of the
`
`pages of the copy of JESD21-C attached as Exhibit A were made publicly
`
`3
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 3
`
`

`

`available in January 2002 and all of the pages of the copy of JESD21-C attached as
`
`Exhibit A were made publicly available by October 2003. My knowledge of the
`
`procedures surrounding the creation of the date notation and publication is based
`
`on JEDEC’s policies and practices as I understand them through my work at
`
`JEDEC. I rely on these policies and practices in the course of my work. I have no
`
`reason to believe that JEDEC’s typical practice was not followed. I have no reason
`
`to believe that JESD21-C was not made publicly accessible in January 2002 in
`
`October 2003 as described above.
`
`10. To further confirm my statements above regarding JESD21-C, I have
`
`visited the Internet Archive to look at the first capture of the online catalog at
`
`www.jedec.org after January 2002, which occurred on November 5, 2002:
`
`<http://web.archive.org/web/20021105112938/http://www.jedec.org/Catalog/displ
`
`ay.cfm>. A printout of this capture is attached as Exhibit B and is consistent with
`
`my personal recollection of the JEDEC website. As can be seen from this capture
`
`on November 5, 2002, the JEDEC Standard No. 21-C was cataloged, indexed with
`
`the title “CONFIGURATIONS FOR SOLID STATE MEMORIES” and the
`
`keyword “21-C,” and was available to the public by that date, consistent with my
`
`statements above. See Exhibit B at pages 6, 43, 66. The JEDEC website
`
`explained, “JESD21-C is a compilation of all memory device standards that have
`
`been developed by the JC-42 Committee and approved by the JEDEC Council
`
`4
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 4
`
`

`

`from September 1989. This latest issue has changed to a loose-leaf format and
`
`comes in a three-ring binder so that new drawings can be added without requiring a
`
`new publication.” See Exhibit B at page 6. In addition, the JEDEC website
`
`offered an “ANNUAL UPDATING SERVICE” for the JEDEC Standard No. 21-C:
`
`“The JEDEC Office has generated a mailing list for those who wish to subscribe to
`
`updates of this publication.” See Exhibit B at page 6. As explained above,
`
`JESD21-C attached as Exhibit A was part of JEDEC Standard No. 21-C, for which
`
`JEDEC provided an update service where specific pages could be updated as part
`
`of a periodic “Release.” The capture on November 5, 2002, attached as Exhibit B
`
`included a link to the Table of Contents for the current Release of the JEDEC
`
`Standard No. 21-C. See Exhibit B at page 66. I have visited the Internet Archive
`
`to look at the first capture of that Table of Contents after January 2002, which
`
`occurred on April 21, 2003:
`
`<http://web.archive.org/web/20021105112938/http://www.jedec.org/download/sea
`
`rch/21C_TOCR11b.pdf>. A printout of this capture is attached as Exhibit C and is
`
`consistent with my personal recollection of the JEDEC website and the JEDEC
`
`Standard No. 21-C. As can be seen from this Table of Contents attached as Exhibit
`
`C, “4.20.4 — 184 Pin PC1600/2100 DDR SDRAM Registered DIMM Design
`
`Specification” was included as part of “Release 11” to the JEDEC Standard No.
`
`5
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 5
`
`

`

`21-C and made available to the public, consistent with my statements above about
`
`JESD21-C attached as Exhibit A. See Exhibit C at page xxi.
`
`11. Exhibit D is a printout of
`
`<https://web.archive.org/web/20031208154552/http://www.jedec.org:80/service_
`
`members/New_Members/memberco.cfm>, which is a capture on December 8,
`
`2003. Exhibit D shows the list of member companies on JEDEC’s website as of
`
`that date, which is consistent with my personal recollection of JEDEC’s
`
`membership. All of those member companies would have had access to JESD21-C
`
`attached as Exhibit A no later than that date.
`
`I, Julie Carlson, do hereby declare and state, that all statements made herein of my
`
`own knowledge are true and that all statements made on information and belief are
`
`believed to be true; and further that these statements were made with the knowledge
`
`that willful false statements and the like so made are punishable by fine or
`
`imprisonment, under Section 1001 of Title 18 of the United States Code.
`
`Executed on
`
`___________
`
`___________________________________
`
`Julie D. Carlson
`
`6
`
`2021/09/16
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 6
`
`

`

`Exhibit A
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 7
`
`

`

`Jedec Standard No. 21-C
`
`Page 4.20.4–1
`
`DDR SDRAM Registered DIMM Design Specification
`
`PC2100 and PC1600 DDR SDRAM Registered DIMM
`
`Design Specification
`
`Revision 1.3
`
`January 2002
`
`Release 11b
`
`Revision 1.3
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 8
`
`

`

`Page 4.20.4–2
`
`Jedec Standard No. 21-C
`
`DDR SDRAM Registered DIMM Design Specification
`
`Revision 1.3
`
`Release 11b
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 9
`
`

`

`Jedec Standard No. 21-C
`
`Page 4.20.4–3
`
`DDR SDRAM Registered DIMM Design Specification
`
`Product Description .................................................................................................................................. 5
`
`Environmental Requirements ................................................................................................................... 6
`
`Architecture ............................................................................................................................................... 6
`Block Diagram: Raw Card Version A/L (x72 DIMM, One Physical Bank) ........................................... 10
`Block Diagram: Raw Card Version A/L (x64 DIMM, One Physical Bank) ............................................ 11
`Block Diagram: Raw Card Version A/L (x72 DIMM, Two Physical Banks) .......................................... 12
`Block Diagram: Raw Card Version A/L (x64 DIMM, Two Physical Banks) .......................................... 13
`Block Diagram: Raw Card Version B/M .............................................................................................. 10
`Block Diagram: Raw Card Version N ................................................................................................... 15
`Block Diagram: Raw Card Version C/E ............................................................................................... 16
`Differential Clock Net Wiring (CK0, CK0) ............................................................................................ 17
`
`Component Details .................................................................................................................................. 20
`Pin Assignments for 64Mb, 128Mb, 256Mb, 512Mb and 1Gb DDR SDRAM Planar Components ..... 20
`Pin Assignments for 64Mb, 128Mb, 256Mb, 512Mb and 1Gb DDR SDRAM 2-High Stack Package . 21
`DDR SDRAM Component Specifications ............................................................................................ 21
`Register Component Specifications .................................................................................................... 22
`Register Sourcing ................................................................................................................................ 23
`PLL Component Specifications ........................................................................................................... 23
`PLL Sourcing ....................................................................................................................................... 24
`
`Registered DIMM Details ......................................................................................................................... 25
`DDR Registered Design File Releases ............................................................................................... 28
`Example Raw Card Versions A (1 Physical Bank) Component Placement ........................................ 29
`Example Raw Card Versions A (2 Physical Banks) Component Placement ...................................... 30
`Example Raw Card Version B Component Placement ....................................................................... 31
`Example Raw Card Version C/E Component Placement ................................................................... 32
`Example Raw Card Versions L (2 Physical Banks) and M Component Placement ............................ 33
`Example Raw Card Versions L (1 Physical Banks) Component Placement ....................................... 34
`Example Raw Card Versions N (2 Physical Banks) Component Placement ...................................... 35
`
`DIMM Wiring Details ................................................................................................................................ 36
`Signal Groups ..................................................................................................................................... 36
`General Net Structure Routing Guidelines .......................................................................................... 36
`Explanation of Net Structure Diagrams ............................................................................................... 37
`Differential Clock Net Structures ......................................................................................................... 38
`Data Net Structures ............................................................................................................................. 44
`Net Structure Routing for CS and CKE ............................................................................................... 54
`Cross Section Recommendations ....................................................................................................... 66
`
`Release 11b
`
`Revision 1.3
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 10
`
`

`

`Page 4.20.4–4
`
`Jedec Standard No. 21-C
`
`DDR SDRAM Registered DIMM Design Specification
`
`Timing Budget .......................................................................................................................................... 67
`
`Serial PD Definition ................................................................................................................................. 68
`
`Product Label ........................................................................................................................................... 71
`
`DIMM Mechanical Specifications ............................................................................................................ 72
`
`Supporting Hardware .............................................................................................................................. 73
`Clock Reference Board ....................................................................................................................... 73
`
`Application Notes .................................................................................................................................... 74
`Clocking Timing Methodology ............................................................................................................. 74
`
`Revision Log ............................................................................................................................................ 75
`
`Revision 1.3
`
`Release 11b
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 11
`
`

`

`Jedec Standard No. 21-C
`
`DDR SDRAM Registered DIMM Design Specification
`
`Page 4.20.4–5
`
` Product Description
`
`Product Description
`
`This specification defines the electrical and mechanical requirements for 184-pin, 2.5 Volt, PC1600/PC2100,
`64/72 bit-wide, Registered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR
`SDRAM DIMMs).These SDRAM DIMMs are intended for use as main memory when installed in systems
`such as servers and workstations. PC1600/PC2100 refers to the JEDEC standard DIMM naming convention
`in which PC1600 indicates a 184-pin DIMM running at 100 MHz clock speed and offering 1600MB/s band-
`width.
`
`Reference design examples are included which provide an initial basis for Registered DIMM designs. Modifi-
`cations to these reference designs may be required to meet all system timing, signal integrity, and thermal
`requirements for PC1600/PC2100 support. All registered DIMM implementations must use simulations and
`lab verification to ensure proper timing requirements and signal integrity in the design.
`
`This specification largely follows the JEDEC defined 184-pin Registered DDR SDRAM DIMM product (refer to
`JEDEC Standards Manual 21-C, at http://www.jedec.org).
`
`Product Family Attributes
`
`DIMM organization
`
`x72 ECC, x64
`
`DIMM dimensions (nominal)
`
`5.25" x 1.2”/1.7"
`
`Pin count
`
`184
`
`SDRAMs supported
`
`64Mb, 128Mb, 256Mb, 512Mb, 1Gb
`
`Capacity
`
`Serial PD
`
`Voltage options
`
`Interface
`
`64MB, 128MB, 256MB, 512MB, 1GB, 2GB, 4GB
`
`Consistent with JC 42.5 Rev 0
`
`2.5 volt (VDD/VDDQ)
`
`SSTL_2
`
`Release 11b
`
`Revision 1.2
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 12
`
`

`

`Page 4.20.4–6
`
`Jedec Standard No. 21-C
`
` Environmental Requirements
`
`DDR SDRAM Registered DIMM Design Specification
`
`Environmental Requirements
`
`DDR SDRAM Registered DIMMs are intended for use in standard office environments that have limited
`capacity for heating and air conditioning.
`
`Environmental Parameters
`
`Symbol
`
`Parameter
`
`Operating temperature (ambient)
`
`Operating humidity (relative)
`
`Storage temperature
`
`Storage humidity (without condensation)
`
`TOPR
`
`HOPR
`
`TSTG
`
`HSTG
`
`PBAR
`
`Rating
`
` 0 to +55
`
` 10 to 90
`
`-50 to +100
`
` 5 to 95
`
`Units
`
`Notes
`
`qC
`
`%
`
`qC
`
`%
`
`1
`
`1
`
`1
`
`1
`
`Barometric pressure (operating & storage)
`
` 105 to 69
`
`K Pascal
`
`1, 2
`
`1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional
`operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods
`may affect reliability.
`2. Up to 9850 ft.
`
`Architecture
`
`Pin Description
`
`Pin Name
`
`Description
`
`Pin Name
`
`Description
`
`A0 - A15
`
`SDRAM address bus
`
`BA0 - BA1
`
`SDRAM bank select
`
`DQ0 - DQ63
`
`DIMM memory data bus
`
`CB0 - CB7
`
`DIMM ECC check bits
`
`CK0
`
`CK0
`
`SCL
`
`SDA
`
`SDRAM clock
`(positive line of differential pair)
`
`SDRAM clock
`(negative line of differential pair)
`
`IIC serial bus clock for EEPROM
`
`IIC serial bus data line for EEPROM
`
`SDRAM row address strobe
`
`SA0 - SA2
`
`IIC slave address select for EEPROM
`
`RAS
`
`CAS
`
`WE
`
`SDRAM column address strobe
`
`SDRAM write strobe
`
`S0 - S3
`
`SDRAM chip select lines
`(Physical. banks 0, 1, 2, and 3)
`
`CKE0 - CKE1
`
`SDRAM clock enable lines
`
`DQS0 - DQS8
`
`SDRAM low data strobes
`
`VDD
`
`VDDQ
`
`VREF
`
`VSS
`
`SDRAM positive power supply
`
`SDRAM I/O Driver positive power supply
`
`SDRAM I/O reference supply
`
`Power supply return (ground)
`
`VDDSPD
`
`Serial EEPROM positive power supply (Sup-
`ports both 2.5 Volt and 3.3 Volt operation)
`
`DM(0-8)/DQS(9-17)
`
`SDRAM low data masks/high data strobes
`(x4, x8-based x72 DIMMs)
`
`NC
`
`Spare Pins (no connect)
`
`VDDID
`
`Test
`
`VDD Identification Flag
`
`RESET
`
`Reset pin (forces register inputs low)
`
`Used by memory bus analysis tools (unused
`on memory DIMMs)
`
`Revision 1.3
`
`Release 12
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 13
`
`

`

`Jedec Standard No. 21-C
`
`DDR SDRAM Registered DIMM Design Specification
`
`Page 4.20.4–7
`
` Architecture
`
`Input/Output Functional Description
`
`Symbol
`
`Type
`
`Polarity
`
`Function
`
`CK0
`
`SSTL
`
`Positive
`Edge
`
`Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL. (All
`DDR SDRAM addr/cntl inputs are sampled on the rising edge of their associated clocks.)
`
`CK0
`
`SSTL
`
`Negative
`Edge
`
`Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
`
`CKE0, CKE1 SSTL
`
`Active
`High
`
`Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivat-
`ing the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
`
`S0, S1,
`S2, S3
`
` RAS, CAS,
`WE
`
`SSTL Active Low
`
`Enables the associated SDRAM command decoder when low and disables decoder when high.
`When decoder is disabled, new commands are ignored but previous operations continue.
`
`SSTL Active Low
`
`When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to
`be executed by the SDRAM.
`
`VREF
`
`VDDQ
`
`Supply
`
`Supply
`
`Reference voltage for SSTL2 inputs
`
`Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
`
`BA0,BA1
`
`SSTL
`
`—
`
`Selects which SDRAM bank of four is activated.
`
`A0 - A9, A11
`A10/AP,
`A12- A15
`
`SSTL
`
`—
`
`During a Bank Activate command cycle, A0-A15 defines the row address (RA0-RA15) when sam-
`pled at the rising clock edge.
`During a Read or Write command cycle, A0-A12 defines the column address (CA0-CA12) when
`sampled at the rising clock edge. In addition to the column address, AP is used to invoke autopre-
`charge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected
`and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled.
`During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which
`bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or
`BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
`
`DQ0 - DQ63,
`CB0 - CB7
`
`SSTL
`
`—
`
`Data and Check Bit Input/Output pins
`
`DM0-DM8
`
`SSTL
`
`Active
`High
`
`Masks write data when high, issued concurrently with input data. Both DM and DQ have a write
`latency of one clock once the write command is registered into the SDRAM.
`
`VDD, VSS
`
`Supply
`
`Power and ground for the DDR SDRAM input buffers and core logic
`
`DQS0-DQS8 SSTL
`
`Negative
`and Posi-
`tive Edge
`
`Data strobe for input and output data.
`
`SA0 - 2
`
`SDA
`
`SCL
`
`—
`
`—
`
`—
`
`These signals are tied at the system planar to either VSS or VDD to configure the serial SPD
`EEPROM address range.
`
`This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be
`connected from the SDA bus line to VDD to act as a pullup.
`
`This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected
`from the SCL bus time to VDD to act as a pullup.
`
`VDDSPD
`
`Supply
`
`Serial EEPROM positive power supply (wired to a separate power pin at the connector which sup-
`ports both 2.3 Volt and 3.3 Volt operation).
`
`RESET
`
`LV-
`CMOS
`
`Active Low
`
`This signal is asynchronous and driven low to the register to guarantee that the register outputs are
`low.
`
`Release 12
`
`Revision 1.3
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 14
`
`

`

`Page 4.20.4–8
`
` Architecture
`
`DDR SDRAM Registered DIMM Design Specification
`
`Jedec Standard No. 21-C
`
`. 1
`
`84-Pin DDR SDRAM DIMM Pin Assignments
`
`Front Side (left side 1 - 52, right
`side 53 - 92)
`
`Back Side (left side 93 -144,
`right side 145 -184)
`
`Front Side (left side 1 - 52, right
`side 53 - 92)
`
`Back Side (left side 93 -144,
`right side 145 -184)
`
`Pin
`#
`
`x64
`Non-Parity
`
`1
`
`2
`
`VREF
`
`DQ0
`
`x72
`ECC
`
`VREF
`
`DQ0
`
`Pin
`#
`
`x64
`Non-Parity
`
`93
`
`94
`
`VSS
`
`DQ4
`
`DQ5
`
`x72
`ECC
`
`VSS
`
`DQ4
`
`DQ5
`
`Pin
`#
`
`x64
`Non-Parity
`
`A0
`
`NC
`
`48
`
`49
`
`50
`
`x72
`ECC
`
`A0
`
`CB2
`
`Pin
`#
`
`x64
`Non-Parity
`
`x72
`ECC
`
`140
`
`141
`
`142
`
`NC
`
`A10
`
`NC
`
`DM8,DQS17
`
`A10
`
`CB6
`
`3
`
`4
`
`5
`
`6
`
`7
`
`VSS
`
`DQ1
`
`VSS
`
`DQ1
`
`95
`
`96
`
`VDDQ
`
`VDDQ
`
` 51
`
`DQS0
`
`DQS0
`
`97 DM0,DQS9 DM0,DQS9
`
`52
`
`DQ2
`
`VDD
`
`DQ2
`
`VDD
`
`98
`
`99
`
`DQ6
`
`DQ7
`
`DQ6
`
`DQ7
`
`53
`
`54
`
`VSS
`
`NC
`
`BA1
`
`KEY
`
`VSS
`
`CB3
`
`BA1
`
`DQ32
`
`DQ32
`
`143
`
`144
`
`145
`
`146
`
`VDDQ
`
`NC
`
`KEY
`
`VSS
`
`DQ36
`
`VDDQ
`
`CB7
`
`VSS
`
`DQ36
`
`8
`
`9
`
`10
`
`11
`
`12
`
`DQ3
`
`DQ3
`
`NC,A15
`
`NC,A15
`
`100
`
`101
`
`VSS
`
`NC
`
`VSS
`
`NC
`
`RESET
`
`RESET
`
`102 NC,TEST
`
`NC,TEST
`
`VSS
`
`DQ8
`
`VSS
`
`DQ8
`
`103
`
`104
`
`NC
`
`NC
`
`VDDQ
`
`VDDQ
`
`DQ33
`
`DQS4
`
`DQ34
`
`VSS
`
`55
`
`56
`
`57
`
`58
`
`VDDQ
`
`DQ33
`
`DQS4
`
`147
`
`148
`
`DQ37
`
`VDD
`
`DQ37
`
`VDD
`
`DQ34
`
`149 DM4,DQS13 DM4,DQS13
`
`VSS
`
`150
`
`DQ38
`
`DQ38
`
`13
`
`14
`
`15
`
`16
`
`DQ9
`
`DQS1
`
`VDDQ
`
`DQ9
`
`DQS1
`
`VDDQ
`
`VDDQ
`
`DQ12
`
`DQ13
`
`105
`
`106
`
`DQ12
`
`DQ13
`
`59
`
`60
`
`BA0
`
`DQ35
`
`107 DM1,DQS10 DM1,DQS10 61
`
`DQ40
`
`NC (CK1)1
`
`NC (CK1)1
`
`108
`
`VDD
`
`VDD
`
`62
`
`VDDQ
`
`WE
`
`BA0
`
`DQ35
`
`DQ40
`
`VDDQ
`
`WE
`
`151
`
`152
`
`153
`
`154
`
`155
`
`DQ39
`
`VSS
`
`DQ44
`
`RAS
`
`DQ45
`
`DQ39
`
`VSS
`
`DQ44
`
`RAS
`
`DQ45
`
`NC (CK1)1
`
`NC (CK1)1
`
`17
`
`18
`
`19
`
`20
`
`21
`
`VSS
`
`DQ10
`
`DQ11
`
`CKE0
`
`109
`
`110
`
`111
`
`112
`
`DQ14
`
`DQ15
`
`CKE1
`
`VDDQ
`
`DQ14
`
`DQ15
`
`CKE1
`
`VDDQ
`
`VSS
`
`DQ10
`
`DQ11
`
`CKE0
`
` 113 NC(BA2)
`
`NC(BA2)
`
`63
`
`64
`
`65
`
`66
`
`67
`
`DQ41
`
`DQ41
`
`CAS
`
`VSS
`
`CAS
`
`VSS
`
`156
`
`157
`
`158
`
`VDDQ
`
`VDDQ
`
`S0
`
`S1
`
`S0
`
`S1
`
`DQS5
`
`DQS5
`
`159 DM5,DQS14 DM5,DQS14
`
`22
`
`23
`
`24
`
`25
`
`VDDQ
`
`DQ16
`
`DQ17
`
`DQS2
`
`VDDQ
`
`DQ16
`
`DQ17
`
`DQS2
`
`114
`
`115
`
`116
`
`117
`
`DQ20
`
`DQ20
`
`A12,NC
`
`A12,NC
`
`VSS
`
`DQ21
`
`VSS
`
`DQ21
`
`68
`
`69
`
`70
`
`71
`
`DQ42
`
`DQ43
`
`VDD
`
`DQ42
`
`DQ43
`
`VDD
`
`NC, S2
`
`NC, S2
`
`DQ48
`
`DQ48
`
`160
`
` 161
`
`162
`
`163
`
`164
`
`VSS
`
`DQ46
`
`DQ47
`
`VSS
`
`DQ46
`
`DQ47
`
`NC, S3
`
`NC, S3
`
`118
`
`A11
`
`A11
`
`72
`
`119 DM2,DQS11 DM2,DQS11 73
`
`DQ49
`
`26
`
`27
`
`28
`
`29
`
`30
`
`VSS
`
`A9
`
`DQ18
`
`A7
`
`VDDQ
`
`VSS
`
`A9
`
`DQ18
`
`A7
`
`VDDQ
`
`120
`
`121
`
`122
`
`VDD
`
`DQ22
`
`A8
`
`VDD
`
`DQ22
`
`A8
`
`74
`
`75
`
`76
`
`VSS
`
`DQ49
`
`VSS
`
`NC (CK2)1
`
`NC (CK2)1
`
`VDDQ
`
`DQ52
`
`DQ53
`
`VDDQ
`
`DQ52
`
`DQ53
`
`A13,NC
`
`A13,NC
`
`VDD
`
`VDD
`
`165
`
`166
`
`167
`
`168
`
`NC (CK2)1
`
`NC (CK2)1
`
`31
`
`32
`
`33
`
`34
`
`DQ19
`
`DQ19
`
`A5
`
`DQ24
`
`VSS
`
`A5
`
`DQ24
`
`VSS
`
`123
`
`124
`
`125
`
`126
`
`DQ23
`
`DQ23
`
`VSS
`
`A6
`
`VSS
`
`A6
`
`DQ28
`
`DQ28
`
`77
`
`78
`
`79
`
`80
`
`VDDQ
`
`DQS6
`
`DQ50
`
`DQ51
`
`VDDQ
`
`DQS6
`
`DQ50
`
`DQ51
`
`169 DM6,DQS15 DM6,DQS15
`
`170
`
`171
`
`172
`
`DQ54
`
`DQ55
`
`VDDQ
`
`DQ54
`
`DQ55
`
`VDDQ
`
` NC = No Connect; NU = Not Useable; DU = Do Not Use
`1. These pins reserved for unbuffered DDR DIMMs. Systems supporting both unbuffered and registered DIMMs may be connected to
`an active signal on the baseboard.
`2. The TEST pin is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
`
`Revision 1.3
`
`Release 12
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 15
`
`

`

`Jedec Standard No. 21-C
`
`DDR SDRAM Registered DIMM Design Specification
`
`Page 4.20.4–9
`
` Architecture
`
`184-Pin DDR SDRAM DIMM Pin Assignments
`
`Front Side (left side 1 - 52, right
`side 53 - 92)
`
`Back Side (left side 93 -144,
`right side 145 -184)
`
`Front Side (left side 1 - 52, right
`side 53 - 92)
`
`Back Side (left side 93 -144,
`right side 145 -184)
`
`Pin
`#
`
`x64
`Non-Parity
`
`35
`
`36
`
`37
`
`38
`
`39
`
`DQ25
`
`DQS3
`
`A4
`
`VDD
`
`DQ26
`
`DQ27
`
`x72
`ECC
`
`DQ25
`
`DQS3
`
`A4
`
`VDD
`
`DQ26
`
`DQ27
`
`Pin
`#
`
`x64
`Non-Parity
`
`127
`
`128
`
`DQ29
`
`VDDQ
`
`x72
`ECC
`
`DQ29
`
`VDDQ
`
`81
`
`82
`
`129 DM3,DQS12 DM3,DQS12 83
`
`A3
`
`A3
`
`DQ30
`
`DQ30
`
`130
`
`131
`
`132
`
`84
`
`85
`
`86
`
`Pin
`#
`
`x64
`Non-Parity
`
`x72
`ECC
`
`VSS
`
`VDDID
`
`DQ56
`
`DQ57
`
`VDD
`
`Pin
`#
`
`x64
`Non-Parity
`
`x72
`ECC
`
`173
`
`174
`
`175
`
`176
`
`NC,A14
`
`NC,A14
`
`DQ60
`
`DQ61
`
`VSS
`
`DQ60
`
`DQ61
`
`VSS
`
`177 DM7,DQS16 DM7,DQS16
`
`DQS7
`
`178
`
`DQ62
`
`DQ62
`
`VSS
`
`VDDID
`
`DQ56
`
`DQ57
`
`VDD
`
`DQS7
`
`40
`
`41
`
`42
`
`43
`
`44
`
`45
`
`46
`
`47
`
`A2
`
`VSS
`
`A1
`
`NC
`
`NC
`
`VDD
`
`NC
`
`A2
`
`VSS
`
`A1
`
`CB0
`
`CB1
`
`VDD
`
`DQS8
`
`133
`
`134
`
`135
`
`136
`
`137
`
`138
`
`139
`
`VSS
`
`DQ31
`
`NC
`
`NC
`
`VDDQ
`
`CK0
`
`CK0
`
`VSS
`
`VSS
`
`DQ31
`
`CB4
`
`CB5
`
`VDDQ
`
`CK0
`
`CK0
`
`VSS
`
`87
`
`88
`
`89
`
`90
`
`91
`
`92
`
`DQ58
`
`DQ59
`
`VSS
`
`NC
`
`SDA
`
`SCL
`
`DQ58
`
`DQ59
`
`VSS
`
`NC
`
`SDA
`
`SCL
`
`179
`
`180
`
`181
`
`182
`
`183
`
`184
`
`DQ63
`
`VDDQ
`
`SA0
`
`SA1
`
`SA2
`
`DQ63
`
`VDDQ
`
`SA0
`
`SA1
`
`SA2
`
`VDDSPD
`
`VDDSPD
`
` NC = No Connect; NU = Not Useable; DU = Do Not Use
`1. These pins reserved for unbuffered DDR DIMMs. Systems supporting both unbuffered and registered DIMMs may be connected to
`an active signal on the baseboard.
`2. The TEST pin is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
`
`Release 12
`
`Revision 1.3
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 16
`
`

`

`Page 4.20.4–10
`
` Architecture
`
`DDR SDRAM Registered DIMM Design Specification
`
`Jedec Standard No. 21-C
`
`Block Diagram: Raw Card Version A/L (x72 DIMM, populated as one physical bank of x8 DDR SDRAMs)
`
`CS
`
`DQS
`
`D0
`
`CS
`
`DQS
`
`D1
`
`CS
`
`DQS
`
`D2
`
`CS
`
`DQS
`
`D3
`
`DQS4
`DM4/DQS13
`
`DQS5
`DM5/DQS14
`
`DQS6
`DM6/DQS15
`
`DQS7
`DM7/DQS16
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`CS
`
`DQS
`
`D4
`
`CS
`
`DQS
`
`D5
`
`CS
`
`DQS
`
`D6
`
`CS
`
`DQS
`
`D7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`CS
`
`DQS
`
`D8
`
`SCL
`
`Serial PD
`
`SDA
`
`WP
`
`A0
`
`A1
`
`A2
`
`SA0 SA1 SA2
`
`VDDSPD
`VDDQ
`VDD
`VREF
`
`VSS
`VDDID
`
`Serial PD
`
`D0- D8
`
`D0-D8
`
`D0-D8
`
`D0-D8
`
`Strap: see Note 4
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`RS0
`DQS0
`DM0/DQS9
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQS1
`DM1/DQS10
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQS2
`DM2/DQS11
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQS3
`DM3/DQS12
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`CB0
`CB1
`CB2
`CB3
`CB4
`CB5
`CB6
`CB7
`
`R E G I S T E R
`
`DQS8
`DM8/DQS17
`
`S0
`
`BA0-BA1
`A0-A137
`RAS
`
`CAS
`
`CKE0
`WE
`
`RS0 -> CS: SDRAMs D0-D8
`
`RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D8
`RA0-RA137 -> A0-A137: SDRAMs D0-D8
`RRAS -> RAS: SDRAMs D0-D8
`
`RCAS -> CAS: SDRAMs D0-D8
`
`RCKE0 -> CKE: SDRAMs D0- D8
`RWE -> WE: SDRAMs D0-D8
`
`PCK
`PCK
`
`RESET
`
`CK0, CK0 --------- PLL*
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`Notes:
`1. DQ-to-I/O wiring may be changed within a byte.
`2. DQ/DQS/DM/CKE/S relationships must be main-
`tained as shown.
`3. DQ/DQS resistors should be 22 Ohms.
`4. VDDID strap connections (for memory device VDD,
`VDDQ):
`STRAP OUT (OPEN): VDD = VDDQ
`STRAP IN (VSS): VDD z VDDQ.
`5. SDRAM placement alternates between the back
`and front sides of the DIMM.
`6. Address and control resistors should be 22 Ohms.
`7. A13 is not wired for raw card A.
`
`Revision 1.2
`
`Release 11b
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 17
`
`

`

`Jedec Standard No. 21-C
`
`DDR SDRAM Registered DIMM Design Specification
`
`Page 4.20.4–11
`
` Architecture
`
`Block Diagram: Raw Card Version A/L (x64 DIMM, populated as one physical bank of x8 DDR SDRAMs)
`
`RS0
`DQS0
`DM0/DQS9
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DQS1
`DM1/DQS10
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`DQS2
`DM2/DQS11
`
`DQ16
`DQ17
`DQ18
`DQ19
`DQ20
`DQ21
`DQ22
`DQ23
`
`DQS3
`DM3/DQS12
`
`DQ24
`DQ25
`DQ26
`DQ27
`DQ28
`DQ29
`DQ30
`DQ31
`
`CS
`
`DQS
`
`D0
`
`CS
`
`DQS
`
`D1
`
`CS
`
`DQS
`
`D2
`
`CS
`
`DQS
`
`D3
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 7
`I/O 6
`I/O 1
`I/O 0
`I/O 5
`I/O 4
`I/O 3
`I/O 2
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS4
`DM4/DQS13
`
`DQS5
`DM5/DQS14
`
`DQS6
`DM6/DQS15
`
`DQS7
`DM7/DQS16
`
`CK0, CK0 --------- PLL*
`
`Serial PD
`
`* Wire per Clock Loading Table/Wiring Diagrams
`
`SCL
`
`WP
`
`A0
`
`A1 A2
`
`SA0 SA1 SA2
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`DQ48
`DQ49
`DQ50
`DQ51
`DQ52
`DQ53
`DQ54
`DQ55
`
`DQ56
`DQ57
`DQ58
`DQ59
`DQ60
`DQ61
`DQ62
`DQ63
`
`SDA
`
`CS
`
`DQS
`
`D4
`
`CS
`
`DQS
`
`D5
`
`CS
`
`DQS
`
`D6
`
`CS
`
`DQS
`
`D7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`VDDSPD
`
`VDDQ
`
`VDD
`
`VREF
`
`VSS
`
`VDDID
`
`Serial PD
`
`D0 - D7
`
`D0 - D7
`
`D0 - D7
`
`D0 - D7
`
`Strap: see Note 4
`
`Notes:
`1. DQ-to-I/O wiring may be changed within a byte.
`2. DQ/DQS/DM/CKE/S relationships must be maintained as
`shown.
`3. DQ/DQS/DM resistors should be 22 Ohms.
`4. VDDID strap connections (for memory device VDD, VDDQ):
`STRAP OUT (OPEN): VDD = VDDQ
`STRAP IN (VSS): VDD z VDDQ.
`5. SDRAM placement alternates between the back and front
`sides of the DIMM.
`6. Address and control resistors should be 22 Ohms.
`7. A13 is not wired for raw card A.
`
`RS0 -> CS: SDRAMs D0-D7
`RBA0-RBA1 -> BA0-BA1: SDRAMs D0-D7
`RA0-RA137 -> A0-A137: SDRAMs D0 - D7
`RRAS -> RAS: SDRAMs D0 - D7
`RCAS -> CAS: SDRAMs D0 - D7
`RCKE0 -> CKE: SDRAMs D0 - D7
`RWE -> WE: SDRAMs D0 - D7
`
`R E G I S T E R
`
`S0
`BA0-BA1
`A0-A137
`RAS
`CAS
`CKE0
`WE
`
`PCK
`PCK
`
`RESET
`
`Release 11b
`
`Revision 1.2
`
`Micron Technology Inc. et al.
`Ex. 1017, p. 18
`
`

`

`Page 4.20.4–12
`
` Architecture
`
`DDR SDRAM Registered DIMM Design Specification
`
`Jedec Standard No. 21-C
`
`Block Diagram: Raw Card Version A/L (x72 DIMM, populated as two physical banks of x8 DDR SDRAMs)
`
`RS1
`RS0
`DQS0
`DM0/DQS9
`
`CS
`
`DQS
`
`D0
`
`DQ0
`DQ1
`DQ2
`DQ3
`DQ4
`DQ5
`DQ6
`DQ7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS1
`DM1/DQS10
`
`DM
`
`CS
`
`DQS
`
`D1
`
`DQ8
`DQ9
`DQ10
`DQ11
`DQ12
`DQ13
`DQ14
`DQ15
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DQS4
`DM4/DQS13
`
`DM
`
`CS
`
`DQS
`
`DQ32
`DQ33
`DQ34
`DQ35
`DQ36
`DQ37
`DQ38
`DQ39
`
`DQS5
`DM5/DQS14
`
`DQ40
`DQ41
`DQ42
`DQ43
`DQ44
`DQ45
`DQ46
`DQ47
`
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`DM
`I/O 0
`I/O 1
`I/O 2
`I/O 3
`I/O 4
`I/O 5
`I/O 6
`I/O 7
`
`D4
`
`CS
`
`DQS
`
`D5
`
`CS
`
`DQS
`
`D9
`
`CS
`
`DQS
`
`D10
`
`D