11111111111111111111111111111111111111111111111111111111111111111111111111II
`
`(12) United States Patent (cid:9)
`Kim et at. (cid:9)
`
`(lo) Patent No.: (cid:9)
`(45) Date of Patent: (cid:9)
`
`US 6,184,701 Bi
`Feb. 6, 2001
`
`(54) INTEGRATED CIRCUIT DEVICES HAVING
`METASTABILITY PROTECTION CIRCUITS
`THEREIN
`
`(75) Inventors: Chang-hyun Kim, Kyungki-do;
`Ki-whan Song, Seoul, both of (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd. (KR)
`
`(*) Notice: (cid:9)
`
`Under 35 U.S.C. 154(b), the term of this
`patent shall be extended for 0 days.
`
`(21) Appl. No.: 09/320,889
`
`(22) Filed: (cid:9)
`
`May 27, 1999
`
`(30) (cid:9)
`
`Foreign Application Priority Data
`
`May 29, 1998 (cid:9)
`
`(KR) ................................................. 98-19805
`
`(51) Int. Cl.7 ..................................................... H03K 17/16
`(52) U.S. Cl ................................. 326/21; 326/26; 327/198
`(58) (cid:9) Field of Search .................................. 326/21, 26-27,
`326/9, 13, 94, 83, 86; 327/53, 198, 312,
`321, 328
`
`(56) (cid:9)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,081,377 * (cid:9) 1/1992 Freyman .............................. 327/198
`5,166,561 * 11/1992 Okura ................................... 327/312
`5,187,385 * (cid:9) 2/1993 Koike ................................... 327/198
`5,256,914 * 10/1993 Boomer .................................. 326/26
`5,754,070 * 5/1998 Baumann et al . ................... 327/198
`5,789,945 * 8/1998 Cline ...................................... 326/94
`
`FOREIGN PATENT DOCUMENTS
`
`OTHER PUBLICATIONS
`Rabaey, "Digital Integrated Circuits: A Design Perspec-
`tive", Prentice Hall, 1996, pp. 334, 534-535.
`Notice to Submit Response, Korean Application No.
`10-1998-0019805, Jul. 31, 2000.
`
`* cited by examiner
`Primary Examiner Jon Santamauro
`(74) Attorney, Agent, or Firm—Myers Bigel Sibley &
`Sajovec
`(57) (cid:9)
`
`ABSTRACT
`
`Integrated circuit devices having metastability protection
`circuits therein include a main active circuit and a metasta-
`bility detection/prevention circuit. The main active circuit
`may comprise a comparator, a sense amplifier, a differential
`amplifier or a voltage generating circuit, for example. The
`metastability detection/prevention circuit performs the func-
`tion of detecting whether an output of the main active circuit
`has been disposed in a metastable state for a duration in
`excess of a transition duration. The output of the main active
`circuit may be considered as being in a metastable state if a
`potential of the output signal equals VMS, where VMS is in a
`range between VIL, and VIH. If the output signal has been in
`a metastable state for a duration in excess of the transition
`duration, then the metastability detection/prevention circuit
`will generate a control signal at a designated logic level. This
`control signal is provided as an input to the main active
`circuit and causes the output of the main active circuit to be
`driven out of the metastable state (i.e., to a logic 1 or 0 level).
`In this manner, prolonged metastability can be prevented
`even if the values of the input signals to the main active
`circuit would otherwise dispose the output in a metastable
`state.
`
`2-100414 (cid:9)
`
`4/1990 (JP)
`
`13 Claims, 4 Drawing Sheets
`
`-------------------------------------------------------------
`--------------------
`VDD (cid:9)
`PDNB~i
`
`P1 (cid:9)
`
`—11 (cid:9)
`J L, (cid:9)
`P2 M1 (cid:9)
`
`A (cid:9)
`
`13
`
`------ J
`I1 (cid:9)
`I2 (cid:9)
`
`I3
`
`X10
`
`
`POUT
`
`PIN1 (cid:9)
`
`N2 (cid:9)
`
`N3
`
`~ ' (cid:9)
`BIAS '' (cid:9)
`I (cid:9)
`I (cid:9)
`
`I (cid:9)
`
`N 1
`
`PIN2 (cid:9)
`
`VSS (cid:9)
`------------- (cid:9)
`
`I r-
`I
`I
`
`-
`
`N4 (cid:9)
`
`II
`
`VSS
`
`PCON
`
`PDICB
`
`HOLDING (cid:9)
`CIRCUIT (cid:9)
`
`SENSING
`CIRCUIT
`
`VSS PDS U (cid:9)
`A (cid:9)
`25 (cid:9)
`L---- (cid:9)
`PDN
`L________________________________J
`
`21
`
`20
`
`Micron Technology Inc. et al.
`Ex. 1008, p. 1
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`Feb. 6, 2001 (cid:9)
`
`Sheet 1 of 4 (cid:9)
`
`US 6,184,701 B1
`
`FIG. 1
`
`PIN1
`PIN2
`
`10
`
`MAIN CIRCUIT
`
`POUT
`
`METASTABILITY
`DETECTION—
`PREVENTION
`CIRCUIT (cid:9)
`
`20
`
`PCON
`
`Micron Technology Inc. et al.
`Ex. 1008, p. 2
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`

`FIG 2
`
`r --------------------------------
`
`' (cid:9)
`I (cid:9)
`I (cid:9)
`
`I (cid:9)
`I (cid:9)
`
`I (cid:9)
`' (cid:9)
`' (cid:9)
`
`PIN 1
`
`i (cid:9)
`r (cid:9)
`I (cid:9)
`
`VDD (cid:9)
`
`PDNB~
`I
`I
`
`P1 (cid:9)
`
`P2 M1
`
`I (cid:9)
`I (cid:9)
`
`I
`I (cid:9)
`I (cid:9)
`
`I
`I
`
`I
`I
`
`I
`
`11
`
`13
`
`
`
`I1 (cid:9)
`
`I2 (cid:9)
`
`I3
`
`, (cid:9)
`, (cid:9)
`L---------------J
`
`I
`
`POUT
`
`-------- (cid:9)
`
`r -
`
`PCON
`
`vss
`--------~
`
`Ia
`
`-- (cid:9)
`
`-----------------------i
`
`---------- (cid:9)
`
`----------
`
`N 4
`
`,I (cid:9)
`
`HOLDING
`I CIRCUIT (cid:9)
`I
`
`PDICB (cid:9)
`
`II
`
`SENSING LI
`CIRCUIT I
`
`VSS PDS 23 (cid:9)
`L.----J~ 25 (cid:9)
`
`PDN
`L------------------- (cid:9)
`
`21 (cid:9)
`
`I X20
`
`J
`
`Micron Technology Inc. et al.
`Ex. 1008, p. 3
`
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`Feb. 6, 2001 (cid:9)
`
`Sheet 3 of 4
`
`US 6,184,701 B1
`
`FIG. 3
`
`VDD
`
`~21
`
`POUT
`
`vss
`
`FIG. 4
`
`VDD
`
`PDICB >—H
`
`PDN>--I
`
`vss
`
`23
`
`PDS
`
`Micron Technology Inc. et al.
`Ex. 1008, p. 4
`
`(cid:9)
`(cid:9)
`

`

`U.S. Patent (cid:9)
`
`Feb. 6, 2001 (cid:9)
`
`Sheet 4 of 4 (cid:9)
`
`US 6,184,701 B1
`
`FIG. 5
`
`n (cid:9)
`
`h
`
`vcc
`
`VSS
`vcc
`
`VSS
`
`vcc
`
`vsS
`
`vcc
`
`vsS
`
`vcc
`
`vsS
`
`Si
`
`:S2
`
`)ICB
`
`K
`
`'CON
`
`VSS
`
`POUT
`
`VCC
`
`Micron Technology Inc. et al.
`Ex. 1008, p. 5
`
`

`

`US 6,184,701 B1
`
`INTEGRATED CIRCUIT DEVICES HAVING
`METASTABILITY PROTECTION CIRCUITS
`THEREIN
`
`RELATED APPLICATION
`
`5
`
`2
`FIG. 4 is an electrical schematic of an embodiment of a
`holding circuit of FIG. 2.
`FIG. 5 is a diagram which illustrates operation of the
`device of FIG. 2.
`
`DESCRIPTION OF PREFERRED
`EMBODIMENTS
`
`SUMMARY OF THE INVENTION
`
`It is therefore an object of the present invention to provide
`integrated circuit devices that have reduced susceptibility to
`metastable operation.
`These and other objects, advantages and features of the
`present invention are provided by integrated circuit devices
`which include a main active circuit and a metastability
`detection/prevention circuit. The main active circuit may
`comprise a comparator, a sense amplifier, a differential
`amplifier or a voltage generating circuit, for example. The
`metastability detection/prevention circuit performs the func-
`tion of detecting whether an output of the main active circuit
`has been disposed in a metastable state for a duration in
`excess of a transition duration. The output of the main active
`circuit may be considered as being in a metastable state if a
`potential of the output signal (VPOU) equals VMS, where
`VMS is in a range between VIL and VJH. If the output signal
`has been in a metastable state for a duration in excess of the
`transition duration, then the metastability detection/
`prevention circuit will generate a control signal at a desig-
`nated logic level. This control signal is provided as an input
`to the main active circuit and causes the output of the main
`active circuit to be driven out of the metastable state (i.e., to
`a logic 1 or 0 level). In this manner, prolonged metastability
`can be prevented even if the values of the input signals to the
`main active circuit would otherwise dispose the output in a
`metastable state.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of an integrated circuit device
`according to an embodiment of the present invention.
`FIG. 2 is an electrical schematic of the device of FIG. 1.
`FIG. 3 is an electrical schematic of an embodiment of a
`sensing circuit of FIG. 2.
`
`This application is related to Korean Application No.
`98-19805, filed May 29, 1998, the disclosure of which is
`hereby incorporated herein by reference.
`
`FIELD OF THE INVENTION
`
`The present invention relates to integrated circuit devices,
`and more particularly to integrated circuit devices which
`may be prone to generating metastable output signals.
`
`BACKGROUND OF THE INVENTION
`
`The present invention will now be described more fully
`10 hereinafter with reference to the accompanying drawings, in
`which preferred embodiments of the invention are shown.
`This invention may, however, be embodied in different
`forms and should not be construed as limited to the embodi-
`ments set forth herein. Rather, these embodiments are pro-
`15 vided so that this disclosure will be thorough and complete,
`and will fully convey the scope of the invention to those
`skilled in the art. Like numbers refer to like elements
`Integrated circuit devices such as comparators, sense
`throughout and signal lines and signals thereon may be
`amplifiers, differential amplifiers and reference voltage gen-
`referred to by the same reference symbols.
`erating circuits may be susceptible to generating output 20
`Referring now to FIGS. 1-2, a preferred embodiment of
`signals that are not always in logic 1 or 0 states. In particular,
`an integrated circuit device according to an embodiment of
`a differential amplifier which receives input signals at simi-
`the present invention includes a main active circuit 10 and
`lar analog levels may be prone to generating an output signal
`a metastability detection/prevention circuit 20, connected as
`in a metastable state (i.e., where the potential of the output
`illustrated. The main active circuit 10, which may be respon-
`signal is greater than a maximum logic 0 level (V1L) and less 25 sive to first and second input signals PINT and PIN2, may
`than a minimum logic 1 level (VJH)). Such generation of
`comprise a comparator, a sense amplifier, a differential
`metastable outputs may result in device failure if devices
`amplifier 11 (as illustrated by FIG. 2) or a voltage generating
`that are responsive to the output signal interpret the state of
`circuit, for example. The circuit 10 may also perform the
`the output signal incorrectly. Accordingly, there is a need to
`function of converting an analog level signal to a CMOS
`develop circuits having less susceptibility to metastable 30 level signal. Alternatively, the circuit 10 may comprise a
`output generation.
`data input buffer an address input buffer a data output buffer
`or an analog-to-digital converter, for example. As explained
`more fully hereinbelow with respect to FIG. 2, the metasta-
`bility detection/prevention circuit 20 preferably performs
`35 the function of detecting whether the output POUT of the
`main active circuit 10 has been disposed in a metastable state
`for a duration in excess of a transition duration. As described
`more fully hereinbelow, the length of the transition duration
`is dependent on the value of a holding capacitor Cl at an
`40 output of a sensing circuit (see, e.g., FIG. 3). Here, a signal
`at the output POUT of the main active circuit 10 may be
`considered as being in a metastable state if a potential of the
`signal V 0 equals VMS, where VMS is in a range between
`VJL and VJH. These aspects of the metastability phenomenon
`45 are more fully described at pages 334 and 534-535 of a
`textbook by Jan M. Rabaey entitled "Digital Integrated
`Circuits: A Design Perspective", Prentice Hall (1996). If the
`signal POUT has been in a metastable state for a duration in
`excess of the transition duration, then the metastability
`50 detection/prevention circuit 20 will generate a control signal
`PCON. This control signal PCON is provided as an input to
`the main active circuit 10 and causes the output POUT of the
`main active circuit 10 to be driven to a logic 1 level (or logic
`0 level), irrespective of the values of the input signals PINT
`55 and PIN2. In this manner, prolonged metastability can be
`prevented even if the values of the input signals would
`otherwise dispose the output POUT in a metastable state.
`Referring now specifically to the device of FIG. 2, the
`main active device 10 is provided as a differential amplifier
`60 11 having an output connected to a buffer circuit 13. As
`illustrated, the differential amplifier 11 is responsive to two
`input signals PINT and PIN2 and comprises a plurality of
`NMOS transistors N1—N3 and a plurality of PMOS transis-
`tors P1 and P2. A fixed bias signal BIAS is provided to the
`65 gate electrode of NMOS transistor Ni which acts as a
`current source. According to a preferred aspect of the active
`device 10, a PMOS pull-up transistor Ml is provided at the
`
`Micron Technology Inc. et al.
`Ex. 1008, p. 6
`
`

`

`output of the differential amplifier at node A. This PMOS
`pull-up transistor is responsive to a complementary main
`circuit control signal PDNB (i.e., /PDN) which acts as a first
`initialization signal. When the first initialization signal
`PDNB is driven to a logic 0 level, node A becomes initial-
`ized at a logic 1 level. Because the buffer circuit 13 com-
`prises a odd-numbered string of inverters (I1–I3), the output
`POUT is driven to a logic 0 level whenever the first
`initialization signal PDNB is driven to a logic 0 level.
`The active device also includes a metastable control input
`PCON which enables the output POUT to be driven from a
`metastable state (where Vpo –VMS) to a logic 1 state
`whenever the metastable control input PCON is pulled down
`to Vss. Alternatively, by changing the number of inverters in
`the buffer circuit 13, the output POUT can be driven to a
`logic 0 state whenever a metastable state is detected.
`According to a preferred aspect of the present invention,
`the metastable control input PCON can be disposed in either
`a logic 0 state (or logic 1 state) or a high impedance state.
`In particular, the value of the metastable control input PCON
`is determined by the metastability detection circuit 20. As
`illustrated by FIG. 2, the metastability detection circuit 20 is
`responsive to the output POUT of the active device 10 and
`drives the metastable control input PCON to a predeter-
`mined logic state if the output POUT is disposed in the
`metastable state for a duration in excess of a transition
`duration. The preferred metastability detection circuit 20
`comprises a sensing circuit 21, a holding circuit 23 and a
`compensating device 25. The sensing circuit 21 is respon-
`sive to the output POUT of the active device 10 and
`generates a sensing signal PDICB. The holding circuit 23 is
`responsive to the sensing signal PDICB as well as a main
`circuit control signal PDN which acts as a second initial-
`ization signal. The holding circuit 23 also generates a state
`indication signal PDS. This state indication signal PDS is
`provided to the compensating device 25 which may com-
`prise a single NMOS pull-down transistor N4. When the
`state indication signal PDS is driven to a logic 1 state, the
`NMOS pull-down transistor N4 will turn on and pull the
`metastable control input PCON down to a logic 0 state (e.g.,
`Vss).
`Referring now to FIG. 3, a preferred configuration of the
`sensing circuit 21 is illustrated. This sensing circuit 21
`comprises a first CMOS inverter formed by PMOS pull-up
`transistor P3 and NMOS pull-down transistor N5, and a
`second CMOS inverter 33. The second CMOS inverter 33
`comprises PMOS pull-up transistor P4 and NMOS pull-
`down transistor N6. An inverter 14 is also provided at the
`output of the first CMOS inverter. The output of the inverter
`14 and the output of the second CMOS inverter 33 are
`provided as inputs to NAND gate 35. The sensing signal line
`PDICB at the output of the NAND gate 35 is only driven to
`a logic 0 state when both inputs thereto (i.e., signal lines
`RES1 and RES2) are established at logic 1 levels. A capaci-
`tor Cl is also provided to prevent normal 0-1 or 1-0
`transitions or noise at the output POUT of the active device
`10 from inadvertently driving the sensing signal PDICB to
`a logic 0 level. Nonetheless, when the output POUT is
`disposed in a metastable state for a duration in excess of a
`transition duration, the output of the first CMOS inverter
`will be driven to a logic 0 level and the output of the second
`CMOS inverter will be driven to a logic 1 level. This is
`achieved by designing PMOS pull-up transistor P3 to have
`a higher resistance than NMOS pull-down transistor N5
`when VJL<V po <VJH (i.e., when the output POUT is
`metastable), and also by designing NMOS pull-down tran-
`sistor N6 to have a higher resistance than PMOS pull-up
`
`30
`
`35 (cid:9)
`
`US 6,184,701 B1
`
`n
`transistor P4 when the output POUT is metastable.
`Accordingly, the sensing circuit 21 can detect when the
`output POUT is metastable, by driving both signal lines
`RES1 and RES2 to logic 1 levels and by driving the sensing
`5 signal line PDICB to a logic 0 level.
`Referring now to FIG. 4, the holding circuit receives the
`sensing signal PDICB as an input and generates a state
`indication signal PDS at a logic 1 level when PDICB is at a
`logic 0 level. This is achieved using the PMOS pull-up
`10 transistor P5 and a noninverting latch circuit comprising
`inverters 15-17. A logic 1 state indication signal PDS will
`then cause NMOS pull-down transistor N4 to turn on and
`pull the control signal line PCON to a logic 0 level. As
`described above, by pulling the control signal line PCON to
`a logic 0 level, the output POUT can be driven from the
`1s metastability state to a logic 1 state automatically. The state
`indication signal line PDS can also be clamped at a logic 0
`level by disposing the main circuit control signal line PDN
`in a logic 1 state. When this occurs, the NMOS pull down
`transistor N7 will turn on and pull the input of inverter 15 to
`20 a logic 0 level. The complementary main circuit control
`signal line PDNB will also be disposed in a logic 0 state so
`that node A can be held at a logic 1 level and the output
`POUT can be held at a logic 0 level.
`Referring now to FIG. 5, the above described operation of
`25 a preferred embodiment of the present invention is illus-
`trated by a plot on the y-axis of signal line voltages for
`signals RES1, RES2, PDICB, PDS and PCON versus the
`output voltage POUT on the x-axis. As illustrated, the output
`POUT is in a metastable state when the potential of the
`output POUT is in the range between "a" and "b". When this
`metastable state is present, the sensing signal line PDICB
`will be driven to a logic 0 level and the state indication signal
`line PDS will be driven to a logic 1 level.
`In the drawings and specification, there have been dis-
`closed typical preferred embodiments of the invention and,
`although specific terms are employed, they are used in a
`generic and descriptive sense only and not for purposes of
`limitation, the scope of the invention being set forth in the
`40 following claims.
`That which is claimed is:
`1. An integrated circuit device, comprising:
`an active device having a metastable control input and an
`output which is driven from a metastable state to a first
`or second logic state whenever the metastable control
`input is in the first logic state; and
`a metastability detection circuit that is responsive to the
`output of said active device and drives the metastable
`control input to the first logic state if the output of said
`active device is disposed in the metastable state when
`said active device is not in an active state.
`2. The device of claim 1, wherein said metastability
`detection circuit comprises:
`a sensing circuit having an input electrically connected to
`the output of said active device; and
`a holding circuit having a first input electrically connected
`to an output of said sensing circuit.
`3. The device of claim 2, wherein said active device
`comprises a first transistor having a gate electrode that is
`6o responsive to a first initialization signal; and wherein a
`second input of said holding circuit is responsive to a second
`initialization signal.
`4. The device of claim 3, wherein the first and second
`initialization signals are complementary versions of each
`65 other.
`5. The device of claim 4, wherein said active device has
`an intermediate output node; wherein the first transistor is
`
`ss (cid:9)
`
`45 (cid:9)
`
`so (cid:9)
`
`Micron Technology Inc. et al.
`Ex. 1008, p. 7
`
`

`

`US 6,184,701 B1
`
`5
`electrically connected in series between the intermediate
`output node and a first reference potential; and wherein said
`metastability detection circuit comprises a second transistor
`electrically connected in series between the intermediate
`output node and a second reference potential.
`6. The device of claim 5, wherein a gate electrode of said
`second transistor is electrically connected to an output of
`said holding circuit.
`7. The device of claim 2, wherein said sensing circuit
`comprises:
`a NAND gate having first and second inputs;
`a first CMOS inverter that is biased to pull-down an
`output thereof if an input thereto is in the metastable
`state; and
`a second CMOS inverter that is biased to pull-up an
`output thereof if an input thereto is in the metastable
`state.
`8. The device of claim 7, wherein inputs of said first and
`second CMOS inverters are electrically connected together
`and to the output of said active device.
`9. The device of claim 3, further comprising a third
`inverter having an input electrically coupled to the output of
`said first CMOS inverter; and wherein the first and second
`inputs of said NAND gate are electrically connected to the
`output of said third inverter and the output of said second
`CMOS inverter, respectively.
`10. The device of claim 6, wherein said active device
`comprises a buffering circuit having an input electrically
`
`10 (cid:9)
`
`15 (cid:9)
`
`6
`connected to the intermediate output node; and wherein an
`output of said buffering circuit is the output of said active
`device.
`11. The device of claim 6, wherein said first transistor
`5 comprises a PMOS transistor; and wherein said second
`transistor comprises an NMOS transistor.
`12. The device of claim 1, wherein said metastability
`detection circuit comprises a sensing circuit having an input
`electrically connected to the output of said active device.
`13. The device of claim 12, wherein said sensing circuit
`comprises:
`a first switching means for generating a first signal in
`response to a first voltage level of the output of said
`active device when said first voltage level is higher than
`a predetermined first reference voltage;
`a second switching means for generating a second signal
`in response to a second voltage level of the output of
`said active device when said second voltage level is
`higher than a predetermined second reference voltage;
`and
`a third switching means for generating a third signal in
`response to the first signal and the second signals when
`the output of said active device has a voltage higher
`than the first reference voltage and lower than the
`second reference voltage.
`
`20 (cid:9)
`
`25 (cid:9)
`
`Micron Technology Inc. et al.
`Ex. 1008, p. 8
`
`