UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SAMSUNG ELECTRONICS CO., LTD.,
`Petitioner,
`v.
`NETLIST, INC.,
`Patent Owner.
`
`Case IPR2023-00847
`Patent 10,268,608
`
`DECLARATION OF DR. ROBERT WEDIG
`REGARDING U.S. PATENT NO. 10,268,608
`
`Micron Technology Inc. et al.
`Ex. 1003, p. i
`
`

`

`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
`
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`INTRODUCTION ......................................................................................... 1
`A.
`Engagement ........................................................................................... 1
`B.
`Background and Qualifications ............................................................. 1
`C.
`Compensation and Prior Testimony ...................................................... 2
`D.
`Information Considered ......................................................................... 3
`LEGAL STANDARDS FOR PATENTABILITY ...................................... 3
`A.
`Anticipation ........................................................................................... 5
`B.
`Obviousness ........................................................................................... 6
`III. THE ’608 PATENT ..................................................................................... 12
`A.
`Effective Filing Date ........................................................................... 12
`B.
`Person of Ordinary Skill in the Art ..................................................... 12
`C.
`Overview of the ’608 Patent ................................................................ 13
`D.
`The Prosecution History ...................................................................... 19
`1. The 599 Application (The ’632 Patent) ........................................19
`2. The 993 Application (The ’587 Patent) ........................................21
`3.
`IPR2017-00730 by SK hynix against the ’632 Patent
`(institution denied) ........................................................................22
`4. The 064 Application (The ’035 Patent) ........................................23
`5. The 076 Application (The ’608 Patent) ........................................26
`6. The 151 Application (The ’506 Patent) ........................................27
`7.
`IPR2022-00236 by Micron against the ‘035 Patent
`(instituted) .....................................................................................29
`IPR2022-00237 by Micron against the ‘608 Patent
`(institution denied) ........................................................................30
`IPR2022-00711 by Samsung against the ‘506 Patent
`(instituted) .....................................................................................31
`Challenged Claims .............................................................................. 33
`Construction of Terms Used in the Patent Claims .............................. 34
`
`8.
`
`9.
`
`E.
`F.
`
`ii
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`Micron Technology Inc. et al.
`Ex. 1003, p. ii
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
`
`1. “memory operation” ......................................................................35
`2. “memory module” ..........................................................................36
`3. “memory controller” .....................................................................37
`4. “memory bus” ................................................................................37
`5. “system command signals” ............................................................37
`6. “module command signals” ..........................................................38
`7. “module control signals” ..............................................................39
`8. “metastability” ...............................................................................40
`IV. OVERVIEW OF THE PRIOR ART ......................................................... 41
`A.
`U.S. Publication No. 2010/0312956 to Hiraishi (EX1005) ................ 41
`B.
`U.S. Patent No. 8,020,022 to Tokuhiro (EX1006) .............................. 51
`C.
`U.S. Patent Publication No. 2006/0277355 to Ellsberry
`(EX1007) ............................................................................................. 54
`U.S. Patent Publication No. 2007/0008791 to Butt (EX1029) ........... 55
`D.
`U.S. Patent No. 6,184,701 to Kim (EX1008) ..................................... 60
`E.
`COMPARISON OF THE PRIOR ART TO THE CLAIMS ................... 61
`A.
`Claims 1-12 are Obvious Over Haraishi in Combination with
`Butt or in further view of Kim and/or Ellsberry ................................. 61
`1. Claim 1 ..........................................................................................65
`a) 1[pre]: “A memory module operable to communicate
`with a memory controller via a memory bus, the
`memory bus including signal lines, the signal lines
`including a set of control/address signal lines and a
`plurality of sets of data/strobe signal lines, the memory
`module comprising” ...............................................................65
`b) 1[a]: “a module board having edge connections for
`coupling to respective signal lines in the memory bus” ........69
`c) 1[b]: “a module control device mounted on the module
`board and configured to receive system command
`signals for memory operations via the set of
`control/address signal lines and to output module
`command signals and module control signals in
`
`V.
`
`iii
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`Micron Technology Inc. et al.
`Ex. 1003, p. iii
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
`
`response to the system command signals, the module
`control device being further configured to receive a
`system clock signal and output a module clock signal”.........73
`d) 1[c]: “memory devices mounted on the module board
`and configured to receive the module command signals
`and the module clock signal, and to perform the
`memory operations in response to the module command
`signals, the memory devices including a plurality of
`sets of memory devices corresponding to respective sets
`of the plurality of sets of data/strobe signal lines” .................81
`e) 1[d]: “a plurality of buffer circuits corresponding to
`respective sets of the plurality of sets of data/strobe
`signal lines” ............................................................................87
`f) 1[e]: “wherein each respective buffer circuit of the
`plurality of buffer circuits is mounted on the module
`board, coupled between a respective set of data/strobe
`signal lines and a respective set of memory devices, and
`configured to receive the module control signals and
`the module clock signal, the each respective buffer
`circuit including a data path corresponding to each data
`signal line in the respective set of data/strobe signal
`lines, and a command processing circuit configured to
`decode the module control signals and to control the
`data path in accordance with the module control signals
`and the module clock signal” .................................................93
`g) 1[f]: “wherein the data path corresponding to the each
`data signal line includes at least one tristate buffer
`controlled by the command processing circuit and a
`delay circuit configured to delay a signal through the
`data path by an amount determined by the command
`processing circuit in response to at least one of the
`module control signals” ........................................................108
`2. Claim 2 ........................................................................................136
`a) 2[a]: “The memory module of claim 1, wherein the
`memory operations include a first memory operation
`and a second memory operation subsequent to the first
`memory operation,” ..............................................................136
`
`iv
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`Micron Technology Inc. et al.
`Ex. 1003, p. iv
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`b) 2[b]: “wherein the command signals include a first set
`of command signals for the first memory operation and
`a second set of command signals for the second
`memory operation,” ..............................................................141
`c) 2[c]: “wherein the module control signals include a first
`set of module control signals output by the module
`control device in response to the first set of command
`signals and a second set of module control signals
`output by the module control device in response to the
`second set of command signals,” .........................................143
`d) 2[d]: “wherein the at least one of the module control
`signals include at least one of the first set of module
`control signals, and wherein the signal through the data
`path is a signal associated with the second memory
`operation.” ............................................................................146
`3. Claim 3 ........................................................................................148
`a) 3[a]: “The memory module of claim 2, wherein the
`memory devices are arranged in a plurality of ranks and
`the respective set of memory devices include at least
`one memory device from each of the plurality of
`ranks,” ...................................................................................148
`b) 3[b]: “wherein the module command signals include a
`first set of module command signals output by the
`module control device in response to the first set of
`command signals and a second set of module command
`signals output by the module control device in response
`to the second set of command signals, and” ........................149
`c) 3[c]: “wherein the second set of module command
`signals include chip select signals that select the at least
`one memory device in the respective set of memory
`devices from one of the plurality of ranks to perform
`the second memory operation.” ............................................151
`4. Claim 4 ........................................................................................153
`5. Claim 5 is obvious over Hiraishi and Butt in further view of
`Ellsberry ......................................................................................154
`
`v
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`Micron Technology Inc. et al.
`Ex. 1003, p. v
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
`
`6. Claim 6 is obvious over Hiraishi and Butt in further view of
`Kim ..............................................................................................158
`7. Claim 7 is obvious over Hiraishi and Butt in further view of
`Kim ..............................................................................................164
`8. Claim 8 is obvious over Hiraishi and Butt in further view of
`Kim and Ellsberry .......................................................................165
`9. Claim 9 ........................................................................................165
`a) 9[a]: “The memory module of claim 1, wherein the
`each respective buffer circuit further includes a clock
`regeneration circuit configured to generate a local clock
`signal having a programmable phase relationship with
`the module clock signal,” .....................................................166
`b) 9[b]: “wherein the each respective buffer circuit is
`further configured to output the local clock signal to the
`respective set of memory devices.” ......................................168
`10. Claim 10 ......................................................................................172
`11. Claim 11 ......................................................................................179
`12. Claim 12 is obvious over Hiraishi and Butt in further view
`of Ellsberry ..................................................................................179
`Claims 1-12 are Obvious Over Hiraishi and Butt in View of
`Tokuhiro ............................................................................................ 180
`1. Tokuhiro’s teaching ....................................................................180
`2. Motivations to Combine Tokuhiro and Hiraishi (in view of
`Butt) .............................................................................................188
`a) First motivation: Tokuhiro teaches calculating read
`delays based on the delays for write operations, which
`is more efficient than Hiraishi’s technique of
`performing read leveling independent of the write
`delays ....................................................................................189
`b) Second motivation: Tokuhiro provides simple
`techniques for removing fly-by delays, while Hiraishi
`does not disclose how its memory controller re-times
`read data received with fly-by delays ...................................199
`
`B.
`
`vi
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`Micron Technology Inc. et al.
`Ex. 1003, p. vi
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`b)
`
`c) Third motivation: Tokuhiro discloses simple solutions
`for fly-by delays greater than one clock cycle, while
`Hiraishi does not ...................................................................202
`3. The combination of Hiraishi in view of Butt and in further
`view of Tokuhiro relied upon here ..............................................209
`a)
`It would have been obvious to implement Tokuhiro’s
`delay elements in Hiraishi’s data register buffers ................209
`It would have been obvious for either of Hiraishi’s
`memory controller and module controller to program
`Tokuhiro’s delay elements in Hiraishi’s data buffers ..........217
`4. Claim 1 ........................................................................................230
`5. Claim 2 ........................................................................................234
`a) 2[a]: “The memory module of claim 1, wherein the
`memory operations include a first memory operation
`and a second memory operation subsequent to the first
`memory operation,” ..............................................................234
`b) 2[b]: “wherein the command signals include a first set
`of command signals for the first memory operation and
`a second set of command signals for the second
`memory operation,” ..............................................................236
`c) 2[c]: “wherein the module control signals include a first
`set of module control signals output by the module
`control device in response to the first set of command
`signals and a second set of module control signals
`output by the module control device in response to the
`second set of command signals,” .........................................238
`d) 2[d]: “wherein the at least one of the module control
`signals include at least one of the first set of module
`control signals, and wherein the signal through the data
`path is a signal associated with the second memory
`operation.” ............................................................................240
`6. Claims 3-12 .................................................................................241
`Claims 1-12 are Obvious Over Haraishi and Butt in View
`Tokuhiro in Further View of Ellsberry and/or Kim .......................... 242
`
`C.
`
`vii
`
`Micron Technology Inc. et al.
`Ex. 1003, p. vii
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`

`

`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
`
`I.
`
`INTRODUCTION
`A.
`Engagement
`1.
`I have been retained by counsel for Samsung Electronics Co., Ltd. as
`
`an expert witness in the above-captioned proceeding. I have been asked to provide
`
`my opinion about the state of the art of the technology described in U.S. Patent No.
`
`10,268,608 (“the ’608 Patent”) (EX1001) and on the patentability of claims 1-12 of
`
`this patent.
`
`B.
`2.
`
`Background and Qualifications
`I received a Bachelor of Electrical Engineering degree from the
`
`University of Dayton in 1977. I received a Master of Science degree in Electrical
`
`Engineering from the University of Southern California in 1979, and received a
`
`Ph.D. in Electrical Engineering from Stanford University in 1982.
`
`3.
`
`From 1977 through 1979, I worked as a processor design engineer at
`
`Hughes Aircraft Company in Fullerton, California. In this capacity, I designed
`
`computer systems which interface with memory integrated circuits. As one
`
`example, I was responsible for the design of an Input/Output processor which
`
`directly interfaced to a memory controller for a military mainframe computer
`
`system. From 1979 through June 1982, I was a Research Assistant, Instructor, and
`
`Teaching Assistant in the Computer Systems Laboratory at Stanford University.
`
`From 1982 through December 1985, I was an Assistant Professor of Electrical and
`
`Computer Engineering at Carnegie-Mellon University. My research, both as a PhD
`
`1
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`Micron Technology Inc. et al.
`Ex. 1003, p. 1
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
`
`student and as an assistant professor, involved the research and design of
`
`concurrent computer systems which interface with memory integrated circuits. As
`
`a professor, I taught courses in computer design which included memory design
`
`issues involving DRAM and SDRAM. Since January 1986, I have worked as an
`
`independent consultant, doing business as Wedig Consulting, Inc. As a consultant,
`
`I have designed digital circuits, analyzed computer systems and designed software
`
`for computer based electronic systems. I have also analyzed high-speed backplane
`
`design issues including crosstalk, signal reflection and signal trace timing and
`
`impedance.
`
`C.
`4.
`
`Compensation and Prior Testimony
`I am being compensated at a rate of $700.00 per hour for work on this
`
`matter. I am also being reimbursed for reasonable and customary expenses
`
`associated with my work on this matter. My compensation is not contingent on the
`
`outcome of this matter or the specifics of my testimony.
`
`5.
`
`Previously, I have testified either by deposition or at trial in a number
`
`of litigation matters. My curriculum vitae, including a list of all of my publications,
`
`and cases in which I have previously testified as an expert is attached as Exhibit
`
`1004.
`
`2
`
`Micron Technology Inc. et al.
`Ex. 1003, p. 2
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
`
`D.
`6.
`
`Information Considered
`My opinions are based on my years of education, research and
`
`experience, as well as my investigation and study of relevant materials. In forming
`
`my opinions, I have considered the materials I identify in this report and those
`
`listed in Attachment B.
`
`7.
`
`I may rely upon these materials and/or additional materials to respond
`
`to arguments raised by the Patent Owner. I may also consider additional documents
`
`and information in forming any necessary opinions — including documents that
`
`may not yet have been provided to me.
`
`8.
`
`My analysis of the materials produced in this matter is ongoing and I
`
`will continue to review any new material as it is provided.
`
`II.
`
`LEGAL STANDARDS FOR PATENTABILITY
`9.
`In expressing my opinions and considering the subject matter of the
`
`claims of the ’608 Patent, I am relying upon certain basic legal principles that have
`
`been explained to me.
`
`10.
`
`First, I understand that for an invention claimed in a patent to be
`
`found patentable, it must be, among other things, new and not obvious from what
`
`was known before the invention was made.
`
`11.
`
`I understand the information that is used to evaluate whether an
`
`invention is new and not obvious is generally referred to as “prior art” and
`
`3
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`Micron Technology Inc. et al.
`Ex. 1003, p. 3
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`generally includes patents and printed publications (e.g., books, journal
`
`publications, articles on websites, product manuals, etc.).
`
`12.
`
`I understand that in this proceeding the Petitioner has the burden of
`
`proving that the claims of the ’608 Patent are anticipated by or obvious from the
`
`prior art by a preponderance of the evidence. I understand that “a preponderance of
`
`the evidence” is evidence sufficient to show that a fact is more likely true than it is
`
`not.
`
`13.
`
`I understand that in this proceeding, the claims should be given their
`
`ordinary and accustomed meaning as understood by one of ordinary skill in the art
`
`in view of the patent and its file history. The claims, after being construed in this
`
`manner, are then to be compared to the information in the prior art.
`
`14.
`
`I understand that in this proceeding, the information that may be
`
`evaluated is limited to patents and printed publications. My analysis below
`
`compares the claims to patents and printed publications that are prior art to the
`
`claims.
`
`15.
`
`I understand that there are two ways in which prior art may render a
`
`patent claim unpatentable. First, the prior art can be shown to “anticipate” the
`
`claim. Second, the prior art can be shown to have made the claim “obvious” to a
`
`person of ordinary skill in the art. My understanding of the two legal standards is
`
`set forth below.
`
`4
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`Micron Technology Inc. et al.
`Ex. 1003, p. 4
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`A.
`16.
`
`Anticipation
`I understand that the following standards govern the determination of
`
`whether a patent claim is “anticipated” by the prior art.
`
`17.
`
`I understand that the “prior art” includes patents and printed
`
`publications that existed before the earliest filing date (the “effective filing date”)
`
`of the claim in the patent. I also understand that a patent will be considered prior
`
`art if it was filed before the effective filing date of the claimed invention, while a
`
`printed publication will be considered prior art if it was publicly available before
`
`that date.
`
`18.
`
`I understand that, for a patent claim to be “anticipated” by the prior
`
`art, each and every requirement of the claim must be found, expressly or
`
`inherently, in a single prior art reference as recited in the claim. I understand that
`
`claim limitations that are not expressly described in a prior art reference may still
`
`be there if they are “inherent” to the thing or process being described in the prior
`
`art. For example, an indication in a prior art reference that a particular process
`
`complies with a published standard would indicate that the process must inherently
`
`perform certain steps or use certain data structures that are necessary to comply
`
`with the published standard.
`
`5
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`Micron Technology Inc. et al.
`Ex. 1003, p. 5
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`19.
`
`I understand that if a reference incorporates other documents by
`
`reference, the incorporating reference and the incorporated reference(s) should be
`
`treated as a single prior art reference for purposes of analyzing anticipation.
`
`20.
`
`I understand that it is acceptable to consider evidence other than the
`
`information in a particular prior art document to determine if a feature is
`
`necessarily present in or inherently described by that reference.
`
`B.
`21.
`
`Obviousness
`I understand that a claimed invention is not patentable if it would have
`
`been obvious to a person of ordinary skill in the field of the invention at the time
`
`the invention was made.
`
`22.
`
`I understand that the obviousness standard is defined in the patent
`
`statute (35 U.S.C. § 103(a)) as follows:
`
`A patent may not be obtained though the invention is not identically
`
`disclosed or described as set forth in section 102 of this title, if the
`
`differences between the subject matter sought to be patented and the prior art
`
`are such that the subject matter as a whole would have been obvious at the
`
`time the invention was made to a person having ordinary skill in the art to
`
`which said subject matter pertains. Patentability shall not be negatived by
`
`the manner in which the invention was made.
`
`6
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`Micron Technology Inc. et al.
`Ex. 1003, p. 6
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`

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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`23.
`
`I understand that the following standards govern the determination of
`
`whether a claim in a patent is obvious. I have applied these standards in my
`
`evaluation of whether the asserted claims of the ’608 Patent would have been
`
`considered obvious as of the priority date of the patent.
`
`24.
`
`I understand that to find a claim in a patent obvious, one must make
`
`certain findings regarding the claimed invention and the prior art. Specifically, I
`
`understand that the obviousness question requires consideration of four factors
`
`(although not necessarily in the following order):
`
` The scope and content of the prior art;
`
` The differences between the prior art and the claims at issue;
`
` The knowledge of a person of ordinary skill in the pertinent art; and
`
` Whatever objective factors indicating obviousness or non-obviousness
`
`may be present in any particular case.
`
`25.
`
`In addition, I understand that the obviousness inquiry should not be
`
`done in hindsight, but must be done using the perspective of a person of ordinary
`
`skill in the relevant art as of the effective filing date of the patent claim.
`
`26.
`
`I understand the objective factors indicating obviousness or non-
`
`obviousness may include: commercial success of products covered by the patent
`
`claims; satisfying a long-felt need for the invention; failed attempts by others to
`
`make the invention; copying of the invention by others in the field; unexpected
`
`7
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`Micron Technology Inc. et al.
`Ex. 1003, p. 7
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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`results achieved by the invention; praise of the invention by those in the field; the
`
`taking of licenses under the patent by others; expressions of surprise by experts and
`
`those skilled in the art at the making of the invention; and the patentee proceeded
`
`contrary to the accepted wisdom of the prior art. I also understand that any of this
`
`evidence must be specifically connected to the invention rather than being
`
`associated with the prior art or with marketing or other efforts to promote an
`
`invention. I am not presently aware of any evidence of “objective factors”
`
`suggesting the claimed inventions are not obvious, and reserve my right to address
`
`any such evidence if it is identified in the future.
`
`27.
`
`I understand the combination of familiar elements according to known
`
`methods is likely to be obvious when it does no more than yield predictable results.
`
`I also understand that an example of a solution in one field of endeavor may make
`
`that solution obvious in another related field. I also understand that market
`
`demands or design considerations may prompt variations of a prior art system or
`
`process, either in the same field or a different one, and that these variations will
`
`ordinarily be considered obvious variations of what has been described in the prior
`
`art.
`
`28.
`
`I also understand that if a person of ordinary skill can implement a
`
`predictable variation, that variation would have been considered obvious. I
`
`understand that for similar reasons, if a technique has been used to improve one
`
`8
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`Micron Technology Inc. et al.
`Ex. 1003, p. 8
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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`device, and a person of ordinary skill in the art would recognize that it would
`
`improve similar devices in the same way, using that technique to improve the other
`
`device would have been obvious unless its actual application yields unexpected
`
`results or challenges in implementation.
`
`29.
`
`I understand that the obviousness analysis need not seek out precise
`
`teachings directed to the specific subject matter of the challenged claim, but
`
`instead can take account of the “ordinary innovation” and experimentation that
`
`does no more than yield predictable results, which are inferences and creative steps
`
`that a person of ordinary skill in the art would employ.
`
`30.
`
`I understand that sometimes it will be necessary to look to interrelated
`
`teachings of multiple patents; the effects of demands known to the design
`
`community or present in the marketplace; and the background knowledge
`
`possessed by a person having ordinary skill in the art. I understand that all these
`
`issues may be considered to determine whether there was an apparent reason to
`
`combine the known elements in the fashion claimed by the patent at issue.
`
`31.
`
`I understand that the obviousness analysis cannot be confined by a
`
`formalistic conception of the words “teaching, suggestion, and motivation.” I
`
`understand that in 2007, the Supreme Court issued its decision in KSR Int'l Co. v.
`
`Teleflex, Inc., 550 U.S. 398 (2007), where the Court rejected the previous
`
`requirement of a “teaching, suggestion, or motivation to combine” known elements
`
`9
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`Micron Technology Inc. et al.
`Ex. 1003, p. 9
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`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`of prior art for purposes of an obviousness analysis as a precondition for finding
`
`obviousness. It is my understanding that KSR confirms that any motivation that
`
`would have been known to a person of skill in the art, including common sense, or
`
`derived from the nature of the problem to be solved, is sufficient to explain why
`
`references would have been combined.
`
`32.
`
`I understand that a person of ordinary skill attempting to solve a
`
`problem will not be led only to those elements of prior art designed to solve the
`
`same problem. I understand that under the KSR standard, steps suggested by
`
`common sense are important and should be considered. Common sense teaches
`
`that familiar items may have obvious uses beyond their primary purposes, and in
`
`many cases a person of ordinary skill will be able to fit the teachings of multiple
`
`patents together like pieces of a puzzle. As such, the prior art considered can be
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`directed to any need or problem known in the field of endeavor as of the priority
`
`date of the patent and can provide a reason for combining the elements of the prior
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`art in the manner claimed. In other words, the prior art does not need to be directed
`
`towards solving the same problem that is addressed in the patent. Further, the
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`individual prior art references themselves need not all be directed towards solving
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`the same problem.
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`33.
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`I understand that an invention that might be considered an obvious
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`variation or modification of the prior art may be considered non-obvious if one or
`
`10
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`Micron Technology Inc. et al.
`Ex. 1003, p. 10
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`

`

`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
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`more prior art references discourage or lead away from the line of inquiry
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`disclosed in the reference(s). A reference does not “teach away” from an invention
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`simply because the reference suggests that another embodiment of the invention is
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`better or preferred. My understanding of the doctrine of teaching away requires a
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`clear indication that the combination should not be attempted (e.g., because it
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`would not work or explicit statements saying the combination should not be made).
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`34.
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`I understand that a person of ordinary skill is also a person of ordinary
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`creativity.
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`35.
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`I further understand that in many fields, it may be that there is little
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`discussion of obvious techniques or combination, and it often may be the case that
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`market demand, rather than scientific literature or knowledge, will drive design
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`trends. When there is such a design need or market pressure to solve a problem and
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`there are a finite number of identified, predictable solutions, a person of ordinary
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`skill has good reason to pursue the known options within their technical grasp. If
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`this leads to the anticipated success, it is likely the product not of innovation but of
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`ordinary skill and common sense. In that instance, the fact that a combination was
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`obvious to try might show that it was obvious. The fact that a particular
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`combination of prior art elements was “obvious to try” may indicate that the
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`combination was obvious even if no one attempted the combination. If the
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`combination was obvious to try (regardless of whether it was actually tried) or
`
`11
`
`Micron Technology Inc. et al.
`Ex. 1003, p. 11
`
`

`

`Declaration of Dr. Robert Wedig Regarding U.S. Patent No. 10,268,608
`
`leads to anticipated success, then it is likely the result of ordinary skill and
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`common sense rather than innovation.
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`III. THE ’608 PATENT
`A. Effective Filing Date
`36. The application that resulted in the ’608 Patent (EX1001) is U.S.
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`Patent Application Serial No. 15/820,076 (EX1002), filed November 21, 2017. The
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`’608 Patent claims priority to U.S. Provisional Application No. 61/676,883
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`(EX1025), filed July 27, 2012. All of the prior art that I rely upon below predates
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`July 27, 2012, and thus, for now, I assume that the claims of the ’608 Patent have
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`an effective filing date of July 27, 2012, regardless of