Case 2:22-cv-00482-RWS Document 98 Filed 09/27/23 Page 1 of 37 PageID #: 2605
`
`UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`
`NETWORK SYSTEM TECHNOLOGIES,
`LLC,
`
`
`
`
`
`TEXAS INSTRUMENTS INCORPORATED;
`FORD MOTOR COMPANY,
`
`
`
`
`
`
`Defendants.
`
`Plaintiff,
`
`v.
`
`
`
`
`
` Civil Action No. 2:22-CV-00482-RWS
`
` JURY TRIAL DEMANDED
`
`OPENING CLAIM CONSTRUCTION BRIEF
`BY PLAINTIFF NETWORK SYSTEM TECHNOLOGIES, LLC
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`
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`Case 2:22-cv-00482-RWS Document 98 Filed 09/27/23 Page 2 of 37 PageID #: 2606
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`TABLES OF CONTENTS
`
`
`TABLES OF CONTENTS ............................................................................................................. ii
`TABLE OF EXHIBITS ................................................................................................................. iii
`TABLE OF AUTHORITIES ......................................................................................................... iv
`I.
`Introduction ............................................................................................................................. 1
`II. Technical Background ............................................................................................................ 1
`A. Background on Network-on-Chip Technology .................................................................. 1
`B. Overview of the Asserted Patents ....................................................................................... 3
`III. Legal Standard ........................................................................................................................ 5
`A. Plain and Ordinary .............................................................................................................. 5
`B. Means-Plus-Function .......................................................................................................... 6
`C. Definiteness......................................................................................................................... 6
`IV. Level of Ordinary Skill in the Art ........................................................................................... 7
`V. Disputed Terms ....................................................................................................................... 8
`A. “Network” ........................................................................................................................... 8
`B. “Interconnect Means” ......................................................................................................... 9
`C. “Integrated Circuit” ........................................................................................................... 10
`D. “Interface Means” ............................................................................................................. 12
`E.
`“Dropping Means” ............................................................................................................ 15
`F.
`“Communication Manager” .............................................................................................. 18
`G. “Resource Manager” ......................................................................................................... 21
`H. “Multicast” ........................................................................................................................ 24
`I.
`“Narrowcast”..................................................................................................................... 25
`J.
`“Data Communication” ..................................................................................................... 26
`K. “Optimal Moment” ........................................................................................................... 27
`L.
`“Optimal Amount” ............................................................................................................ 29
`VI. Conclusion ............................................................................................................................ 30
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`ii
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`TABLE OF EXHIBITS
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`Exhibit
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`U.S. Patent No. 7,366,818
`
`U.S. Patent No. 7,373,449
`
`U.S. Patent No. 7,594,052
`
`U.S. Patent No. 7,769,893
`
`U.S. Patent No. 8,072,893
`
`U.S. Patent No. 8,086,800
`
`2023-08-17 – Declaration of Dr. Erik Chmelar re Claim Construction
`
`American Heritage College Dictionary (4th ed. 2000)
`
`Ex. No.
`1
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`2
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`3
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`4
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`5
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`6
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`7
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`8
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`iii
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`TABLE OF AUTHORITIES
`
`
`
`Page(s)
`
`Cases
`
`Apex Inc. v. Raritan Computer, Inc.,
`325 F.3d 1364 (Fed. Cir. 2003)......................................................................................6, 14, 17
`
`Avid Tech., Inc. v. Harmonic, Inc.,
`812 F.3d 1040 (Fed. Cir. 2016)............................................................................................6, 23
`
`Bitmicro LLC v. Kioxia America, Inc., et al.,
`Case 6:22-cv-00331 (W.D. Texas Feb. 16, 2023) .............................................................28, 30
`
`Budde v. Harley-Davidson, Inc.,
`250 F.3d 1369 (Fed. Cir. 2001)..................................................................................................6
`
`Halliburton Energy Servs., Inc. v. M-I LLC,
`514 F.3d 1244 (Fed. Cir. 2008)..................................................................................................7
`
`Interval Licensing LLC v. AOL, Inc.,
`766 F.3d 1364 (Fed. Cir. 2014)..................................................................................................7
`
`Linear Tech. Corp. v. Impala Linear Corp.,
`379 F.3d 1311 (Fed. Cir. 2004)..........................................................................................14, 17
`
`Massachusetts Institute of Technology v. Shire Pharmaceuticals, Inc.,
`839 F.3d 1111 (Fed. Cir. 2016)................................................................................................23
`
`Medrad, Inc. v. MRI Devices Corp.,
`401 F.3d 1313 (Fed. Cir. 2005)..................................................................................................5
`
`MIT v. Abacus Software,
`462 F.3d 1344 (Fed. Cir. 2006)..........................................................................................14, 17
`
`Nautilus, Inc. v. Biosig Instruments, Inc.,
`572 U.S. 898 (2014) ...................................................................................................................6
`
`O2 Micro, Ltd. v. Beyond Innovation Tech. Co.,
`521 F. 3d 1351 (Fed. Cir. 2008).....................................................................................9, 10, 11
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005)..................................................................................................5
`
`Power Integrations, Inc. v. Fairchild Semiconductor Int'l, Inc.,
`711 F.3d 1348 (Fed. Cir. 2013)..........................................................................................14, 17
`
`
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`iv
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`
`
`Skky, Inc. v. MindGeek s.a.r.l.,
`859 F.3d 1014 (Fed. Cir 2017).................................................................................6, 13, 16, 20
`
`Thorner v. Sony Computer Entertainment America LLC,
`669 F.3d 1362 (Fed. Cir. 2012)........................................................................................5, 6, 23
`
`Vitronics Corp. v. Conceptronic, Inc.,
`90 F.3d 1576 (Fed. Cir. 1996)....................................................................................................5
`
`Statutes
`
`35 U.S.C. § 112 ¶ 6 ................................................................................................................ passim
`
`35 U.S.C. § 282 ................................................................................................................................7
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`
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`I.
`
`Introduction
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`Pursuant to P.R. 4-5 and this Court’s Docket Control Order (Dkt. 49), Plaintiff Network
`
`System Technologies, LLC (“NST”) respectfully submits its opening claim construction brief
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`regarding U.S. Patent Nos. 7,366,818 (“’818 Patent”), 7,373,449 (“’449 Patent”), 7,594,052 (“’052
`
`Patent”), 7,769,893 (“’9893 Patent”), 8,072,893 (“’2893 Patent”), and 8,086,800 (“’800 Patent”)
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`(collectively, “Asserted Patents” attached hereto as Exhibits 1–6). The Parties have requested that
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`the Court construe 12 claim terms, each of which are addressed below.
`
`II.
`
`Technical Background
`
`A.
`
`Background on Network-on-Chip Technology
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`System-on-chip (“SoC”) technology is widely used in consumer electronics and computing
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`devices, including smartphones, laptops, and embedded systems such as vehicle infotainment and
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`advanced driver assistance systems. Dkt. 1 ¶ 92. As the adoption of SoCs in electronic devices
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`grew over time, and as microchip manufacturing technology advanced, more processing cores and
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`other circuitry modules were incorporated into SoCs. Id. ¶ 93. In early SoC designs, these circuitry
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`modules were directly connected, first by point-to-point interconnects, and later by shared buses,
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`both of which resulted in large SoCs with poor interconnect efficiency. Id.; see also Declaration
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`of Dr. Erik Chmelar (“Chmelar Decl.” attached hereto as Exhibit 7), ¶¶ 29-31. Though more
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`efficient than point-to-point interconnects, buses suffered from a critical limitation insofar as only
`
`one module can send data to the bus at a time and the others must wait their turn. ’818 Patent at
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`1:33-34. Thus, as the number of circuitry modules increased, buses became a bottleneck limiting
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`the number of circuitry modules that could be practicably interconnected—and therefore, limited
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`the potential power and capability of SoCs. Id.
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`To eliminate this bottleneck, the inventors of the Asserted Patents at Philips Semiconductor
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`developed advanced network-on-chip (“NoC”) technologies. An NoC is a substantially different
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`interconnection paradigm for on-chip communication that leverages certain aspects of traditional
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`computer networks, such as network interfaces for connecting modules to an on-chip network,
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`packetized data for breaking messages up into smaller units for transmission by the on-chip
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`network, and routers for switching of data packets along various routes. Chmelar Decl. ¶¶ 32, 57-
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`59. In an NoC, a message transmitted from one module to another may be divided into smaller
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`packets by a network interface and those packets may travel across the NoC using different routes
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`determined by the routers in the NoC. Id. ¶ 58. Each interconnection between routers may be called
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`a “hop,” such that the NoC is a “multi-hop” interconnection between modules separated by routers,
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`or network nodes. Id. ¶¶ 32, 57-60. Accordingly, an NoC is an “indirect” interconnection between
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`modules. Id. ¶¶ 181, 189. This is distinctly different from a shared bus, where data transmitted
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`from one module to another always takes the same route, and is therefore a “direct” interconnection
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`between modules.
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`Besides overcoming the bottleneck of shared buses, NoCs have other advantages over
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`prior, direct, interconnections. Because NoCs can utilize interconnects more efficiently than shared
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`buses, fewer interconnects are required. Id. ¶¶ 32-36, 65. This reduces the area and power
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`consumption of the on-chip interconnects of an SoC compared to shared buses. Id. ¶¶ 59, 65.
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`Additionally, by moving the communications logic of a circuitry module to a dedicated network
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`interface that connects the module to the NoC, the modules can be simpler and more modular,
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`which enables even higher levels of integration at lower design costs. Id. ¶¶ 59, 65.
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`Although NoCs leverage certain aspects of traditional computer networks, the on-chip
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`environment of NoCs introduces several constraints and challenges not present in the off-chip
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`environment. ’818 Patent at 1:62-2:6. For example, there is substantially less memory and
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`computational resources in the on-chip environment that can be dedicated to network processing.
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`Id. at 2:44-50, 3:7-22, 3:31- 35. The Asserted Patents address these challenges.
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`B.
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`Overview of the Asserted Patents
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`The Asserted Patents generally relate to integrated circuits having a plurality of circuitry
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`modules that are communicatively interconnected via NoCs.
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`
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`Multiple of the Asserted Patents disclose systems for Quality of Service (“QoS”), called
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`“connection properties” in the Patents, which are mechanisms to prioritize and manage
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`communication between different circuitry modules. Chmelar Decl. ¶¶ 38-39. QoS allows for the
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`allocation of network resources according to the specific requirements of different applications or
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`tasks, ensuring, for example, that critical communications get higher priority while lower-priority
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`communications do not unnecessarily consume resources. Id. ¶¶ 38-39. Examples of QoS include
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`minimum throughput or bandwidth, maximum latency, and priority. Id. ¶¶ 38-39. The ’449 and
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`’052 Patents concern aspects of QoS.
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`The ’449 Patent discloses an NoC that interconnects modules by communication channels,
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`with each channel having QoS properties, such as bandwidth and latency guarantees, that can be
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`configured independently. ’449 Patent at Abstract, 7:15-30, 11:20-22, 16:1-5. For example, a
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`request channel can guarantee a bandwidth of 1 mega-bit-per-second, and a return channel can
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`guarantee bandwidth of 25 mega-bits-per-second. Id. at 9:51-59. Such independently configurable
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`QoS guarantees enable more efficient utilization of the resources of the NoC because the
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`guarantees on each channel can be efficiently adapted to their actual requirements. Id. at Abstract,
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`7:26-31.
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`The ’052 Patent discloses NoC network interfaces configured to map communications to
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`communication channels based on a desired QoS requested for the communication. ’052 Patent at
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`Abstract, 1:6-10, 3:6-34, 3:45-51, 4:7-18, 8:7-9, 8:63-65. This mapping ensures that high-priority
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`communications requiring certain QoS guarantees are appropriately mapped within the network,
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`resulting in the most efficient use of network resources. Id. at 7:63-67. Moreover, performing
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`such mapping within the network interfaces, as opposed to within the modules, frees the modules
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`to focus on their dedicated operations. Id. at 3:30-34, 5:16-21.
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`The Asserted Patents disclose NoC network interfaces that manage certain inter-module
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`communication tasks, such as packetizing data at the sending module and the depacketizing data
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`at the receiving module, translating between different communication protocols used by the
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`modules, and dropping data in certain cases. The ’9893 and ’818 Patents concern aspects of
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`network interfaces.
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`The ’9893 Patent discloses an NoC network interface configured to translate between
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`different address formats used by the modules. ’9893 Patent at Abstract, 3:43-63. This address
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`translation allows various types of modules to be integrated regardless of the communication
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`protocols used by the modules. Id. at 1:45-48. This can simplify modules and reduce SoC design
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`time and costs. Id. at 1:42-48.
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`The ’818 Patent discloses NoC network interfaces configured to drop data in certain cases.
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`’818 Patent at 5:35-36. One example where data may be dropped is when the buffer at the receiving
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`module is full and thus no more data may be received at that module. Id. at 4:40-55.
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`Finally, multiple of the Asserted Patents disclose NoC buffers to increase network
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`efficiency and resolve synchronization issues between fast and slow communication channels. The
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`’2893 and ’800 Patents concern aspects of data storage and buffering.
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`The ’2893 Patent discloses how to synchronize slow communication channels with faster
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`channels. ’2893 Patent at 1:34-2:33. Instead of simply slowing down the faster channels, data
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`storage elements are added to the slow channels to delay their communications by an amount that
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`causes each data package transmitted on the slow channels to be received in a next data-package
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`cycle instead of the current data-package cycle. Id. at 1:65-2:14, 2:26-33, 2:47-3:17, 3:49-53.
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`The ’800 Patent discloses an NoC network interface that has buffers to store data until an
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`optimal amount of data is available for transmission on the network. ’800 Patent at 4:18-28, 4:50-
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`57. Rather than inefficiently transmitting data in small packages as it is generated by the circuitry
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`modules, the buffers aggregate data until an optimal amount of data is ready to be transmitted over
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`the network, increasing overall network utilization and efficiency. Id. at 3:1-3, 7:44-46.
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`III. Legal Standard
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`A.
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`Plain and Ordinary
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`
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`The “words of a claim” are understood according to their plain and ordinary meaning in
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`the context of the surrounding claim limitations, the specification, and the prosecution history.
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`Thorner v. Sony Computer Entertainment America LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012);
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`Vitronics Corp. v. Conceptronic, Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996).
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`
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`The “words of a claim” are not given their plain meaning only when the patentee “acts as
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`his own lexicographer” or “disavows the full scope of a claim term either in the specification or
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`during prosecution.” Thorner, 669 F.3d at 1365. As the Federal Circuit cautions, “we must look at
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`the ordinary meaning in the context of the written description and the prosecution history,” since
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`importing limitations is one of the “cardinal sins of patent law.” Medrad, Inc. v. MRI Devices
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`Corp., 401 F.3d 1313, 1319 (Fed. Cir. 2005); Phillips v. AWH Corp., 415 F.3d 1303, 1320 (Fed.
`
`Cir. 2005). Accordingly, a “claim construction that does not encompass a disclosed embodiment
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`is rarely, if ever, correct.” Medrad, 401 F.3d at 1320.
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`
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`The standard for lexicography is exacting. Thorner, 669 F.3d at 1365-67. “To act as its
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`own lexicographer, a patentee must clearly set forth a definition of the disputed claim term other
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`than its plain and ordinary meaning,” and occurs only when the patentee explicitly discloses that
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`a term “means” a particular definition or “is defined.” Id. The “standard for disavowal of claim
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`scope is similarly exacting.” Id. The intrinsic evidence must provide “expressions of manifest
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`exclusion or restriction,” clarifying that the invention does not include a particular feature. Id.
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`“Where the alleged disavowal is ambiguous,” courts do not apply the doctrine of prosecution
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`history disclaimer. Avid Tech., Inc. v. Harmonic, Inc., 812 F.3d 1040, 1045 (Fed. Cir. 2016).
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`B. Means-Plus-Function
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`
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`“In determining whether a claim term invokes § 112, ¶ 6, the essential inquiry is not merely
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`the presence or absence of the word ‘means’ but whether the words of the claim are understood by
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`persons of ordinary skill in the art to have a sufficiently definite meaning as the name for structure.”
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`Skky, Inc. v. MindGeek s.a.r.l., 859 F.3d 1014, 1019 (Fed. Cir 2017) (internal quotations and
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`citations omitted). While the word “means” triggers a presumption that § 112, ¶ 6 applies, this can
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`be rebutted by a preponderance of the evidence when “consider[ing] the limitations as a whole”
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`according to the “understanding of one of ordinary skill in the art.” Apex Inc. v. Raritan Computer,
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`Inc., 325 F.3d 1364, 1374 (Fed. Cir. 2003) (internal quotations, citations, and modifications
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`omitted). “[W]hen a claim uses the term ‘means,’ the focus is on whether the claim term recites
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`no function corresponding to the means or recites sufficient structure or material for performing
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`that function.” Id. at 1372 (internal quotations omitted). To further “hold that a claim containing a
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`means-plus-function limitation lacks a disclosure of structure” “requires [an additional] finding,
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`by clear and convincing evidence, that the specification lacks disclosure of structure sufficient to
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`be understood by one skilled in the art as being adequate to perform the recited function.” Budde
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`v. Harley-Davidson, Inc., 250 F.3d 1369, 1376-77 (Fed. Cir. 2001).
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`C.
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`Definiteness
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`Definiteness is evaluated from the perspective of someone “skilled in the relevant art.”
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`Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 909 (2014). “[T]he certainty which the
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`law requires in patents is not greater than is reasonable, having regard to their subject-matter.” Id.
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`at 910 (quoting Minerals Separation, Ltd. v. Hyde, 242 U.S. 261, 270 (1916)). Terms of degree
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`are not “inherently indefinite,” and “absolute or mathematical precision is not required.” Interval
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`Licensing LLC v. AOL, Inc., 766 F.3d 1364, 1370 (Fed. Cir. 2014).
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`Indefiniteness requires an accused infringer to show “by clear and convincing evidence
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`that a skilled artisan could not discern the boundaries of the claim based on the claim language,
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`the specification, and the prosecution history, as well as her knowledge of the relevant art area.”
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`Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1249-50 (Fed. Cir. 2008); 35 U.S.C.
`
`§ 282.
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`IV.
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`Level of Ordinary Skill in the Art
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`NST’s expert, Dr. Chmelar, opines that a person of ordinary skill in the art (“POSITA”) at
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`the time of the invention of the Asserted Patents is an individual having at least: a Bachelor of
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`Science (or equivalent) degree in electrical engineering, computer engineering, or a related field,
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`and 2-3 years of work experience in very large-scale integrated (“VLSI”) systems, such as
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`application-specific integrated circuits (“ASICs”), application-specific standard parts (“ASSPs”),
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`system-on-chip (“SoC”), or field-programmable gate arrays (“FPGAs”), and has an understanding
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`of on-chip interconnection networks. Chmelar Decl. ¶ 26.
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`Defendants’ expert, Dr. Thornton, posits an even higher skill level: at least either a Master’s
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`degree in Electrical Engineering, or related field, as well as at least three years of work experience
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`in the field of SoC design, or a Bachelor’s degree in Electrical Engineering, or related field, as
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`well as at least five years of work experience in the field of SoC design.
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`Neither expert has opined whether this discrepancy would have an impact on their
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`conclusions as to the constructions of the various terms. It is noteworthy, however, that Dr.
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`Chmelar opines that the Asserted Patents would not be indefinite to a POSITA having a skill level
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`lower than that posited by Dr. Thornton, so it is reasonable to conclude that Dr. Chmelar’s
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`definiteness conclusions would remain the same for Dr. Thornton’s higher-skilled POSITA.
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`V.
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`Disputed Terms
`
`A.
`
`“Network”
`
`Term
`
`“network”
`
`’818 Patent: claims 1, 2
`’449 Patent: claims 10-12, 14
`’9893 Patent: claims 4, 11
`’2893 Patent: claims 1, 10
`
`NST’s Construction
`“multi-hop interconnection
`between modules separated
`by one or more network
`nodes”
`
`Defendants’ Construction
`Plain and ordinary meaning
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`NST’s proposed construction of “network” as a “multi-hop interconnection between
`
`modules separated by one or more network nodes” reflects what a POSITA would have understood
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`this term to mean as used in the Asserted Patents. See Chmelar Decl. ¶¶ 50-52. This construction
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`is based on intrinsic evidence in the Asserted Patents, which explain, “[i]ntroducing networks as
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`on-chip interconnects radically changes the communication when compared to direct
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`interconnects, such as buses or switches. This is because of the multi-hop nature of a network,
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`where communication modules are not directly connected, but separated by one or more
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`network nodes.” See, e.g., ’818 Patent at 3:36-41; see also ’449 Patent at 3:47-52; ’052 Patent at
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`2:32-37; ’9893 Patent at 2:46-51; ’800 Patent at 2:3-8. Defendants’ proposal fails to account for
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`the multi-hop nature of the network.
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`Moreover, Defendants’ proposal is unworkable because the term “network” lacked a
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`consistent plain and ordinary meaning at the time of the inventions. At that time, the concept of an
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`on-chip “network” was still emerging from the intersection of computer networking and microchip
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`design. Chmelar Decl. ¶ 53. This is reflected in an authoritative IEEE dictionary of the time, which
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`includes differing definitions for the term “network.” See Chmelar Decl. ¶ 56 (comparing “An
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`arrangement of components, or nodes, and interconnecting branches” (microchip-design
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`perspective) with “A network is any set of devices or subsystems connected by links joining
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`(directly or indirectly) a set of terminal nodes” (computer networking perspective)). Not
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`surprisingly, the Asserted Patents explicitly distinguish between the differing definitions of a
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`“network” as used in the asserted inventions from traditional computer networking or traditional
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`microchip design concepts. Id. ¶ 59; ’818 Patent at 1:67-2:16; see also ’449 Patent at 1:66-2:15;
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`’052 Patent at 1:64-2:12; ’9893 Patent at 1:65-2:11; ’800 Patent at 1:64-2:2. These distinctions
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`were not trivial to the inventions, and are key to the Parties’ invalidity disputes. Thus, NST’s plain
`
`and ordinary meaning construction should be adopted. O2 Micro, Ltd. v. Beyond Innovation Tech.
`
`Co., 521 F. 3d 1351, 1361 (Fed. Cir. 2008) (“[W]hen a term has more than one ‘ordinary’ meaning
`
`or when reliance on a term’s ‘ordinary’ meaning does not resolve the parties’ dispute.”).
`
`B.
`
`“Interconnect Means”
`
`Term
`“interconnect means”
`
`’052 Patent: claim 6
`
`NST’s Construction
`“multi-hop interconnection
`between modules separated by
`one or more network nodes.”
`
`Defendants’ Construction
`Plain and ordinary meaning.
`
`Not subject to Section 112 ¶ 6.
`
`
`Intrinsic evidence shows that a POSITA would have understood the term “interconnect
`
`means” to describe a “multi-hop interconnection between modules separated by one or more
`
`network nodes” as a “network” (i.e., an indirect interconnection) rather than a shared bus (i.e., a
`
`direct interconnection). See Chmelar Decl. ¶¶ 175-177.
`
`For instance, the ’052 Patent ascribes the exact same functionalities to an “interconnect
`
`means (N)” as it does to a “network N,” which was addressed in the previous section. See Chmelar
`
`Decl. ¶¶ 182-187 (citing ’052 Patent at Abstract, Fig. 1, Fig. 4, 1:7-8, 3:18-22, 3:51-54, 4:1-4,
`
`5:24-31). Furthermore, the ’052 Patent discloses that the “interconnect means (N) is provided . . .
`
`for enabling a connection based communication having a set of connection properties.” See
`
`9
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`Page 14
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`Case 2:22-cv-00482-RWS Document 98 Filed 09/27/23 Page 15 of 37 PageID #: 2619
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`
`
`Chmelar Decl. ¶ 188 (citing ’052 Patent at Abstract; see also 3:15-18, 3:51-54, 4:1-4). To this end,
`
`the Patent lists a number of properties for the “connection,” including “1) data integrity, 2)
`
`transaction ordering, 3) transaction completion, 4) connection flow control, and 5) connection
`
`throughput, latency, and jitter.” Id. ¶¶ 188-189 (citing ’052 Patent at 4:50-5:5, 6:13-19). A POSITA
`
`would understand a connection with these properties to be a known attribute of an example of the
`
`“network” disclosed in the Asserted Patents. Id. ¶ 189. In this context, a POSITA would understand
`
`“interconnection means” to describe a “network” comprising indirect interconnections between
`
`modules, not a direct interconnection between modules as typically found in a bus architecture. Id.
`
`Thus, a POSITA would understand that the “network N” and the “interconnect means (N)” to be
`
`the same thing. Id.
`
`Defendants’ argument for a plain and ordinary meaning construction fails because, like
`
`“network,” the term “interconnect means” lacked consistent meaning at the time of the inventions.
`
`See Chmelar Decl. ¶¶ 178-181. Moreover, adopting a plain and ordinary meaning would fail to
`
`resolve key invalidity disputes regarding whether the terms “network” and “interconnect means”
`
`should be constrained by their usage in the Asserted Patents or should encompass additional
`
`concepts like bus architectures and off-chip communications. Thus, a plain and ordinary meaning
`
`is inappropriate. O2 Micro, Ltd., 521 F. 3d at 1361 (Fed. Cir. 2008).
`
`C.
`
`“Integrated Circuit”
`
`NST’s Construction
`“interconnected circuitry on a
`chip”
`
`Defendants’ Construction
`Plain and ordinary meaning
`
`Term
`“integrated circuit”
`
`’818 Patent: claims 1-3, 5-7
`’449 Patent: claim 10
`’052 Patent: claim 6
`’9893 Patent: claim 4
`’2893 Patent: claims 1, 10
`’800 Patent: claim 12
`
`10
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`Page 15
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`Case 2:22-cv-00482-RWS Document 98 Filed 09/27/23 Page 16 of 37 PageID #: 2620
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`
`
`Intrinsic evidence supports NST’s construction of an “integrated circuit” as
`
`“interconnected circuitry on a chip.” The Asserted Patents disclose embodiments concerning
`
`circuitry “on a chip” (i.e., network-on-chip) rather than “off-chip,” explaining the many ways in
`
`which “NoC’s [(network-on-chip’s)] premises are different from off-chip networks,” including
`
`“their constraints and synchronization,” such that “most of the network design choices must be
`
`reevaluated.” Chmelar Decl. ¶¶ 64-65; ’818 Patent at 1:67-2:43;’449 Patent at 1:66-2:42; ’052
`
`Patent at 1:64-2:12; ’9893 Patent at 1:65-2:36; ’800 Patent at 1:64-2:2. For instance, the Asserted
`
`Patents disclose a “system-on-chip” or a “system on silicon” where most or all components are
`
`integrated on an interconnected circuit, including memories, processors, high-speed I/O interfaces,
`
`and dedicated application-specific logic. Chmelar Decl. ¶¶ 67-68; ’818 Patent at 1:51-53; ’449
`
`Patent at 1:15-35, 1:50-52; ’052 Patent at 1:14-32, 1:48-50; ’9893 Patent at 1:14-34, 1:49-51;
`
`’2893 Patent at 1:8-13; ’800 Patent at 1:14-32, 1:48-50.
`
`NST’s construction of an “integrated circuit” as an “interconnected circuitry on a chip” is
`
`also supported by extrinsic evidence, including IEEE technical dictionaries that define an
`
`“integrated circuit” as “[a] combination of interconnected circuit elements [(i.e., ‘interconnected
`
`circuitry’)] inseparably associated on or within a continuous substrate [(i.e., ‘on a chip’)].”
`
`Chmelar Decl. ¶ 69 (citing Exs. H, I and G thereto).
`
`Defendants’ plain and ordinary meaning argument fails to recognize that the Asserted
`
`Patents only disclose an “integrated circuit” that can be interconnected on-chip. Instead,
`
`Defendants’ construction would actually introduce the new concept that an “integrated circuit” can
`
`be off-chip, which is not disclosed by the Asserted Patents and would expand the Parties’ invalidity
`
`disputes. Thus, Defendants’ position is inappropriate. O2 Micro, 521 F. 3d at 1361.
`
`11
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`Page 16
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`Case 2:22-cv-00482-RWS Document 98 Filed 09/27/23 Page 17 of 37 PageID #: 2621
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`
`
`
`
`D.
`
`“Interface Means”
`
`Term
`“interface means” /
`
`“interface means (ANIP,
`PNIP) for managing the
`interface between a module
`(M, S) and the network (N,
`RN) wherein said interface
`means (ANIP, PNIP)
`comprises a first dropping
`means (DM) for dropping
`data, and wherein the dropping
`of data and therefore the
`transaction completion can be
`controlled by the interfaces
`means”
`
`’818 Patent: claims 1, 6, 7
`
`Defendants’ Construction
`Subject to § 112 ¶ 6.
`
`Function: Claim 1: “managing
`the in