Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________________________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________________________________________
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`SAMSUNG ELECTRONICS CO., LTD.
`
`Petitioner
`
`v.
`
`NETWORK SYSTEM TECHNOLOGIES, LLC,
`
`Patent Owner
`
`
`U.S. PATENT NO. 7,373,449
`
`Case IPR2023-TBD
`
`DECLARATION OF TODD MOWRY, PH.D.
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`
`
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`Samsung Ex. 1003
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`
`TABLE OF CONTENTS
`LIST OF EXHIBITS ............................................................................................... V
`I.
`BACKGROUND AND QUALIFICATIONS ................................................ 9
`II. MATERIALS AND OTHER INFORMATION CONSIDERED ................ 12
`III. UNDERSTANDING OF PATENT LAW ................................................... 13
`A.
`The Level of Ordinary Skill in the Art ............................................... 13
`B.
`Obviousness ....................................................................................... 14
`
`IV. SUMMARY OF OPINIONS ....................................................................... 16
`V. OVERVIEW OF THE TECHNOLOGY ..................................................... 16
`A.
`Systems-on-Chip (SoC) ..................................................................... 16
`B.
`Networks-on-Chip (NoC) .................................................................. 18
`C.
`Connections ........................................................................................ 19
`D. Admission Control ............................................................................. 24
`VI. THE ’449 PATENT ..................................................................................... 25
`A.
`Claims ................................................................................................ 26
`B.
`Summary of the Specification ............................................................ 28
`C.
`Summary of the Prosecution History ................................................. 30
`VII. LEVEL OF ORDINARY SKILL IN THE ART .......................................... 32
`VIII. OVERVIEW OF THE PRIOR ART ............................................................ 34
`A. Overview of Goossens2002 ............................................................... 34
`
`Overview of Drake ............................................................................. 35
`B.
`Overview of Goossens2003 ............................................................... 37
`C.
`IX. SPECIFIC GROUNDS FOR PETITION ..................................................... 38
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`3.
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`4.
`
`5.
`
`6.
`7.
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`A. Ground I: Claims 1–6 and 9–16 Are Rendered Obvious by
`Goossens2002 in View of Drake ....................................................... 38
`1.
`Claim 1 ..................................................................................... 45
`2.
`Claim 2: “Integrated circuit according to claim 1, further
`comprising: at least one communication manager (CM)
`for managing the communication between different
`modules” .................................................................................. 66
`Claim 3: “The Integrated circuit of claim 1, further
`comprising at least one of a switch and a router” .................... 69
`Claim 4: “The Integrated circuit of claim 1, further
`comprising a chip, wherein the processing modules and
`the network are disposed on said chip” ................................... 70
`Claim 5: “The Integrated circuit of claim 1, wherein the
`connection properties comprise at least one of data
`transport ordering, flow control, throughput, latency, and
`lossiness” ................................................................................. 70
`Claim 6 ..................................................................................... 71
`Claim 9: “Integrated circuit according to claim 2, further
`comprising: at least one network interface means (NI),
`associated to each of said modules, for managing the
`communication between said modules and said network
`(N)” .......................................................................................... 77
`Claim 10 ................................................................................... 77
`Claim 11: “The method of claim 10, wherein the network
`manages traffic utilizing at least one of a switch and a
`router” ...................................................................................... 81
`10. Claim 12: “The method of claim 10, wherein the
`processing modules and the network are disposed on a
`chip” ......................................................................................... 81
`11. Claim 13: The method of claim 10, wherein the
`connection properties comprise at least one of data
`transport ordering, flow control, throughput, latency, and
`lossiness” ................................................................................. 81
`12. Claim 14: “The method of claim 10, further comprising
`the resource manager determining whether the target
`connection with the desired connection properties is
`available based on reading of a centralized or distributed
`property table comprising properties associated with the
`network” .................................................................................. 82
`
`8.
`9.
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`13. Claim 15: “The method of claim 10, further comprising
`the resource manager reserving the target connection
`after determining whether the target connection with the
`desired connection properties is available” ............................. 84
`14. Claim 16: “The method of claim 10, wherein the
`connection properties comprise at least one of
`throughput, latency and jitter” ................................................. 84
`
`B.
`
`3.
`
`4.
`
`Ground II: Claims 1-6 and 9-16 Are Rendered Obvious by
`Goossens2003 in view of Drake ........................................................ 85
`1.
`Claim 1 ..................................................................................... 91
`2.
`Claim 2: “Integrated circuit according to claim 1, further
`comprising: at least one communication manager (CM)
`for managing the communication between different
`modules” ................................................................................ 101
`Claim 3: “The Integrated circuit of claim 1, further
`comprising at least one of a switch and a router” .................. 102
`Claim 4: “The Integrated circuit of claim 1, further
`comprising a chip, wherein the processing modules and
`the network are disposed on said chip” ................................. 104
`Claim 5: “The Integrated circuit of claim 1, wherein the
`connection properties comprise at least one of data
`transport ordering, flow control, throughput, latency, and
`lossiness” ............................................................................... 104
`Claim 6 ................................................................................... 105
`Claim 9: “Integrated circuit according to claim 2, further
`comprising: at least one network interface means (NI),
`associated to each of said modules, for managing the
`communication between said modules and said network
`(N)” ........................................................................................ 108
`Claim 10 ................................................................................. 109
`Claim 11: “The method of claim 10, wherein the network
`manages traffic utilizing at least one of a switch and a
`router” .................................................................................... 112
`10. Claim 12: “The method of claim 10, wherein the
`processing modules and the network are disposed on a
`chip” ....................................................................................... 112
`11. Claim 13: The method of claim 10, wherein the
`connection properties comprise at least one of data
`
`5.
`
`6.
`7.
`
`8.
`9.
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`transport ordering, flow control, throughput, latency, and
`lossiness” ............................................................................... 113
`12. Claim 14: “The method of claim 10, further comprising
`the resource manager determining whether the target
`connection with the desired connection properties is
`available based on reading of a centralized or distributed
`property table comprising properties associated with the
`network” ................................................................................ 113
`13. Claim 15: “The method of claim 10, further comprising
`the resource manager reserving the target connection
`after determining whether the target connection with the
`desired connection properties is available” ........................... 114
`14. Claim 16: “The method of claim 10, wherein the
`connection properties comprise at least one of
`throughput, latency and jitter” ............................................... 114
`SECONDARY CONSIDERATIONS ..................................................... 115
`X.
`XI. CONCLUSION ......................................................................................... 116
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`
`LIST OF EXHIBITS
`
`Exhibit
`No.
`1001
`1002
`1003
`
`1004
`1005
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`1006
`1007
`
`1008
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`1009
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`1010
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`1011
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`1012
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`1013
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`1014
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`Description
`
`U.S. Patent No. 7,373,449 (the “ʼ449 Patent”)
`File History of U.S. Pat. No. 7,373,449
`Declaration of Todd Mowry Ph.D. in Support of Petition for Inter
`Partes Review of U.S. Patent No. 7,373,449
`Curriculum Vitae of Todd Mowry Ph.D.
`K. Goossens, et al., Networks on Silicon: Combining Best-Effort and
`Guaranteed Services (“Goossens2002”)
`U.S. Patent No. 5,461,611 (“Drake”)
`K. Goossens, et al., Guaranteeing the Quality of Services in Networks
`on Chip (“Goossens2003”)
`Ahmed Amine Jerraya & Wayne Wolf, Multiprocessor Systems-on-
`Chips (2005) (“Wolf”)
`Wael Badawy, System on Chip: The Challenge and Opportunities,
`SYSTEM ON CHIP FOR REAL-TIME APPLICATIONS, 3–16 (2003)
`(“Badawy”)
`Andrei Rădulescu et al., An Efficient On-Chip Network Interface
`Offering Guaranteed Services, Shared-Memory Abstraction, and
`Flexible Network Configuration, 2 PROC. DESIGN, AUTOMATION AND
`TEST IN EUR. CONF. & EXHIBITION 878 (2004) (“Rădulescu”)
`A. Campbell et al., Integrated Quality of Service for Multimedia
`Communications, Computing Dept.
`Lancaster University
`(“Campbell”)
`D. Kandlur et al., Real-Time Communication in Multihop Networks,
`IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, VOL.
`5, NO. 10 (1994) (“Kandlur”)
`Jose Duato, et al., Interconnection Networks: An Engineering
`Approach, IEEE COMPUTER SOCIETY PRESS, Ch. 7 (1997) (“Duato”)
`Axel Jantsch and Hannu Tenhunen, Networks on Chip, Ch. 1-3 (2003)
`(“Jantsch”)
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`Exhibit
`No.
`1015
`
`1016
`
`1017
`
`1018
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`Description
`
`David E. Culler and Jaswinder Pal Singh, Parallel Computer
`Architecture, A Hardware/Software Approach, Ch. 10 (1999)
`(“Culler”)
`Hugo De Man, System-on-chip design: Impact on Education and
`Research, IEEE DESIGN & TEST OF COMPUTERS, Vol. 16, No. 3, pp.
`11-19 (July-Sept. 1999) (“Man”)
`ETSI Technical Report, Trans European Trunked Radio (TETRA)
`system; Technical requirements specification, Part 2: Packet Data
`Optimised (PDO) systems (January 1994)
`U.S. Patent No. 5,828,658 (“Ottersten”)
`Joint Claim Construction and Prehearing Statement, Network Sys.
`Techs., LLC v. Tex. Instruments Inc., No. 2:22-cv-00482-RWS, Dkt.
`84 (E.D. Tex. Aug. 17, 2023)
`Pl.’s Opening Claim Construction Br., Network Sys. Techs., LLC v.
`Tex. Instruments Inc., No. 2:22-cv-00482-RWS, Dkt. 98 (E.D. Tex.
`Sept. 27, 2023)
`E. Rijpkema et al., Trade-offs in the Design of a Router with Both
`Guaranteed and Best-Effort Services for Networks on Chip, 150 IEEE
`PROC.-COMPUT. DIGIT. TECH. 294–302 (2003) (“Rijpkema”)
`M. Sgroi et al., Addressing the System-on-a-Chip Interconnect Woes
`Through Communication-Based Design (2001) (“Sgroi”)
`Yasusi Kanada, A Representation of Network Node QoS Control
`Policies Using Rule-based Building Blocks (2000) (“Kanada”)
`IEEE 100, The Authoritative Dictionary of IEEE Standards Terms
`(2000) (“IEEE Dictionary”)
`Declaration of Gordon MacPherson regarding K. Goossens, et al.,
`Networks on Silicon: Combining Best-Effort and Guaranteed Services
`IEEE Bibliographic Data Regarding K. Goossens, et al., Networks on
`Silicon: Combining Best-Effort and Guaranteed Services
`Declaration of the University of Texas at Austin Libraries regarding
`“Networks on Chip”
`SpringerLink Bibliographic Data Regarding “Networks on Chip”
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`Exhibit
`No.
`1029
`
`1030
`
`
`
`
`
`Description
`
`William J. Dally and Brian Towles, Route Packets, Not Wires: On-
`Chip Interconnection Networks, Computer Systems Laboratory
`Stanford University (2001) (“Dally”)
`Defendants’ Joint Claim Construction Br. (Excerpts), Network Sys.
`Techs., LLC v. Tex. Instruments Inc., No. 2:22-cv-00482-RWS, Dkt.
`77 (E.D. Tex. Oct. 12, 2023)
`
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`I, Dr. Todd Mowry, declare as follows:
`
` My name is Todd Mowry.
`
`
`
`I have been retained as an expert witness on behalf of Samsung
`
`Electronics Co., Ltd., (“Samsung” or “Petitioner”) for the above-captioned Petition
`
`for Inter Partes Review (“Petition”) of U.S. Patent No. 7,373,449 (the “’449 patent”)
`
`(Ex. 1001). I am being compensated for my time in connection with this Petition at
`
`my standard consulting rate of $650 per hour. My compensation is not affected by
`
`the outcome of this matter.
`
`
`
`I have been asked to provide my opinions regarding whether claims 1–
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`6 and 9–16 of the ’449 patent (the “Challenged Claims”) are invalid as obvious to a
`
`person having ordinary skill in the art at the time of the alleged invention.
`
`
`
`The ’449 patent issued on May 13, 2008, from U.S. Application No.
`
`10/530,267 (Ex-1002, “the ’267 Application”), which was filed on April 5, 2005.
`
`The ’267 Application is a national stage application (under 35 U.S.C. § 371) of
`
`PCT/IB03/04414, which was filed on October 7, 2003. The ’449 patent claims
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`priority to a foreign patent application, EP Application No. 02079196, which was
`
`filed on October 8, 2002.
`
`
`
`I am not currently, and have not at any time in the past been, an
`
`employee of Samsung. I have no financial interest in Samsung.
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`I.
`
`BACKGROUND AND QUALIFICATIONS
`
`I am a Professor in the Department of Computer Science at Carnegie
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`Mellon University. I also have a courtesy appointment in the Department of
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`Electrical and Computer Engineering. I have served on the faculty of Carnegie
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`Mellon University for twenty-six (26) years starting in 1997 through the present
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`(2023).
`
`
`
`I also served on the faculty of the University of Toronto for four (4)
`
`years between 1993 and 1997, in the Department of Electrical and Computer
`
`Engineering and a courtesy appointment in the Department of Computer Science.
`
`Prior to that appointment, I served as a Graduate Research Assistant in the
`
`Department of Electrical Engineering at Stanford University for four (4) years
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`between 1989 and 1993. As a faculty member, I have taught and continue to teach
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`courses and directed research in computer architecture, parallel processing,
`
`computer systems and software, compiler optimization, and operating systems.
`
`
`
`I received a B.S. degree in Electrical Engineering with Highest
`
`Distinction from the University of Virginia in May 1988. I received an M.S. in
`
`Electrical Engineering from Stanford University in June 1989, and a Ph.D. in
`
`Electrical Engineering from Stanford University in March 1994.
`
`
`
`I have worked in the computer industry in various capacities. I was a
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`part-time Computer Architect and then Computer Architecture Consultant at Silicon
`
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`Graphics, Inc. in Mountain View, California (formerly MIPS Computer Systems in
`
`Sunnyvale, California) from 1989 to 1993 and 1993 to 1996, respectively. I was a
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`Visiting Scientist at IBM in Toronto from 1996 to 2004. During that same time
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`period (1996 to 2004), I was also a Member of the Technical Advisory Board of
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`SandCraft, Inc. in Santa Clara, California. I was the Director of the Intel Research
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`Pittsburgh Lab at Intel Corporation in Pittsburgh, Pennsylvania from 2004 to 2007.
`
`
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`I have authored 19 journal articles and over 60 conference papers. I am
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`also an inventor on 5 patents.
`
`
`
`I am the recipient of several honors and awards: the Arthur Samuel
`
`Thesis Award (awarded by the Stanford Computer Science department to the top
`
`two Ph.D. theses in a given year), several IBM Faculty Development Awards (1996,
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`1997, 1998, 2000, 2001, 2002, and 2003), several Best Paper Awards (the Second
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`Symposium on Operating Systems Design and Implementation in 1996; the 20th
`
`International Conference on Data Engineering (ICDE) in 2004), the Alfred P. Sloan
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`Research Fellowship (awarded to researchers in recognition of distinguished
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`performance and a unique potential to make substantial contributions to their field),
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`the Most Thought-Provoking Idea Award in 2004 (awarded by the Architectural
`
`Support for Programming Languages and Operating Systems (ASPLOS)), the
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`TR100 Award in 1999 (awarded by MIT’s Technology Review magazine to the top
`
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`100 most promising young innovators in science and technology), and I became an
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`ACM Fellow in 2016.
`
`
`
`I am a member of the Institute of Electrical and Electronics Engineers
`
`(IEEE) and the Association of Computing Machinery (ACM). I was the Editor-in-
`
`Chief of ACM Transactions on Computer Systems from 2013 through 2018, which
`
`is the premier journal for computer systems research. (I was an Associate Editor for
`
`the journal prior to that, since 2001.) I was the Program Chair of the International
`
`Conference on Architectural Support for Programming Languages and Operating
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`Systems (ASPLOS) in 2010. I was the Co-Program Chair of the International
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`Conference on Parallel Architectures and Compilation Techniques (PACT) in 2001.
`
`I have been on the programming committee in various years for ASPLOS, the
`
`International Symposium on Computer Architecture (ISCA), the International
`
`Symposium on Microarchitectures, and the Workshop on Architectural and System
`
`Support for Improving Format.
`
`
`
`I have authored numerous publications relating to systems-on-chips
`
`(SOCs) comprised of multiple processors that communicate with each other via
`
`networks-on-chips (NOCs). For example, when the Association of Computing
`
`Machinery (ACM) made me an ACM Fellow in 2016, they explicitly recognized my
`
`research contributions in the area of thread-level speculation, which was a new
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`technique specifically motivated by these architectures. As other examples, my
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`work in the Log-Based Architectures project proposed a novel use of SOCs where
`
`logs were captured and shipped across NOCs to other processors on the same chip,
`
`and my work on on-chip memory compression helped to reduce the load on the NOC
`
`(and also led to an interesting observation about how memory compression had an
`
`unintended consequence on NOC energy, which we were able to fix).
`
`
`
`I am also the named inventor on multiple issued patents relating to
`
`processor architecture.
`
` My qualifications and publications are set forth more fully in my
`
`curriculum vitae, attached as Ex. 1004.
`
`II. MATERIALS AND OTHER INFORMATION CONSIDERED
`
`In forming the opinions expressed in this Declaration, I relied upon my
`
`education and experience in the relevant field of the art and have considered the
`
`viewpoint of a person having ordinary skill in the art (POSITA) at the time of the
`
`alleged invention.
`
`
`
`I have considered the materials referenced herein, including the ’449
`
`patent (Ex. 1001), the file history of the ’449 patent (Ex. 1002), the Petition, and
`
`other documents listed in the Exhibit List of the Petition, including:
`
`Description
`K. Goossens, et al., Networks on
`Silicon: Combining Best-Effort and
`Guaranteed Services
`(“Goossens2002”) (Ex. 1005)
`
`Date of Public Availability
`Published no later than August 7,
`2002
`
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`
`Description
`U.S. Patent No. 5,461,611 (“Drake”)
`(Ex. 1006)
`K. Goossens, et al., Guaranteeing the
`Quality of Services in Networks on
`Chip (“Goossens2003”) (Ex. 1007)
` The references listed above are prior art to the ’449 patent.
`
`Date of Public Availability
`Filed on June 7, 1994 and issued on
`October 24, 1996.
`Published no later than January 31,
`2003.
`
`III. UNDERSTANDING OF PATENT LAW
`
`I am not an attorney. For purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as listed below.
`
`A. The Level of Ordinary Skill in the Art
`
`It is my understanding that the level of ordinary skill in the art is based
`
`on a study of the patents at issue and their file histories, a study of the prior art cited
`
`therein, and knowledge of the following:
`
`• The level of education and experience of persons actively working in the
`field at the time the subject matter at issue was developed;
`
`• The types of problems encountered in the art at the time the subject matter
`was developed;
`
`• The prior art patents and publications;
`
`• The activities of others working in that field;
`
`• Prior art solutions to those problems; and
`
`• The sophistication of the technology at issue in this case.
`It is also my understand that these factors are not exhaustive, and merely a useful
`
`guide to determine the level of ordinary skill in the art.
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`B. Obviousness
`
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a POSITA at the time the application was filed.
`
`This means that, even if all of the requirements of a claim are not found in a single
`
`prior art reference, the claim is not patentable if the differences between the subject
`
`matter in the prior art and the subject matter in the claim would have been obvious
`
`to a POSITA at the time the application was filed.
`
`
`
`I have been informed and understand that a determination of whether a
`
`claim would have been obvious should be based upon several factors, including,
`
`among others:
`
`• the level of ordinary skill in the art at the time the application was filed;
`
`• the scope and content of the prior art; and
`
`• what differences, if any, existed between the claimed invention and the
`prior art.
`
`I have been informed and understand that the teachings of two or more
`
`references may be combined in the same way as disclosed in the claims, if such a
`
`combination would have been obvious to a POSITA. In determining whether a
`
`combination based on either a single reference or multiple references would have
`
`been obvious, it is appropriate to consider at least the following factors:
`
`• whether the teachings of the prior art references disclose known concepts
`combined in familiar ways, which, when combined, would yield
`predictable results;
`
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`• whether a POSITA could implement a predictable variation, and would
`see the benefit of doing so;
`
`• whether the claimed elements represent one of a limited number of
`known design choices, and would have a reasonable expectation of
`success by a POSITA;
`
`• whether a POSITA would have recognized a reason to combine known
`elements in the manner described in the claims;
`
`• whether there is some teaching or suggestion in the prior art to make the
`modification or combination of elements claimed in the patent; and
`
`• whether the innovation applies a known technique that had been used to
`improve a similar device or method in a similar way.
`
`
`I understand that a POSITA has ordinary creativity, and is not an
`
`automaton.
`
`
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`
`
`I understand that prior art to the ’449 patent includes patents and printed
`
`publications in the relevant art that predate the Priority Date of the ’449 patent.
`
`
`
`I understand
`
`that certain
`
`factors—often called “secondary
`
`considerations”—may support or rebut an assertion of obviousness of a claim. I
`
`understand that such secondary considerations include, among other things,
`
`commercial success of the alleged invention, skepticism of those having ordinary
`
`skill in the art at the time of the alleged invention, unexpected results of the alleged
`
`invention, any long-felt but unsolved need in the art that was satisfied by the alleged
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`Declaration of Dr. Mowry for Inter Partes Review of U.S. Patent No. 7,373,449
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`invention, the failure of others to make the alleged invention, praise of the alleged
`
`invention by those having ordinary skill in the art, and copying of the alleged
`
`invention by others in the field.
`
`
`
`I further understand that there must be a nexus—a connection—
`
`between any such secondary considerations and the alleged invention. I also
`
`understand that contemporaneous and independent invention by others is a
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`secondary consideration tending to show obviousness.
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`IV. SUMMARY OF OPINIONS
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`It is my opinion that claims 1–6, and 9–16 of the ’449 patent are (i)
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`rendered obvious by Goossens2002 in combination with Drake and (ii) rendered
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`obvious by Goossens2003 in combination with Drake.
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`V. OVERVIEW OF THE TECHNOLOGY
`A.
`Systems-on-Chip (SoC)
` Computer systems are comprised of a number of different components,
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`including processors (e.g, CPUs, GPUs, etc.), memory (e.g., SRAM, DRAM, etc.)
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`and various input/output (I/O) devices. As the capacity of integrated circuit (IC)
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`technology has improved exponentially over the years, it has enabled larger portions
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`of computer systems to be integrated onto single chips. For example, in the early
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`1970s, Intel was able to integrate an entire CPU onto a single chip: e.g., the Intel
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`4004, which was the first commercial “microprocessor”. Compared with CPUs
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`during the 1960s (with their numerous separate chips on motherboards), single-chip
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`microprocessors offered significant cost and energy savings.
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` As IC capacity has continued to increase well beyond what is needed
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`to implement a single processor, it has enabled “Systems-on-Chip” (SoC) designs
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`that include even more system components on a single chip: usually some
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`combination of processors (often including multiple CPUs and possibly accelerators
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`such as GPUs), portions of the memory hierarchy, and possibly I/O devices or
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`controllers. SoCs were well-known by the late 1990s, and are integrated on a silicon
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`die. See, e.g., Ex-1014 (Jantsch) at vii (“During the 1990s more and more processor
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`cores and large reusable components have been integrated on a single silicon die,
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`which has become known under the label System on Chip (SoC).”); Ex-1008 (Wolf)
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`at 1 (“An SoC is an integrated circuit that implements most or all of the functions of
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`a complete electronic system.”); Ex-1009 (Badawy) at 1 (“With the increase in the
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`number of logic gates that can be implemented on a single chip, various
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`functionalities … can be integrated into a single silicon chip, realizing an entire
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`system on chip (SoC)”). Thus, SoCs can also be referenced as System on Silicon.
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`See, e.g., Ex-1009 (Badawy) at 1 (An SoC “is also known as a system on silicon”);
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`Ex-1016 (Man) at 12 (“A SOC thus encapsulates system knowledge in a single
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`medium—silicon—which blurs the separation between component design and
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`system design.”).
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`B. Networks-on-Chip (NoC)
` To enable the various system components within a chip for an SoC
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`design to communicate with each other, an on-chip interconnect is needed. One such
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`on-chip interconnect is often referred to as a “Network on Chip” (NoC). Rather than
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`directly wiring together each pair of on-chip components via dedicated hardware
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`FIFO buffers and wires, the idea of a NoC design is to create a more general on-chip
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`interconnect that routes packets from sources to destinations, often traversing
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`multiple hops through on-chip routing switches. The rationale for this NoC
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`approach was described in the influential paper by Bill Dally and Brian Towles that
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`appeared in the Design Automation Conference (DAC)—the premier IC technology
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`conference—in June, 2001. Ex-1029 (Dally).
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` By integrating the interconnection network fully onto a chip, NoC
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`designs can potentially provide lower cost, lower latency, and higher bandwidth
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`relative to off-chip designs. To take full advantage of these potential benefits and to
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`provide scalability as the number of on-chip components increases, NoCs have
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`borrowed many design features from scalable interconnection networks that were
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`designed for large-scale parallel machines in the 1990s. See Ex-1015 (Culler) at
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`749–828; Ex-1010 (Radulescu) at 277 (“Networks have been the subject of research
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`for decades, both in the context of local and wide area networks (computer networks)
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`[], and as an interconnect for parallel machines []. Both are very much related to on-
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`chip networks, and many of the results in those fields are also applicable on chip.”);
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`Ex-1014 (Jantsch) at 86–95 (“[M]any research groups have concurrently proposed
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`the idea of using a packet switched communication network, similar to one used in
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`computer networks, for on chip communication.”); Ex-1013 (Duato) at vii-viii
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`(“Originally developed for the demanding communication requirements of
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`multicomputers, interconnection networks are beginning to replace buses as the
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`standard system-level interconnection.”).
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` Because NoCs can have more diverse types of communicating
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`components beyond traditional parallel machines (e.g., DMA engines transferring
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`data between I/O and on-chip memory, video streaming to frame buffers, CPU cache
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`misses to memory, data transfers between CPUs and GPUS, etc.), they are often
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`extended to also support quality-of-service (QoS) across different communication
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`streams.
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`C. Connections
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`In the field of networking, the term “connection” refers to a type of
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`communication link between two devices. Although the term may mean different
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`things across different layers of the OSI (Open Systems Interconnection) model
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`(e.g., in the physical layer, it might refer to a wire or cable that physically connects
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`two devices), it is commonly associated with the OSI transport layer, which focuses
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`on end-to-end communication services. The transport layer can operate in one of
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`two modes: connection-oriented or connectionless. For wide area networks, an
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`example of a connection-oriented protocol is TCP/IP (Transmission Control
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`Protocol/Internet Protocol),