UNITED STATES PATENT AND TRADEMARK OFFICE
`
`__________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`__________________________
`
`MONOLITHIC POWER SYSTEMS, INC.,
`
`Petitioners,
`
`v.
`
`GREENTHREAD, LLC,
`Patent Owner.
`
`PTAB Case Nos.: IPR2024-00468 on U.S. Patent No. 8,421,195; IPR2024-00469
`on U.S. Patent No. 9,190,502; and IPR2024-00470 on U.S. Patent No. 11,121,222
`__________________________
`
`DECLARATION OF STEPHEN CAMPBELL IN SUPPORT OF PETITION
`FOR INTER PARTES REVIEW OF
`U.S. PATENT NOS. 8,421,195; 9,190,502; 11,121,222
`
`165352825.6
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`TABLE OF CONTENTS
`
`
`I.
`
`INTRODUCTION .......................................................................................... 1
`A. Qualifications ....................................................................................... 2
`1.
`Education and Work Experience ............................................... 2
`2.
`Curriculum Vitae ........................................................................ 5
`B. Materials Reviewed .............................................................................. 5
`C.
`Level of Ordinary Skill in the Art ........................................................ 5
`D.
`Summary of Opinions .......................................................................... 6
`II. OVERVIEW OF THE TECHNOLOGY ........................................................ 6
`A.
`Priority Date of the Claims ................................................................... 6
`B. Overview of the ’195, ’222, and ’502 Patents ..................................... 7
`C.
`Static Unidirectional Electric Drift Fields .......................................... 11
`D.
`Claim Construction ............................................................................ 21
`III. UNPATENTABILITY OF THE ’195, ’222, and ’502 PATENT
`CLAIMS ....................................................................................................... 22
`A.
`Standards for Invalidity ...................................................................... 22
`1.
`Obviousness ............................................................................. 22
`’195 Patent .......................................................................................... 24
`1.
`Onoda Renders Obvious Claims 1, 2, 3, 5, and 6. ................... 24
`2.
`Ground II: Onoda in view of Nishizawa Renders Obvious
`Claims 1, 2, 3, 5, and 6. ........................................................... 51
`Ground III: Kawagoe Renders Obvious Claims 1, 2, 3, 5,
`and 6. ........................................................................................ 58
`’222 Patent .......................................................................................... 87
`1.
`Ground I: Onoda Renders Obvious Claim 44. ......................... 87
`2.
`Ground II: Onoda in view of Nishizawa Renders Obvious
`Claim 44. .................................................................................. 90
`Ground III: Kawagoe Renders Obvious Claim 44. ................ 92
`3.
`’502 Patent .......................................................................................... 95
`
`D.
`
`B.
`
`C.
`
`3.
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`1.
`2.
`
`Ground I: Onoda Renders Obvious Claims 7-8. ...................... 95
`Ground II: Onoda in view of Nishizawa Renders Obvious
`Claims 7-8 .............................................................................. 100
`Ground III: Kawagoe Renders Obvious Claims 7-8. ............ 101
`3.
`IV. CONCLUSION ........................................................................................... 105
`
`
`
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`LIST OF APPENDICES
`
`Curriculum Vitae of EXPERT
`
`
`Appendix A
`
`
`
`
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`I.
`
`INTRODUCTION
`I, Stephen Campbell, have been retained by Petitioner Monolithic
`
`1.
`
`Power Systems, Inc. (“Petitioner”) to investigate and opine on certain issues relating
`
`to United States Patent Nos. 8,421,195; 9,190,502; and 11,121,222 (the “’195 Patent,”
`
`“’502 Patent,” and “’222 Patent,” respectively) in its Petitions for Inter Partes
`
`Reviews. The Petition requests that the Patent Trial and Appeal Board (“PTAB” or
`
`“Board”) review and cancel claims 1-3 and 5-6 of the ’195 Patent, claims 7-8 of
`
`the ’502 Patent, and claim 44 of the ’222 Patent.
`
`2.
`
`I have included the analysis of these three patents in a single declaration
`
`due to their overlap in claims. I have limited my analysis to the above-identified
`
`claims and my lack of analysis with respect to other claims of the ’195, ’502,
`
`and ’222 Patents should in no way be interpreted as a concession of their validity. I
`
`reserve the right to provide further opinion in other proceedings regarding those
`
`claims.
`
`3.
`
`The opinions set forth in this declaration are based on my personal
`
`knowledge, my professional judgment, and my analysis of the materials and
`
`information referenced in this declaration and its exhibits.
`
`4.
`
`I am being compensated for consulting services. I am also reimbursed
`
`for reasonable and customary expenses associated with my work in this case. I
`
`receive no other forms of compensation related to this case. My compensation does
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`not depend on the outcome of this post-grant review or the co-pending district court
`
`litigation, and I have no other financial interest in the post-grant review or the co-
`
`pending district court or Petitioner.
`
`5.
`
`I understand that the ’195, ’502, and ’222 Patents have been assigned
`
`to Greenthread, LLC. I make no opinion on whether this assignment or ownership
`
`is correct.
`
`6.
`
`This declaration is based on the information currently available to me.
`
`To the extent that additional information becomes available, I reserve the right to
`
`continue my investigation and study, which may include a review of documents and
`
`information that may be produced, as well as testimony from depositions that have
`
`not yet been taken.
`
`A. Qualifications
`Education and Work Experience
`1.
`I received my Bachelor’s degree in Physics from the University of St.
`
`7.
`
`Thomas (St. Paul, Minnesota) in 1975, my M.S. and Ph.D. in Physics from
`
`Northwestern University (Evanston, Illinois) in 1978 and 1981, respectively. I then
`
`joined Sperry, now called Unisys, in 1981 as a CMOS process development engineer.
`
`In 1982, I was assigned the lead engineer for the 1.2 µm technology process
`
`development effort. In 1984 I was promoted to head of silicon research for the
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`company. This involved a wide variety of process technologies for submicron
`
`CMOS.
`
`8.
`
`In 1986, I joined the University of Minnesota as an Assistant Professor
`
`in the Electrical Engineering Department. My research at the University involved
`
`semiconductor processing, materials, and device structures. I raised more than
`
`$100M in various grants and successful submissions to companies and industry
`
`consortiums such as the Semiconductor Research Association, as well as State and
`
`US government agencies including DARPA and the National Science Foundation.
`
`The first ten years of my career at the University concentrated on the development
`
`of rapid thermal annealing for 200 mm wafers, particle control in CVD systems, and
`
`the development of high uniformity wafer cleaning systems. The next ten years were
`
`dedicated to the invention and development of high permittivity (aka high-k) films
`
`for use as the gate insulators. This is necessary to allow the development of deeply
`
`scaled CMOS devices. This technology has been widely adopted for nanoscale
`
`CMOS devices. In the last fifteen years at the University, my work involved the
`
`development of low-cost tandem photovoltaics, micro electromechanical systems
`
`(MEMS), and novel materials. The latter included a chronic deep brain
`
`sense/stimulation system and very high-speed mechanical switches. Finally, I
`
`developed processes for the fabrication of novel 2D materials such as black arsenic,
`
`and fabricated transistors using these materials. I retired from the University in 2021.
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`9.
`
`A brief summary of my work at the University would include:
`
`A. Approximately 200 publications
`
`B. The leading textbook on semiconductor technology. Currently in
`
`its fourth edition, Fabrication Engineering at the Micro and
`
`Nanoscale (Oxford 1996, 2000, 2008, 2013) is the dominant text
`
`on the topic.
`
`C. Honors from outside the University such as being named a
`
`Presidential Young Investigator by the National Science
`
`Foundation and a Life Fellow by the Institute of Electrical and
`
`Electronic Engineers (IEEE).
`
`D. Honors within the University including outstanding service and
`
`outstanding teaching.
`
`E. As the Director of the University’s Nanofabrication Center, I
`
`increased lab usage from 30 to more than 300 users, enabling
`
`millions of dollars research awards annually by Minnesota
`
`faculty, and leading to the construction of a new $80M building
`
`with a expansive cleanroom facility.
`
`10. Since retiring from the University, I have consulted with
`
`semiconductor companies including patent litigation. My work with these
`
`companies has been quite successful.
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`Curriculum Vitae
`2.
`11. A copy of my curriculum vitae is attached as Appendix A to this
`
`declaration.
`
`B. Materials Reviewed
`12. My opinions expressed in this declaration are based on documents and
`
`materials identified in this declaration, including the ’195, ’502, and ’222 Patents,
`
`the prior art references and background materials discussed in this declaration, and
`
`the other references specifically identified in this declaration. I have considered
`
`these materials in their entirety, even if only portions are discussed here.
`
`13.
`
`I have also relied on my own experience and expertise in semiconductor
`
`fabrication.
`
`C. Level of Ordinary Skill in the Art
`I am not an attorney and offer no legal opinions. I have been informed
`14.
`
`about certain aspects of the law for purposes of my analyses and opinions.
`
`15.
`
`I understand that in analyzing questions of invalidity and infringement,
`
`the perspective of a person having ordinary skill in the art (“POSITA”) is often
`
`implicated, and the Court may need assistance in determining that level of skill.
`
`16.
`
`I understand that the claims and written description of a patent must be
`
`understood from the perspective of a POSITA. I have been informed that the
`
`following factors may affect the level of skill of a POSA: (1) the educational level
`
`of the inventor; (2) the type of problems encountered in the art; (3) the prior-art
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`solutions to those problems; (4) the rapidity with which innovations are made; (5)
`
`the sophistication of the technology; and (6) the educational level of active workers
`
`in the field. A person of ordinary skill in the art is also a person of ordinary creativity
`
`in the art.
`
`17.
`
`In my opinion, a POSITA of the subject matter of the ’195, ’502, and
`
`’222 Patents would have had a Bachelor’s degree in electrical engineering, material
`
`science, applied physics, or a related field, and four years of experience in
`
`semiconductor design and manufacturing or equivalent work experience. Additional
`
`education might compensate for a deficiency in experience, and vice-versa.
`
`D.
`18.
`
`Summary of Opinions
`I have reviewed and analyzed the ’195, ’502, and ’222 Patents.
`
`19. Based on my review and analysis, it is my opinion that claims 1-3 and
`
`5-6 of the ’195 Patent, claims 7-8 of the ’502 Patent, and claim 44 of the ’222 Patent
`
`are invalid as obvious by: (1) Onoda; (2) Nishizawa; and (3) Kawagoe.
`
`II. OVERVIEW OF THE TECHNOLOGY
`Priority Date of the Claims
`A.
`20.
`I have been informed that a U.S. patent application may claim the
`
`benefit of the filing date of an earlier patent application if the earlier patent
`
`application disclosed each limitation of the invention claimed in the later-filed U.S.
`
`patent application. I have also been informed that priority is determined on a claim-
`
`by-claim basis so that certain claims of a patent may be entitled to the priority date
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`of an earlier-filed patent application even if other claims of the same patent are not
`
`entitled to that priority date.
`
`21.
`
`I have also been informed that a patented claim is invalid if the claimed
`
`invention was patented, described in a printed publication, or in public use, on sale,
`
`or otherwise available to the public before the effective filing date of the claimed
`
`invention, or the claimed invention was described in an issued patent or a published
`
`patent application that was effectively filed before the effective filing date of the
`
`claimed invention.
`
`22. The ’502 and ’222 Patents claim priority to the ’195 Patent, which
`
`claims priority to Sept. 3, 2004. All of the ’195, ’502, and ’222 Patent claims claim
`
`priority to Sept. 3, 2004.
`
`B. Overview of the ’195, ’502, and ’222 Patents
`23. As an initial matter, the independent claims of the ’195, ’502, and ’222
`
`Patents are nearly identical. A table showing the claim language, with highlighted
`
`substantive differences, is provided below. Claim 1 of the ’195 and ’502 Patents
`
`recite “said” while claim 7 of the ’502 Patent recites “the.”
`
`’195 Patent
`Claim 1
`A CMOS Semiconductor
`device comprising:
`a surface layer;
`a substrate;
`an active region including
`a source and a drain,
`
`’222 Patent
`Claim 44
`A CMOS Semiconductor
`device comprising:
`a surface layer;
`a substrate;
`an active region including
`a source and a drain,
`
`’502 Patent
`Claim 7
`A semiconductor device
`comprising:
`a surface layer;
`a substrate;
`an active region including
`a source and a drain,
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`disposed on one surface
`of said surface layer;
`a
`single
`drift
`layer
`disposed between
`the
`other surface of said
`surface
`layer and said
`substrate,
`said drift layer having a
`graded concentration of
`dopants
`extending
`between
`said
`surface
`layer and said substrate,
`said drift layer further
`having
`a
`first
`static
`unidirectional
`electric
`drift field
`to aid
`the
`movement of minority
`carriers from said surface
`layer to said substrate;
`and
`at least one well region
`disposed in said single
`drift
`layer, said well
`region having a graded
`concentration of dopants
`and
`a
`second
`static
`unidirectional
`electric
`drift field
`to aid
`the
`movement of minority
`carriers from said surface
`layer to said substrate.
`
`layer
`the
`the
`the
`
`disposed on one surface
`of the surface layer;
`a
`single
`drift
`disposed between
`other
`surface of
`surface
`layer and
`substrate,
`the drift layer having a
`graded concentration of
`dopants
`extending
`between the surface layer
`and the substrate, the drift
`layer further having a first
`static
`unidirectional
`electric drift field to aid
`the movement of carriers
`from the surface layer to
`an area of the substrate
`where there are no active
`regions; and
`at least one well region
`disposed in the single drift
`layer,
`the well region
`having
`a
`graded
`concentration of dopants
`and
`a
`second
`static
`unidirectional
`electric
`drift field
`to aid
`the
`movement of
`carriers
`from the surface layer to
`the area of the substrate
`where there are no active
`regions.
`
`
`
`disposed on one surface
`of said surface layer;
`a
`single
`drift
`layer
`disposed between
`the
`other surface of said
`surface
`layer and said
`substrate,
`said drift layer having a
`graded concentration of
`dopants generating a first
`static
`unidirectional
`electric drift field to aid
`the movement of minority
`carriers from said surface
`layer to said substrate;
`and
`
`at least one well region
`disposed in said single
`drift
`layer, said well
`region having a graded
`concentration of dopants
`generating a second static
`unidirectional
`electric
`drift field
`to aid
`the
`movement of minority
`carriers from said surface
`layer to said substrate.
`
`24. The ’195, ’502, and ’222 Patents all share a similar specification. The
`
`below reference is to the earliest filed application (the ’195 Patent). There are
`
`analogous citations to the other patents that describe the same subject matter.
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`25. The ’195, ’502, and ’222 Patents describe a CMOS semiconductor
`
`device that has semiconductor layers that have been doped. (’195 Patent at Abstract
`
`& 3:30-33; ’502 Patent at Abstract & 3:38-44; ’222 Patent at Abstract & 3:53-59.)
`
`The ’195, ’502, and ’222 Patents state that the doping profile is graded, to enable an
`
`electric drift that would sweep minority carriers from semiconductor’s surface to its
`
`substrate. (Id.)
`
`26. The ’195, ’502, and ’222 Patents acknowledge that graded doping
`
`profiles have been used. They state that some prior art bipolar junction transistors
`
`employed a graded dopant base to create an “‘aiding drift field’ to enhance the
`
`diffusing minority carrier’s speed from emitter to collector.” (’195 Patent at 1:34-
`
`36; ’502 Patent at 1:38-40; ’222 Patent at 1:46-48.) The ’195, ’502, and ’222 Patents
`
`state that this had deficiencies because “most semiconductor devices … still use a
`
`uniformly doped drift epitaxial region in the base.” (’195 Patent at 1:36-40; ’502
`
`Patent at 1:40-44; ’222 Patent at 1:46-53.)
`
`27. The ’195, ’502, and ’222 Patents state that these purported problems of
`
`the prior art could be improved by having an epitaxial layer at the surface that has a
`
`graded dopant profile. (’195 Patent at 3:30-35; see also id. at 4:28-29; 2:51-67; ’502
`
`Patent at 3:38-44 & 2:55-3:17; ’222 Patent at 3:53-59 & 3:4-35.) This would carry
`
`minority carriers from the surface to the substrate (indicated by arrows in FIG. 5(b)).
`
`(Id.)
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`(’195, ’502, and ’222 Patents at FIG. 5(b).)
`In my opinion, doping profiles with a gradient (i.e., non-uniform) was
`28.
`
`well known. It was common in the industry, and widely employed via common
`
`techniques. For example, thermally diffusing dopants was a common technique in
`
`semiconductor formation, and it provided for a graded dopant profile in the
`
`semiconductor layers by the nature of the process. A dopant would be introduced to
`
`the surface, and thereafter thermally diffused. There would be a greater
`
`concentration at the surface and then a downward gradient where the concentration
`
`disperses away from the surface.
`
`29. The ’195, ’502, and ’222 Patents echo the well-matured nature of the
`
`field with respect to creating doping profiles. Doping in the art was widely known
`
`to be done in order to create various layers where various regions are doped to be N
`
`or P type, along with associated drain and source regions, to create PNP or NPN
`
`transistors. This is fundamental to forming transistors.
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`30.
`
`It was also well known to use several doping gradients to control
`
`electric fields. The ’195, ’502, and ’222 Patents show the doping gradients at the
`
`emitter (decreasing as a function of distance) and collector (increasing upward).
`
`(’195 Patent at 1:34-36 and FIG. 1; ’502 Patent at 1:38-40 and FIG. 1; ’222 Patent
`
`at 1:46-48 and FIG. 1.) In my opinion, the ’195, ’502, and ’222 Patents confirm the
`
`well-known nature of various doping profiles by merely listing them by name (e.g.,
`
`“linear, quasi linear, exponential”). (’195 Patent at 2:40-42; ’502 Patent at 2:44-
`
`46; ’222 Patent at 2:60-62.) I consider the first two to have a change in concentration
`
`no more than a factor of ten and are usually displayed on a linear-linear plot. The
`
`latter has a change in concentration more than a factor of ten and are usually
`
`displayed on a log-linear plot. Gaussian and error function curves are examples of
`
`exponential profiles.
`
`31. The ’195, ’502, and ’222 Patents also did not provide any new layers to
`
`apply those known doping techniques. The layers described are routine and known,
`
`and this is confirmed by the ’195, ’502, and ’222 Patents describing various known
`
`semiconductor layers when describing the prior art. (’195 Patent at 1:34-36 and FIG.
`
`1; ’502 Patent at 1:38-40 and FIG. 1; ’222 Patent at 1:46-48 and FIG. 1.)
`
`C. Overview of the Technical Concepts
`32. My analysis will primarily rely on prior art patents Onoda, Nishizawa,
`
`and Kawagoe to show that the ’195, ’502, and ’222 patents are invalid. All three
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`prior art patents deal with the same technical challenge as the patents being
`
`challenged: how to protect electronic circuits from impacts of high energy photons
`
`such as x-rays or high energy particles such as alpha particles. When a high-energy
`
`collision takes place in a semiconductor, it creates a very large number of negatively
`
`charged electrons and positively charged holes. Of particular interest are the
`
`minority carriers such as electrons in a p-type region. If enough of these electrons
`
`are collected by the circuitry on the surface of the semiconductor, they can introduce
`
`faults in the circuit. As will be discussed, these charged species move in response to
`
`an electric field, and so an electric field that is properly constructed will push the
`
`minority carriers away from the surface, making their collection much less probable.
`
`I will also point out that an electric field caused by a doping profile can improve the
`
`performance of photosensing devices (Patents from Jastrzebski and from Kamins)
`
`by drifting minority carriers into the substrate.
`
`33. Onoda, Nishizawa, and Kawagoe cite latch-up and/or soft errors to
`
`motivate the need for the innovation. Soft errors occur when the circuitry collects
`
`enough of the minority carriers to change the voltage of that part of the circuit. Thus,
`
`a logical “1” becomes a logical “0”, or vice versa. It is a soft error in the sense that
`
`the circuitry is not damaged, only the stored information is corrupted. Latch-up, on
`
`the other hand, can be destructive. The basic element of a CMOS circuit is the
`
`inverter consisting of one NMOS transistor and one PMOS transistor. In addition to
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`the two MOSFETs, parasitic bipolar transistors are automatically formed in the
`
`active region of the devices. These bipolar transistors are also inevitably connected
`
`so as to create a latch. Once triggered, the latch remains in the state it enters until the
`
`circuit forces a change or until the circuit is powered down. In this case the minority
`
`carriers collected by part of the circuitry provide the trigger to start the latch-up
`
`process.
`
`34. While the exact faults vary slightly from patent to patent, the source of
`
`the faults (the collection of excess minority carriers) and the proposed solution (a
`
`static electric field to drift excess minority carriers away from the circuit) are
`
`identical.
`
`Static Unidirectional Electric Drift Fields
`D.
`35. The ’195, ’502, and ’222 Patents state that a graded doping
`
`concentration sweeps minority carriers to the substrate. (’195 Patent at 3:30-
`
`33; ’502 Patent 3:38-44; ’222 Patent at 3:53-59.)
`
`Hence, a novel technique has been described here by creating a
`drift field to sweep these unwanted minority carriers into the
`substrate as quickly as possible, from the active circuitry at the
`surface. In a preferred embodiment, the subterrain n-layer has a
`graded donor concentration to sweep the minority carriers deep
`into the substrate.
`In my opinion, Patent Owner represented to the Patent and Trademark
`
`36.
`
`Office that a graded dopant concentration creates, as an inherent physical property,
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`a static unidirectional electric drift field. Patent Owner argued this in the ’195 Patent
`
`prosecution, and the ’502 Patent and ’222 Patents claim priority to that application.
`
`To argue for written description support in the specification of the ’195 Patent, the
`
`Patent Owner argued that:
`
`“[T]he graded dopant concentration itself creates a ‘built-in’
`electrical field that forces the movement of carriers into a
`particular direction, whereby the ‘direction’ of the electrical field
`and the resulting direction of the carrier movement depends solely
`on the slope of the graded concentration of dopant.”
`(’195 Patent App., App. No. 11/622,496, Apr. 17, 2012 Amendment at
`7.)
`37. Patent Owner stated that:
`
`“a unidirectional drift (electric) field necessarily affects all the
`present minority carriers in the same way… Depending on the
`particular slope of the graded concentration of dopant, all
`minority carriers are either swept ‘down’ … or ‘up…’” (’195
`Patent App., App. No. 11/622,496, Apr. 17, 2012 Amendment at
`6-7.)
`38. Patent Owner referenced U.S. Pat. No. 4,481,522 (“Jastrzebski”) in
`
`support. (’195 Patent App., App. No. 11/622,496, Apr. 17, 2012 Amendment at 7.).
`
`Patent Owner stated that:
`
`“With regard to the existence of a "built-in" electric field created
`by a graded dopant density, see, e.g., Jastrzebski (US 4,481,522)
`col. 5, lines 11-13 (cited in Office Action). Applicant respectfully
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`submits that this inherent “built-in” unidirectional electric field is
`the additional parameter for ensuring that all minority carriers are
`being moved in one direction and which parameter the Office
`Action deemed to be missing from the disclosure.”
`(Jastrzebski at FIGS. 1a, 1b.)
`Jastrzebski confirms this inherent physical property resulting from a
`39.
`
`graded dopant. It states that a downward-sloping graded-dopant concentration
`
`creates an electric drift field that “force[s] most of the charge carriers … deep into
`
`the substrate[.]” (Jastrzebski at 5:14-22; id. at 2:27-32 (“This is done by creating a
`
`field, such as a drift field, in the semiconductor substrate to sweep minority charge
`
`carriers…into the bulk [substrate], away from the electrode-bearing surface of the
`
`substrate.”).).
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`40.
`
`Jastrzebski at 5:5-24 discloses:
`
`
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`These background striation and cross-talk problems are
`surmounted by constructing CCD shift registers, as exemplified
`by the FIG. 1a structural segment, in accordance with the present
`invention, so that there is an electric field normal to the surface
`11 that tends to force carriers deeper into the bulk away from the
`depletion regions induced adjacent to surface 11. This electric
`field can be a drift field created by a graded concentration of
`doping in the substrate. In the FIG. 1a structural segment the
`gradient of doping concentration would be normal, or
`perpendicular, to the surface 11 of substrate 10, with the doping
`concentration decreasing with depth from surface 11. The drift
`field is accordingly directed to force most of the charge carriers
`generated outside a depletion region deep into the substrate 10
`bulk. In these portions of the bulk remote from surface 11 of
`substrate 10 the charge carriers recombine. Arrangements can
`also be made to place deep drain structures to dispose of the
`charge carriers driven into these remote portions of the bulk.
`41. Patent Owner made the same representation to the Patent Office
`
`regarding U.S. Pat. No. 4,160,985 (“Kamins”). (’195 Patent App., App. No.
`
`11/622,496, Apr. 17, 2012 Amendment at 7.). Patent Owner stated:
`
`Kamins discloses a photosensing device in which selective
`doping of a semiconductor substrate of the device produces
`electric fields in the substrate which accelerate photo generated
`charge carriers toward or away from the surface of the device.
`Abstract, Fig. 3.
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`42. According to Patent Owner, Kamins’ Figure 3 shows “two electrical
`
`fields with opposing directions” (highlighted in blue and yellow) that correspond to
`
`increasing and decreasing graded-dopant concentrations, respectively. (Id. at 237,
`
`253 (citing Kamins at 3:6-13, FIGS. 2-3).)
`
`(Kamins at FIG. 3.)
`43. Patent Owner argued that:
`
`
`
`In particular, Kamins' disclosure further states that "[t]he carriers
`therefore tend to be accelerated either toward the nearest
`photosensor or away from the surface. More specifically, carriers
`created below the maximum dopant concentration are accelerated
`into the substrate [ ... ], while carriers created above the maximum
`dopant concentration are accelerated toward the surface [ ... ]."
`Col. 3, Lines 6-13, Fig. 2 (showing minority carries accelerated
`into the substrate and the surface layer, depending on the location
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`of the carriers relative to the maximum dopant concentration
`within the "buried layer" 21) and Fig. 3 (showing two electrical
`fields with opposing directions, away from the area of maximum
`dopant concentration towards both the surface layer and the
`substrate, respectively).
`44. Kamins at 2:64-3:18 teaches that a graded dopant concentration creates
`
`electric fields:
`
`FIG. 3 schematically illustrates profiles of doping concentration
`vs. depth into substrate 19. Curve 24 represents the N-type
`dopants, while curve 26 indicates the P+ -type doping for
`photosensors 11, 13 etc. The non-uniform dopant concentration
`in the substrate creates electric fields in the substrate, indicated by
`arrows labeled "ε" in FIGS. 2 and 3. In devices fabricated as
`described above, the electric field in the substrate is about 460
`V/cm near the surface, decreasing to 60 V/cm at 1 μm above the
`maximum dopant concentration. The carriers therefore tend to be
`accelerated either toward the nearest photosensor or away from
`the surface. More specifically, carriers created below the
`maximum dopant concentration are accelerated into the substrate
`where they recombine without contributing to the collected
`current of any sensor, while carriers created above the maximum
`dopant concentration are accelerated toward the surface where
`they increase the collected current of the adjacent photosensor. In
`either case, the probability of a carrier reaching a distant sensor is
`reduced. The field also leads to more rapid collection of
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`photogenerated carriers, thus improving the frequency response
`of the device.
`45. FIG. 3 of Kamins depicts these two electric fields that are inherently
`
`created by a graded dopant concentration.
`
`46. Kamins depicts the minority carriers in FIG. 2, stating that it provides
`
`“built-in electric fields into the structure so that a directional drift motion is
`
`superposed on the random thermal diffusion of the charge carriers.” (Kamins at
`
`
`
`2:32-36.)
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`47. Patent Owner also described “static” with respect to Kamins and
`
`conceded that it “discloses the presence of a ‘static’ drift field, ‘because the drift
`
`field is created by graded concentration of dopants which does not change over
`
`time.’” Patent Owner stated (’195 Patent App., App. No. 11/622,496, Oct. 15, 2015
`
`Amendment at 6 (citing Office Action ¶ 4 p.4 lines 1-3, further citing to Kamins,
`
`Col. 2, lines 15-16; Col. 2, line 64- Col. 3, line 2; Col. 1,