( 12 ) United States Patent
`Rao
`
`US 11,316,014 B2
`( 10 ) Patent No .:
`( 45 ) Date of Patent :
`* Apr . 26 , 2022
`
`US011316014B2
`
`( * ) Notice :
`
`( 71 )
`
`9
`
`( 54 ) SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`Applicant : GREENTHREAD , LLC , Dallas , TX
`( US )
`( 72 ) Inventor : G. R. Mohan Rao , Allen , TX ( US )
`( 73 ) Assignee : GREENTHREAD , LLC , Dallas , TX
`( US )
`Subject to any disclaimer , the term of this
`patent is extended or adjusted under 35
`U.S.C. 154 ( b ) by 0 days .
`This patent is subject to a terminal dis
`claimer .
`( 21 ) Appl . No .: 17 / 371,839
`( 22 ) Filed :
`Jul . 9 , 2021
`( 65 )
`Prior Publication Data
`Nov. 18 , 2021
`US 2021/0359086 A1
`Related U.S. Application Data
`( 60 ) Continuation of application No. 16 / 947,294 , filed on
`Jul . 27 , 2020 , now Pat . No. 11,121,222 , which is a
`( Continued )
`
`( 51 ) Int . Ci .
`HOIL 29/10
`HOIL 27/11524
`
`( 52 ) U.S. Ci .
`CPC
`
`( 2006.01 )
`( 2017.01 )
`( Continued )
`HOIL 29/1095 ( 2013.01 ) ; HOIL 27/11521
`( 2013.01 ) ; HOIL 27/11524 ( 2013.01 ) ;
`( Continued )
`( 58 ) Field of Classification Search
`CPC
`
`( Continued )
`
`HO1L 29/1095
`
`Access Transistor
`
`( 56 )
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,160,985 A
`4,684,971 A
`
`7/1979 Kamins et al .
`8/1987 Payne
`( Continued )
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`
`3/1989
`s6482563 A
`2/2003
`2003051551 A
`( Continued )
`
`OTHER PUBLICATIONS
`
`IPR2020-00288 – Exhibit 1029 - Claim Construction District Court
`Apr. 20 , 2020 .
`
`( Continued )
`
`Primary Examiner Ajay Arora
`( 74 ) Attorney , Agent , or Firm Gregory M. Howison
`
`( 57 )
`ABSTRACT
`Most semiconductor devices manufactured today , have uni
`form dopant concentration , either in the lateral or vertical
`device active ( and isolation ) regions . By grading the dopant
`concentration , the performance in various semiconductor
`devices can be significantly improved . Performance
`improvements can be obtained in application specific areas
`like increase in frequency of operation for digital logic ,
`various power MOSFET and IGBT ICs , improvement in
`refresh time for DRAMs , decrease in programming time for
`nonvolatile memory , better visual quality including pixel
`resolution and color sensitivity for imaging ICs , better
`sensitivity for varactors in tunable filters , higher drive capa
`bilities for iFETs , and a host of other applications .
`
`a
`
`30 Claims , 10 Drawing Sheets
`
`Storage Capacitor or
`sensor element
`
`H
`
`Graded dopant region
`
`HHH
`
`P
`
`Greenthread Ex. 2072, p. 1 of 16
`Semiconductor v. Greenthread
`
`

`

`US 11,316,014 B2
`Page 2
`
`Related U.S. Application Data
`continuation of application No. 16 / 717,950 , filed on
`Dec. 17 , 2019 , now Pat . No. 10,734,481 , which is a
`continuation of application No. 15 / 590,282 , filed on
`May 9 , 2017 , now Pat . No. 10,510,842 , which is a
`continuation of application No. 14 / 931,636 , filed on
`Nov. 3 , 2015 , now Pat . No. 9,647,070 , which is a
`continuation of application No. 14 / 515,584 , filed on
`Oct. 16 , 2014 , now Pat . No. 9,190,502 , which is a
`continuation of application No. 13 / 854,319 , filed on
`Apr. 1 , 2013 , now aband
`which is a continuation
`of application No. 11 / 622,496 , filed on Jan. 12 , 2007 ,
`now Pat . No. 8,421,195 , which is a division of
`application No. 10 / 934,915 , filed on Sep. 3 , 2004 ,
`now abandoned .
`( 51 ) Int . Ci .
`HOIL 27/146
`HOIL 27/11521
`HOIL 29/739
`HOIL 29/36
`HOIL 27/02
`HOIL 27/108
`( 52 ) U.S. CI .
`CPC
`
`.
`
`( 2006.01 )
`( 2017.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`
`( 56 )
`
`HOIL 27/14643 ( 2013.01 ) ; HOIL 29/36
`( 2013.01 ) ; HOIL 29/7395 ( 2013.01 ) ; HOIL
`27/0214 ( 2013.01 ) ; HOIL 27/10844 ( 2013.01 )
`( 58 ) Field of Classification Search
`USPC
`257/25
`See application file for complete search history .
`References Cited
`U.S. PATENT DOCUMENTS
`4,688,063 A
`4,907,058 A
`4,994,887 A
`5,835,402 A
`6,025,237 A
`6,384,431 B1
`6,465,862 B1
`2001/0028097 A1
`2002/0195656 A1
`2003/0183856 Al
`2007/0045682 A1 *
`
`8/1987 Lu et al .
`3/1990 Sakai
`2/1991 Hutter et al .
`11/1998 Rao et al .
`22000 Choi
`5/2002 Takahashi et al .
`10/2002 Harris
`10/2001 Matsuoka et al .
`12/2002 Hattori
`10/2003 Wieczorek et al .
`3/2007 Hong
`6/2008 Morris et al .
`2/2014 Rahimo
`
`2008/0142899 Al
`2014/0034997 A1 *
`
`2017/0243876 Al
`
`8/2017 Rao
`
`HO1L 27/14689
`257/292
`
`HO1L 29/861
`257/139
`
`FOREIGN PATENT DOCUMENTS
`2003218356 A
`7/2003
`6/2004
`2004049453 Al
`
`JP
`WO
`
`OTHER PUBLICATIONS
`IPR2020-00288_Exhibit 2007 - Minutes for Markman Hearing
`Held via Video Conference Before U.S. District Judge Rodney
`Gilstrap , Greenthread , LLC v . Samsung Electronics Co. , Ltd. , et al . ,
`Case No. 2 : 19 - CV - 147 - JRG .
`IPR2020-00288 — Petitioner Reply .
`IPR2020-00289-00289 Petitioner Reply .
`IPR2020-00292 – Petition for IPR .
`IPR2020-00292 — Exhibit 2002 — Excerpt from Exhibit 4 to Appen
`dix B of Samsung Electronics Co. , Ltd.'s Invalidity Contentions
`( Invalidity Contention based on U.S. Pat . No.6,384,431 to Takahashi .
`
`IPR2020-00288 — Ex . 1020 — Michael Nastasi and James W. Mayer ,
`Ion Implantation and Synthesis of Materials ( 2006 ) . 4 pages .
`IPR2020-00288 – Exhibit 2001 — IPR2020-00288 — Excerpt from
`Exhibit 1 to Appendix A of Samsung Electronics Co. , Ltd.'s
`Invalidity Contentions regarding Morris .
`IPR2020-00288 — Exhibit 2002 — xcerpt from Exhibit 2 to Appen
`dix A of Samsung Electronics Co. , Ltd.'s Invalidity Contentions
`regarding Miyamoto .
`IPR2020-00288 - Exhibit 2009_Complaint for Patent Infringe
`ment , Greenthread , LLC v . Samsung Electronics Co. , Ltd. , at al . ,
`Case No. 2 : 19 - CV - 147 - JRG .
`IPR2020-00288 — Exhibit 2011 – Exhibit A to Revised Joint Claim
`Construction Chart Pursuant to Patent Rule 4-5 , Greenthread , LLC
`v . Samsung Electronics Co. , Ltd. , et al . , Case No. 2 : 19 - CV - 147
`JRG .
`IPR2020-00288 — Exhibit 2012 — Samsungs Responsive Claim Con
`struction Brief - District Court .
`IPR2020-00288 — Exhibit 2013– Glew Dec.
`IPR2020-00288 — Exhibit 2014 — Excerpt from Exhibit 10 to Appen
`dix A of Samsung Electronics Co. , Ltd.'s Invalidity Contentions .
`IPR2020-00288 - Patent Owner Preliminary Response .
`IPR2020-00288 — Patent Owner Sur Reply .
`IPR2020-00288 - Petition .
`IPR2020-00289 - Exhibit 1 to Appendix C of Samsung Electronics
`Co. , Ltd.'s Invalidity Contentions regarding Payne .
`IPR2020-00289 — Exhibit 1003 – Smith Dec.
`IPR2020-00289 — Exhibit 1010 — S . M. Sze et al . , Semiconductor
`Devices : Physics and Technology , John Wiley & Sons , 2nd Ed . ,
`2002 ( “ Sze '02 ” ) .
`IPR2020-00289 — Exhibit 1012 – Ben G. Streetman , Solid State
`Electronic Devices , 2nd Ed . , Prentice - Hall , 1980 ( “ Streetman " ) .
`IPR2020-00289 –Exhibit 2001 – Exhibit 1 to Appendix C of Samsung
`Electronics Co. , Ltd.'s Invalidity Contentions regarding Payne .
`IPR2020-00289 — Exhibit 2002 — Exhibit 3 to Appendix C of Samsung
`Electronics Co. , Ltd.’s Invalidity Contentions regarding Wieczorek .
`IPR2020-00289 — Exhibit 2011 — Behzad Razavi , Design of Analog
`CMOS Integrated Circuits , 2001 ( “ Razavi ” ) .
`IPR2020-00289 — Exhibit 2012 — Excerpts from Wolf , S. , Silicon
`Processing for the VLSI Era , vol . 4 - Deep - Submicron Process
`Technology ( 2002 ) ( “ Wolf vol . 4 ” ) .
`IPR2020-00289 — Exhibit 2013– Glew Dec.
`IPR2020-00289 — Patent Owner Pre Resp .
`IPR2020-00289 — Patent Owner Sur reply .
`IPR2020-00289 — Petition .
`IPR2020-00290 — Exhibit 1003 - Declaration of Dr. Bruce Smith .
`IPR2020-00290 — Exhibit 1013 — Tango , Mega bit Memory Tech
`nology
`IPR2020-00290 — Patent Owner Preliminary Resp .
`IPR2020-00290 — Patent Owner Sur Reply .
`IPR2020-00290 — Petition .
`IPR2020-00290 — Petitioners Reply to Patent Owner Preliminary
`Response .
`1 PR2020-00291 – Exhibit 1003 — Declaration of Dr. Bruce Smith .
`IPR2020-00291 – Exhibit 1011 — The Insulated Gate Bipolar Tran
`sistor : IGBT Theory and Design , Vinod Kumar Khanna , IEEE Press
`and Wiley - Interscience , 2003 .
`IPR2020-00291 — Exhibit 1020_S . M. Sze , Physics of Semicon
`ductor Devices , Wiley - Interscience , 2nd Ed . , 1981 ( “ Sze '81 " ) .
`IPR2020-00291 – Exhibit 1021 — S . M. Sze , Semiconductor Devices :
`Physics and Technology , John Wiley & Sons , 2nd Ed . , 2002 ( “ Sze
`'02 ” ) .
`IPR2020-00291 – Exhibit 2001 – Exhibit 2 to Appendix B of Samsung
`Electronics Co. , LTD'S Invalidity Contentions ( Invalidity Conten
`tion based on U.S. Patent Application Publication No. 2002 /
`0195656 ( “ Hattori ” ) ) .
`IPR2020-00291 – Exhibit 2013 — Declaration of Dr. Alexander D.
`Glew .
`IPR2020-00291 – Patent Owner Preliminary Resp .
`IPR2020-00291 - Patent Owner Sur Reply .
`IPR2020-00291 – Petition .
`IPR2020-00291 – Petitioners Reply .
`IPR2020-00292 — Exhibit 1003 — Declaration of Dr. Bruce Smith .
`
`Greenthread Ex. 2072, p. 2 of 16
`Semiconductor v. Greenthread
`
`

`

`US 11,316,014 B2
`Page 3
`
`( 56 )
`
`References Cited
`OTHER PUBLICATIONS
`IPR2020-00292 — Exhibit 2001 — Excerpt from Exhibit 1 to Appen
`dix B of Samsung Electronics Co. , Ltd.'s Invalidity Contentions
`( Invalidity Contention based on “ Insulated Gate Bipolar Transistor
`IGBT Theory and Design ” by Vinod Kumar Khanna .
`IPR2020-00292 — Exhibit 2012 — Excerpt from Exhibit A to Joint
`Claim Construction Chart Pursuant to Patent Rule 4-5 , Greenthread ,
`LLC v . Samsung Electronics Co. , Ltd. , et al . , Case No. 2 : 19 - CV
`147 - JRG , ( Mar. 18 , 2020 ) .
`IPR2020-00292 — Patent Owner Preliminary Response .
`* cited by examiner
`
`Greenthread Ex. 2072, p. 3 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 1 of 10
`
`US 11,316,014 B2
`
`
`
`Cmething ( per
`
`
`
`
`
`Dopant Concentration
`
`Collector
`
`B
`
`3
`
`3
`3
`7
`$
`?
`
`3
`
`Emitter
`
`$
`
`7
`4
`
`5
`?
`
`$
`
`$
`
`7
`
`BASE
`
`Distance
`
`
`
`Figure 1 Prior Art
`
`
`
`Crayon ( Dopant Concentration per
`
`
`
`
`
`
`
`Greenthread Ex. 2072, p. 4 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 2 of 10
`
`US 11,316,014 B2
`
`q Collector
`
`N + Pt
`
`FIGURE 2 Prior art
`
`
`
`
`
`n epitaxial drift region
`
`NH
`
`..................
`
`NÝ
`
`Ennitter
`
`Greenthread Ex. 2072, p. 5 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 3 of 10
`
`US 11,316,014 B2 |
`
`4 & $
`
`1
`
`
`
`Active devices
`
`1
`
`}
`
`}
`
`P well
`Innnnnn
`
`n well
`
`AMA
`
`P well
`
`m
`
`W P
`
`FIGURE 3A Prior art
`
`Greenthread Ex. 2072, p. 6 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 4 of 10
`
`US 11,316,014 B2
`
`Tumel Insulator
`
`n layer ,
`
`
`
`Storage gate
`
`Access Transistor
`
`www
`P
`
`Prior art
`
`FIGURE 3B
`
`Greenthread Ex. 2072, p. 7 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 5 of 10
`
`|
`US 11,316,014 B2
`
`
`
`Storage capacitor
`
`Access Transistor
`
`P substrate
`
`
`
`FIGURE 3C Prior art
`
`Greenthread Ex. 2072, p. 8 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 6 of 10
`
`US 11,316,014 B2
`
`Control / Select Transistor
`
`Control / Select Transistor
`
`Storage
`
`Storage
`
`Storage
`
`P
`
`FIGURE 3D
`
`Greenthread Ex. 2072, p. 9 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 7 of 10
`
`US 11,316,014 B2
`
`GATE
`
`
`
`SIASTA KOKKU
`
`HA
`
`DOCTRICA
`Voor
`OUTLOOK
`
`Emitter 1
`
`Collector
`
`entend
`
`}
`
`Greenthread Ex. 2072, p. 10 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 8 of 10
`
`US 11,316,014 B2
`
`
`
`P well miwa rain
`
`n well
`
`
`
`Active devices
`
`WWW
`
`P well
`
`w P
`
`NAKARARATILIK
`
`FIGURE SA
`
`Greenthread Ex. 2072, p. 11 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 9 of 10
`
`US 11,316,014 B2
`
`
`Capacitor or Ksensor Storage element
`
`
`
`
`
`Access Transistor
`
`1
`
`1
`
`White
`
`WWW
`
`LUCCI
`P
`
`
`
`
`
`Graded dopant region
`
`FIGURE SB
`
`Greenthread Ex. 2072, p. 12 of 16
`Semiconductor v. Greenthread
`
`

`

`U.S. Patent
`
`Apr. 26 , 2022
`
`Sheet 10 of 10
`
`US 11,316,014 B2
`
`Control / Select Transistor
`
`Storage
`
`Control / Sect Transistor
`
`
`
`
`
`Graded dopant region
`
`P
`
`FIGURE SC
`
`Greenthread Ex. 2072, p. 13 of 16
`Semiconductor v. Greenthread
`
`

`

`US 11,316,014 B2
`
`.
`
`10
`
`a
`
`30
`
`35
`
`1
`SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`
`2
`still use a uniformly doped ‘ drift epitaxial region in the
`base . FIG . 1 shows the relative doping concentration versus
`distance in a BJT . FIG . 2 shows the uniformly doped epi
`region in an IGBT . In contrast to BJTS , MOS devices are
`CROSS - REFERENCE TO RELATED
`5 majority carrier devices for conduction . The conduction is
`APPLICATIONS
`channel dominated . The channel can be a surface in one
`plane in planar devices . The surface can also be on the
`This application is a Continuation of U.S. patent appli
`sidewalls in a vertical device . Other device architectures to
`cation Ser . No. 16 / 947,294 , filed Jul . 27 , 2020 , entitled
`combine planar and vertical conductions are also possible .
`SEMICONDUCTOR DEVICES WITH GRADED DOP The maximum frequency of operation is dictated primarily
`ANT REGIONS , which is a Continuation of U.S. patent
`by source - drain separation distance . Most MOS devices use
`application Ser . No. 16 / 717,950 , filed Dec. 17 , 2019 , entitled
`a uniformly doped substrate ( or a well region ) . When a
`SEMICONDUCTOR DEVICES WITH GRADED DOP MOSFET is optimally integrated with a BJT in a monolithic
`a
`ANT REGIONS , issued as U.S. Pat . No. 10,734,481 on Aug.
`fashion , an IGBT results . The IGBT inherits the advantages
`4 , 2020. U.S. patent application Ser . No. 16 / 717,950 is a
`of both MOSFET and BJT . It also brings new challenges
`Continuation of U.S. patent application Ser . No. 15 / 590,282 , 15 because the required characteristics ( electron transit and
`filed May 9 , 2017 , entitled SEMICONDUCTOR DEVICES
`hole recombination as fast as possible in n - channel IGBT )
`WITH GRADED DOPANT REGIONS , issued as U.S. Pat .
`necessitate different dopant gradients either in the same
`No. 10,510,842 on Dec. 17 , 2019 , which is a Continuation
`layer at different positions , or at the interfaces of similar or
`dissimilar layers .
`of U.S. patent application Ser . No. 14 / 931,636 , filed Nov. 3 ,
`2015 ,
`entitled SEMICONDUCTOR DEVICES WITH 20
`Retrograde wells have been attempted , with little success ,
`to help improve soft error immunity in SRAMs and visual
`GRADED DOPANT REGIONS , issued as U.S. Pat . No.
`quality in imaging circuits . FIG . 3A shows a typical CMOS
`9,647,070 on May 9 , 2017 , which is Continuation of U.S.
`VLSI device employing a twin well substrate , on which
`patent application Ser . No. 14 / 515,584 , filed Oct. 16 , 2014 ,
`active devices are subsequently fabricated . FIGS . 3B , 3C ,
`entitled SEMICONDUCTOR DEVICES WITH GRADED
`DOPANT REGIONS , issued as U.S. Pat . No. 9,190,502 on 25 and 3D illustrate device cross sections , as practiced today .
`Retrograde and halo wells have also been attempted to
`Nov. 17 , 2015 , which is a Continuation of U.S. patent
`improve refresh time in DRAMs ( dynamic random - access
`application Ser . No. 13 / 854,319 filed April 1 , 2013 , entitled
`memories ) , as well as , reducing dark current ( background
`SEMICONDUCTOR DEVICES WITH GRADED DOP noise ) and enhance RGB ( Red , Green , Blue ) color resolution
`ANT REGIONS , which is a Continuation of Ser . No.
`in digital camera ICs . Most of these techniques either divert
`11 / 622,496 , filed Jan. 12 , 2007 , entitled SEMICONDUC the minority carriers away from the active regions of critical
`TOR DEVICES WITH GRADED DOPANT REGIONS ,
`charge storage nodes at the surface , or , increase minority
`issued as U.S. Pat . No. 8,421,195 on Apr. 16 , 2013 , which
`carrier density locally as the particular application requires .
`is a Divisional of U.S. patent application Ser . No. 10/934 ,
`BRIEF DESCRIPTION OF THE DRAWINGS
`915 , filed Sep. 3 , 2004. The disclosures of which are
`incorporated herein by reference in their entirety .
`For a more complete understanding of the present inven
`tion , and the advantages thereof , reference is now made to
`TECHNICAL FIELD
`the following descriptions taken in conjunction with the
`accompanying drawings , in which :
`This present invention relates to all semiconductor
`FIG . 1 illustrates the relative doping profiles of emitter ,
`devices and systems . Particularly it applies to diffused 40
`base and collector for the two most popular bipolar junction
`diodes , avalanche diodes , Schottky devices , power MOS
`transistors : namely , uniform base ( “ A ” ) and graded base
`transistors , JFET's , RF bipolar transistors , IGBTs ( Insulated
`( " B " ) ;
`Gate Bipolar Transistors ) , varactors , digital VLSI , mixed
`FIG . 2 illustrates the cross section of a commercial IGBT
`signal circuits and sensor devices including camera ICs
`with a uniform epitaxial drift region ( base ) ;
`employing CCD ( Charge Coupled Device ) as well as CMOS 45
`FIGS . 3A , 3B , 3C , and 3D illustrate cross sections of
`technologies .
`commonly used prior art CMOS silicon substrates ; FIG . 3A
`showing a typical prior art IC with two wells ( one nº well
`BACKGROUND
`in which p - channel transistors are subsequently fabricated
`and one p well in which n - channel transistors are subse
`Bipolar Junction Transistors ( BJT ) are classified as minor- 50 quently fabricated ) ; FIG . 3B showing a prior art EEPROM
`ity carrier devices because minority carriers are the principle
`( Electronically
`Erasable
`Programmable
`Read - Only
`device conduction mechanism . However , majority carriers
`Memory ) memory cell having a tunnel insulator ; FIG . 30
`also play a small but finite role in modulating the conduc-
`showing a prior art DRAM memory cell ; and FIG . 3D
`tivity in BJTs . Consequently , both carriers ( electrons and
`showing a prior art NAND flash memory cell ;
`holes ) play a role in the switching performance of BJTs . The 55
`FIG . 4 illustrates the cross section of an IGBT , using one
`maximum frequency of operation in BJTs is limited by the
`embodiment of the invention described here , where the
`base transit time as well as the quick recombination of the
`dopant is optimally graded in the epitaxial drift region ; and
`majority carriers when the device is switched off ( prior to
`FIGS . 5A , 5B , and 5C illustrate the cross sections of a
`beginning the next cycle ) . The dominant carrier mechanism
`CMOS silicon substrate with two wells and an underlying
`in BJTs is carrier diffusion . The carrier drift current com- 60 layer using embodiments of the invention to improve per
`ponent is fairly small , especially in uniformly doped base
`formance in each application — VLSI logic , DRAM / image
`BJTs . Efforts have been made in graded base transistors to
`nonvolatile memory IC .
`IC ,
`create an aiding drift field to enhance the diffusing minority
`carrier's speed from emitter to collector . However , most
`DETAILED DESCRIPTION
`semiconductor devices , including various power MOSFETs 65
`( traditional , DMOS , lateral , vertical and a host of other
`The relative doping concentrations of emitter and collec
`configurations ) , IGBT's ( Insulated Gated Base Transistors ) ,
`tor regions varies from 1018 to 102 ° / cm " , whereas the base
`
`Greenthread Ex. 2072, p. 14 of 16
`Semiconductor v. Greenthread
`
`

`

`US 11,316,014 B2
`
`3
`4
`possible . In a preferred embodiment , the subterranean n
`region is 1014 to 1016 / cm² depending on the desired char-
`layer has a graded donor concentration to sweep the minor
`acteristics of the BJT . In graded base p - n - p transistors , the
`ity carriers deep into the substrate . One or more of such
`donor dopant concentration may be 10 to 100x at the
`layers can also be implemented through wafer to wafer
`emitter - base junction , relative to the base - collector junction
`( 1x ) . The gradient can be linear , quasi linear , exponential or 5 bonding or similar “ transfer ” mechanisms . This n layer can
`complimentary error function . The relative slope of the
`be a deeply - implanted layer . It can also be an epitaxial layer .
`donor concentration throughout the base creates a suitable
`As desired , the n- well and p - wells can also be graded or
`aiding drift electric field , to help the holes ( p - n - p transistor )
`retrograded in dopants to sweep those carriers away from the
`transverse from emitter to collector . Since the aiding drift
`surface as well . The graded dopant can also be implemented
`electric field helps hole conduction , the current gain at a 10 in surface channel MOS devices to accelerate majority
`given frequency is enhanced , relative to a uniformly - doped
`carriers towards the drain . To decrease programming time in
`( base ) BJT . The improvement in cut - off frequency ( or ,
`nonvolatile memory devices , carriers should be accelerated
`frequency at unity gain , fr ) can be as large as 2x - 5x . Similar
`towards the surface when programming of memory cells is
`performance improvements are also applicable to n - p - n
`executed . The graded dopant can also be used to fabricate
`15 superior Junction Field - Effect transistors where the " channel
`transistors .
`As illustrated in FIG . 4 , in one embodiment according to
`pinch - off ” is controlled by a graded channel instead of a
`uniformly doped channel ( as practiced in the prior art ) .
`the invention , a donor gradient is established from the
`emitter - drift epitaxial base region junction of the punch-
`One of ordinary skill and familiarity in the art will
`through IGBT , to the drift epitaxial base region- -nt buffer
`recognize that the concepts taught herein can be customized
`layer boundary ( electrons in this case are accelerated in their 20 and tailored to a particular application in many advanta
`transit from emitter to collector ) . The “ average ” base resis-
`geous ways . For instance , minority carriers can be channeled
`tance is optimized so that conductivity modulation and
`to the surface to aid programming in nonvolatile memory
`lifetime ( for minority carriers ) in the base region are not
`devices ( NOR , NAND , multivalued - cell ) . Moreover , single
`compromised . By sweeping the carriers towards the nt
`well , and triple - well CMOS fabrication techniques can also
`buffer region a number of advantages are obtained . First , the 25 be optimized to incorporate these embodiments individually
`frequency of operation ( combination of ton and toff as is
`and collectively . Any modifications of such embodiments
`known in the IGBT commercial nomenclature ) can be
`( described here ) fall within the spirit and scope of the
`enhanced . Second , and maybe more importantly , during topy
`invention . Hence , they fall within the scope of the claims
`holes can be recombined much quicker at the n + buffer layer ,
`described below .
`compared to the uniformly doped n epitaxial drift region by 30
`Although the invention has been described with reference
`establishing a different dopant gradient near the nt buffer
`to specific embodiments , these descriptions are not meant to
`layer . It should be noted that the drift region can also be a
`be construed in a limiting sense . Various modifications of the
`non - epitaxial silicon substrate . Although epitaxy enhances
`disclosed embo ments , as well as alternative embodiments
`lifetime , it is not mandatory . Different layers of dopant
`of the invention will become apparent to persons skilled in
`regions can be transferred through wafer to wafer bonding 35 the art upon reference to the description of the invention . It
`( or other similar transfer mechanisms ) for eventual device
`should be appreciated by those skilled in the art that the
`fabrication . The " reverse recovery time ” for an IGBT is
`conception and the specific embodiment disclosed may be
`significantly improved due to the optimized graded dopant
`readily utilized as a basis for modifying or designing other
`in the so called " drift region ” as well as at the interfaces of
`structures for carrying out the same purposes of the present
`the drift region . Graded dopants can also be implemented in 40 invention . It should also be realized by those skilled in the
`the nt buffer layer as well as other regions adjacent to the
`art that such equivalent constructions do not depart from the
`respective layers . Two important performance enhance-
`spirit and scope of the invention as set forth in the appended
`ments are the result of dopant gradients . For example , in an
`claims .
`n - channel IGBT , electrons can be swept from source to drain
`It is therefore , contemplated that the claims will cover any
`rapidly , while at the same time holes can be recombined 45 such modifications or embodiments that fall within the true
`closer to the nt buffer layer . This can improve ton and toffin
`scope of the invention .
`the same device .
`As illustrated in FIGS . 5A , 5B , and 5C , donor gradient is
`What is claimed is :
`also of benefit to very large scale integrated circuits
`1. An electronic system , the system comprising :
`( VLSI ) —VLSI logic , DRAM , nonvolatile memory like 50
`at least one semiconductor device , the at least one semi
`NAND flash . Spurious minority carriers can be generated by
`conductor device including :
`clock switching in digital VLSI logic and memory ICs .
`a substrate of a first doping type at a first doping level
`These unwanted carriers can discharge dynamically - held
`having a surface ;
`“ actively held high ” nodes . In most cases , statically - held
`a first active region disposed adjacent the surface with
`nodes ( with Vcc ) cannot be affected . Degradation of refresh 55
`a second doping type opposite in conductivity to the
`first doping type and within which transistors can be
`time in DRAMs is one of the results , because the capacitor
`holds charge dynamically . Similarly , degradation of CMOS
`formed ;
`digital images in digital imaging ICs is another result of the
`a second active region separate from the first active
`region disposed adjacent to the first active region and
`havoc caused by minority carriers . Pixel and color resolution
`can be significantly enhanced in imaging ICs with the 60
`within which transistors can be formed ;
`embodiments described herein . Creating “ subterranean ”
`transistors formed in at least one of the first active
`region or second active region ;
`recombination centers underneath the wells ( gold doping ,
`platinum doping ) as is done in some high - voltage diodes is
`at least a portion of at least one of the first and second
`active regions having at least one graded dopant
`not practical for VLSI circuits . Hence , a novel technique is
`described herein which creates a drift field to sweep these 65
`concentration to aid carrier movement from the first
`unwanted minority carriers from the active circuitry at the
`and second active regions towards an area of the
`surface into the substrate in a monolithic die as quickly as
`substrate where there are no active regions ; and
`
`a
`
`Greenthread Ex. 2072, p. 15 of 16
`Semiconductor v. Greenthread
`
`

`

`US 11,316,014 B2
`
`5
`
`5
`6
`20. The system of claim 1 , wherein each of the first and
`at least one well region adjacent to the first or second
`second active regions of the at least one semiconductor
`active region containing at least one graded dopant
`device are in the lateral or vertical direction .
`region , the graded dopant region to aid carrier move-
`21. An electronic system , comprising :
`ment from the surface towards the area of the sub-
`at least one semiconductor device , the at least one semi
`strate where there are no active regions , wherein at
`conductor device including :
`least some of the transistors form digital logic of the
`semiconductor device .
`a substrate of a first doping type at a first doping level
`2. The system of claim 1 , wherein the substrate of the at
`having a surface ;
`least one semiconductor device is a p - type substrate .
`a first active region disposed adjacent the surface of the
`3. The system of claim 1 , wherein the substrate of the at 10
`substrate with a second doping type opposite in
`least one semiconductor device has epitaxial silicon on top
`conductivity to the first doping type and within
`of a nonepitaxial substrate .
`which transistors can be formed in the surface
`4. The system of claim 1 , wherein the first active region
`thereof ;
`and second active region of the at least one semiconductor
`a second active region separate from the first active
`device contain digital logic formed by one of either p - chan- 15
`region disposed adjacent to the first active region and
`nel and n - channel devices .
`within which transistors can be formed in the surface
`5. The system of claim 1 , wherein the first active region
`thereof ;
`and second active region of the at least one semiconductor
`transistors formed in at least one of the first active
`device contain either p - channel or n - channel devices in
`region or second active region ;
`n - wells or p - wells , respectively , and each well has at least 20
`at least a portion of at least one of the first and second
`one graded dopant .
`active regions having at least one graded dopant
`6. The system of claim 1 , wherein the first active region
`concentration to aid carrier movement from the
`and second active region of the at least one semiconductor
`surface to an area of the substrate where there are no
`device are each separated by at least one isolation region .
`active regions ; and
`7. The system of claim 1 , wherein the graded dopant is 25
`at least one well region adjacent to the first or second
`fabricated with an ion implantation process .
`active region containing at least one graded dopant
`8. The system of claim 1 , wherein the first and second
`region , the graded dopant region to aid carrier move
`active regions of the at least one semiconductor device are
`ment from the surface to the area of the substrate
`formed adjacent the first surface of the substrate of the at
`where there are no active regions , and wherein the
`least one semiconductor device .
`graded dopant concentration is linear , quasilinear ,
`9. The system of claim 1 , wherein dopants of the graded
`error function , complementary error function , or any
`dopant concentration in the first active region or the second
`combination thereof .
`active region of the at least one semiconductor device are
`22. The system of claim 21 , wherein the substrate of the
`either p - type or n - type .
`10. The system of claim 1 , wherein dopants of the graded 35 at least one semiconductor device is an n - type substrate .
`23. The system of claim 21 , wherein the substrate of the
`dopant concentration in the first active region of the at least
`at least one semiconductor device is a p - type substrate .
`one semiconductor device are both p - type and n - type .
`24. The system of claim 21 , wherein the substrate of the
`11. The system of claim 1 , wherein dopants of the graded
`at least one semiconductor device has epitaxial silicon on
`dopant concentration in the second active region of the at
`least one semiconductor device are both p - type and n - type . 40 top of a nonepitaxial substrate .
`25. The system of claim 21 , wherein the first active region
`12. The system of claim 1 , wherein dopants of the graded
`and second active region of the at least one semiconductor
`dopant region in the well region of the at least one semi
`device contain at least one of either p - channel and n - channel
`conductor device are both p - type and n - type .
`devices .
`13. The system of claim 1 , wherein the transistors which
`26. The system of claim 21 , wherein the first active region
`can be formed in the first and second active regions of the 45
`and second active region of the at least one semiconductor
`at least one semiconductor device are CMOS digital logic
`device contain either p - channel or n - channel devices in
`transistors requiring at least a source , a drain , a gate and a
`n - wells or p - wells , respectively , and each well has at least
`channel .
`one graded dopant .
`14. The system of claim 1 , wherein the at least one
`27. The system of claim 21 , wherein the first active region
`semiconductor device is a dynamic random access memory 50
`and second active region of the at least one semiconductor
`( DRAM ) .
`device are each separated by at least one isolation region .
`15. The system of claim 1 , wherein the at least one
`28. The system of claim 21 , wherein dopants of the graded
`semiconductor device is a complementary metal oxide semi
`dopant concentration in the first active region or the second
`conductor ( CMOS ) with a nonepitaxial substrate .
`16. The system of claim 1 , wherein the at least one 55 active region of the at