( 12 ) United States Patent
`Rao
`
`( 10 ) Patent No .: US 10,734,481 B2
`Aug. 4 , 2020
`( 45 ) Date of Patent :
`
`US010734481B2
`
`( 54 ) SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`( 71 ) Applicant : GREENTHREAD , LLC , Dallas , TX
`( US )
`( 72 ) Inventor : G. R. Mohan Rao , Allen , TX ( US )
`( 73 ) Assignee : Greenthread , LLC , Dallas , TX ( US )
`Subject to any disclaimer , the term of this
`( * ) Notice :
`patent is extended or adjusted under 35
`U.S.C. 154 ( b ) by 0 days .
`( 21 ) Appl . No .: 16 / 717,950
`( 22 ) Filed :
`Dec. 17 , 2019
`( 65 )
`
`Prior Publication Data
`US 2020/0127095 A1 Apr. 23 , 2020
`Related U.S. Application Data
`Continuation of application No. 15 / 590,282 , filed on
`May 9 , 2017 , now Pat . No. 10,510,842 , which is a
`continuation of application No. 14 / 931,636 , filed on
`Nov. 3 , 2015 , now Pat . No. 9,647,070 , which is a
`continuation of application No. 14 / 515,584 , filed on
`( Continued )
`
`Int . Cl .
`( 2006.01 )
`HOIL 29/06
`( 2006.01 )
`HOIL 29/10
`HOIL 29/36
`( 2006.01 )
`( 2006.01 )
`HOIL 29/739
`( 2006.01 )
`HOIL 27/146
`( 2017.01 )
`HOIL 27/11524
`( 2017.01 )
`HOIL 27/11521
`( 2006.01 )
`HOIL 27/02
`( 2006.01 )
`HOIL 27/108
`U.S. CI .
`CPC ... HOIL 29/1095 ( 2013.01 ) ; HOIL 27/11521
`( 2013.01 ) ; HOIL 27/11524 ( 2013.01 ) ; HOIL
`27/14643 ( 2013.01 ) ; HOIL 29/36 ( 2013.01 ) ;
`
`( 60 )
`
`( 51 )
`
`( 52 )
`
`( 58 )
`
`( 56 )
`
`HOIL 29/7395 ( 2013.01 ) ; HOIL 27/0214
`( 2013.01 ) ; HOIL 27/10844 ( 2013.01 )
`Field of Classification Search
`HO1L 29/1095
`CPC
`257/25
`USPC
`See application file for complete search history .
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,001,864 A
`4,160,985 A
`
`1/1977 Gibbons
`7/1979 Kamins et al .
`( Continued )
`
`OTHER PUBLICATIONS
`P.D. Moor , Advanced CMOS - based pixel sensors , https : // indico .
`cem.ch/event/122027/contributions/88236/attachments/69340/99377/
`FEEimecPdM.pdf , 2011 , 41 pages .
`( Continued )
`
`Primary Examiner — Ajay Arora
`( 74 ) Attorney , Agent , or Firm — Bill R. Naifeh
`
`ABSTRACT
`( 57 )
`Most semiconductor devices manufactured today , have uni
`form dopant concentration , either in the lateral or vertical
`device active ( and isolation ) regions . By grading the dopant
`concentration , the performance in various semiconductor
`devices
`be significantly improved . Performance
`can
`improvements can be obtained in application specific areas
`like increase in frequency of operation for digital logic ,
`various power MOSFET and IGBT ICs , improvement in
`refresh time for DRAMs , decrease in programming time for
`nonvolatile memory , better visual quality including pixel
`resolution and color sensitivity for imaging ICs , better
`sensitivity for varactors in tunable filters , higher drive capa
`bilities for JFETs , and a host of other applications .
`
`36 Claims , 10 Drawing Sheets
`
`Access ' taisistor
`
`nt
`
`Storage Capacitor or
`sensor element
`
`#
`
`Gradet depan run 16 puli muturity camius Gor sofoco
`
`P substrate
`
`CMOS Substrate for a DRAM ar inzage sensor , with noe embodiment of the invention
`
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`

`US 10,734,481 B2
`Page 2
`
`Related U.S. Application Data
`Oct. 16 , 2014 , now Pat . No. 9,190,502 , which is a
`continuation of application No. 13 / 854,319 , filed on
`Apr. 1 , 2013 , now abandoned , which is a continuation
`of application No. 11 / 622,496 , filed on Jan. 12 , 2007 ,
`now Pat . No. 8,421,195 , which is a division of
`application No. 10 / 934,915 , filed on Sep. 3 , 2004 ,
`now abandoned .
`
`( 56 )
`
`References Cited
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`
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`2001/0040622 Al
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`
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`
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`
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`257/292
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`
`HO1L 29/0821
`330/57
`
`OTHER PUBLICATIONS
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`Z. Cao , Design of Pixel for High Speed CMOS Image Sensors ,
`http://www.imagesensors.org/Past%20Workshops/2013%20Workshop/
`2013 % 20Papers / 07-11_072 - Cao_papers.pdf , 4 pages .
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`IEEE Transactions on Electron Devices , vol . Ed - 14 , No. 2 , Feb.
`1967 .
`Berinder Brar et al . , Herb's Bipolar Transistors , IEEE Transactions
`on Electron Devices , vol . 48 , No. 11 , Nov. 2001 .
`* cited by examiner
`
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`U.S. Patent
`
`Aug. 4 , 2020
`
`Sheet 1 of 10
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`US 10,734,481 B2
`
`
`
`Cm ( per
`
`
`
`
`
`Color ( per
`
`
`
`
`
`Dopant Concentration
`
`Collector
`
`wt
`7
`
`$
`
`7
`
`Emitter
`
`E
`
`**
`1
`3
`
`$
`
`1
`
`7
`
`BASE
`
`Distance
`
`
`
`Dopant Concentration
`
`Figure 1 Prior Art
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`U.S. Patent
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`Aug. 4 , 2020
`
`Sheet 2 of 10
`
`US 10,734,481 B2
`
`GATE
`
`Einitter
`
`P
`
`N +
`
`uniform ) .
`
`
`
`
`concentration is n epitaxial drift region ( n - dopant
`
`
`layer Pogle substrate
`N + buffer
`
`Collector
`
`FIGURE 2 Prior art
`
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`

`U.S. Patent
`
`Aug. 4 , 2020
`
`Sheet 3 of 10
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`US 10,734,481 B2
`
`? 1 **
`
`$
`
`$
`
`
`
`Active devices
`
`**
`
`ve
`
`P well
`
`n well
`
`P well
`
`P substrate
`
`
`
`
`
`FIGURE 3A Prior art ( Twin well CMOS ) for a CMOS integrated circuit
`
`
`
`
`
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`U.S. Patent
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`Aug. 4 , 2020
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`Sheet 4 of 10
`
`US 10,734,481 B2
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`Insulator
`
`3 layer ,
`
`
`
`Storage gate ( for program / erase )
`
`Access Transistor
`
`P substrate
`
`
`
`FIGURE 3B Prior art for a two - device EEPROM memory cell
`
`
`
`
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`U.S. Patent
`
`Aug. 4 , 2020
`
`Sheet 5 of 10
`
`US 10,734,481 B2
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`
`
`Storage capacitor
`
`Access Transistor
`
`P substrate
`
`
`
`
`
`FIGURE 3C Prior art for a 1T - 1C DRAM memory cell
`
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`U.S. Patent
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`Aug. 4 , 2020
`
`Sheet 6 of 10
`
`US 10,734,481 B2
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`Control / Select Transistor
`
`N
`
`Storage
`
`Storage
`
`Storage
`
`ControlSelect
`
`Transistor
`
`P substrate
`
`
`
`Prior art for a NAND flash memory cell
`
`
`
`
`
`
`
`Note : Control / Sect transistors have a single insulator - traditional
`
`
`
`
`
`
`
`
`
`
`
`
`
`Storage nodes have a stacked gate structure , typically with a floating gate and control gate comprising the stack .
`
`
`
`
`
`MOS transistor .
`
`FIGURE 3D
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`U.S. Patent
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`Aug. 4 , 2020
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`Sheet 7 of 10
`
`US 10,734,481 B2
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`GATE
`
`Emitter
`
`Po
`
`N +
`
`graded ) .
`
`
`
`
`concentration is n epitaxial drift region ( n - dopant
`
`
`layer Paline substrate
`N + buffer
`
`Collector
`
`
`
`FIGURE 4 A dopant - concentration grinded drift region in a IGBT
`
`
`
`
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`U.S. Patent
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`Aug. 4 , 2020
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`Sheet 8 of 10
`
`US 10,734,481 B2
`
`P well
`YA
`
`
`
`Active devices
`
`ovel
`
`
`
`Graded dopant n layer
`
`n well
`
`P well
`
`P substrate
`
`
`
`
`
`FIGURE SA A CMOS Substrate for digital , mixed , signal , and senors IC's
`
`
`
`
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`U.S. Patent
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`Aug. 4 , 2020
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`Sheet 9 of 10
`
`US 10,734,481 B2
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`
`
`
`
`elenient Storage Capacitor or sensor
`
`AccessTransistor
`
`P substrate
`
`
`
`
`
`FIGURE SB CMOS Substrate for a DRAM or image sensor , with one embodiment of the invention
`
`
`
`
`
`
`
`
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`
`
`Graded dopant region to pull minority carriers from surface
`
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`U.S. Patent
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`Aug. 4 , 2020
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`Sheet 10 of 10
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`US 10,734,481 B2
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`Control / Select Transistor
`
`Storage
`
`Control / Sect Transistor
`
`
`Graded dopant
`
`
`
`
`
`
`
`
`
`
`region Accelerates carriers towards surface during programining
`
`P substrate
`
`
`
`
`
`FIGURE SC CMOS Substrate for a NAND flash device to improve programming times
`
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`US 10,734,481 B2
`
`1
`SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`
`2
`region in an IGBT . In contrast to BJTS , MOS devices are
`majority carrier devices for conduction . The conduction is
`channel dominated . The channel can be a surface in one
`plane in planar devices . The surface can also be on the
`CROSS - REFERENCE TO RELATED
`5 sidewalls in a vertical device . Other device architectures to
`APPLICATIONS
`combine planar and vertical conductions are also possible .
`The maximum frequency of operation is dictated primarily
`This application is a Continuation of U.S. patent appli
`by source - drain separation distance . Most MOS devices use
`cation Ser . No. 15 / 590,282 , filed May 9 , 2017 , published on
`a uniformly doped substrate ( or a well region ) . When a
`Aug. 24 , 2017 , as U.S. Publication No. 2017-0243876 .
`application Ser . No. 15 / 590,282 is a continuation of U.S. 10 MOSFET is optimally integrated with a BJT in a monolithic
`patent application Ser . No. 14 / 931,636 , filed Nov. 3 , 2015 ,
`fashion , an IGBT results . The IGBT inherits the advantages
`published on Jun . 16 , 2016 as U.S. Publication No. 2016
`of both MOSFET and BJT . It also brings new challenges
`0172447 , now U.S. Pat . No. 9,647,070 , issued on May 9 ,
`because the required characteristics ( electron transit and
`2017. Application Ser . No. 14 / 931,636 is a continuation of
`hole recombination as fast as possible in n - channel IGBT )
`U.S. patent application Ser . No. 14 / 515,584 , filed Oct. 16 , 15 necessitate different dopant gradients either in the same
`2014 , published on Feb. 5 , 2015 , as U.S. Publication No.
`layer at different positions , or at the interfaces of similar or
`2015-0035004 , now U.S. Pat . No. 9,190,502 , issued on Nov.
`dissimilar layers .
`17 , 2015. Application Ser . No. 14 / 515,584 is a Continuation
`Retrograde wells have been attempted , with little success ,
`of U.S. patent application Ser . No. 13 / 854,319 filed Apr. 1 ,
`to help improve soft error immunity in SRAMs and visual
`2013 , published on Aug. 29 , 2013 , as U.S. Publication No. 20 quality in imaging circuits . FIG . 3A shows a typical CMOS
`2013-0221488 . Application Ser . No. 13 / 854,319 is a Con
`VLSI device employing a twin well substrate , on which
`tinuation of Ser . No. 11 / 622,496 , filed Jan. 12 , 2007 , pub
`active devices are subsequently fabricated . FIGS . 3B , 3C ,
`lished on Jul . 12 , 2007 , as Publication No. 2007-0158790 ,
`and 3D illustrate device cross sections , as practiced today .
`now U.S. Pat . No. 8,421,195 , issued on Apr. 16 , 2013 .
`Retrograde and halo wells have also been attempted to
`Application Ser . No. 11 / 622,496 , is a Division of U.S. patent 25 improve refresh time in DRAMs ( dynamic random - access
`application Ser . No. 10 / 934,915 , filed Sep. 3 , 2004 , pub
`memories ) , as well as , reducing dark current ( background
`lished on Mar. 9 , 2006 , as U.S. Publication No. 2006
`noise ) and enhance RGB ( Red , Green , Blue ) color resolution
`0049464. U.S. Pat . Nos . 9,647,070 , 9,190,502 , and 8,421 ,
`in digital camera ICs . Most of these techniques either divert
`195 , and Patent Application Publication Nos . 2017
`the minority carriers away from the active regions of critical
`0243876 , 2016-0172447 , 2015-0035004 , 2013-0221488 , 30 charge storage nodes at the surface , or , increase minority
`2007-0158790 , and 2006-0049464 , are incorporated herein
`carrier density locally as the particular application requires .
`by reference in their entirety .
`BRIEF DESCRIPTION OF THE DRAWINGS
`TECHNICAL FIELD
`For a more complete understanding of the present inven
`tion , and the advantages thereof , reference is now made to
`This present invention relates to all semiconductor
`the following descriptions taken in conjunction with the
`devices and systems . Particularly it applies to diffused
`diodes , avalanche diodes , Schottky devices , power MOS accompanying drawings , in which :
`transistors , JFET's , RF bipolar transistors , IGBTs ( Insulated
`FIG . 1 illustrates the relative doping profiles of emitter ,
`Gate Bipolar Transistors ) , varactors , digital VLSI , mixed 40 base and collector for the two most popular bipolar junction
`signal circuits and sensor devices including camera ICs
`transistors : namely , uniform base ( “ A ” ) and graded base
`employing CCD ( Charge Coupled Device ) as well as CMOS ( " B " ) ;
`technologies .
`FIG . 2 illustrates the cross section of a commercial IGBT
`with a uniform epitaxial drift region ( base ) ;
`BACKGROUND
`FIGS . 3A , 3B , 3C , and 3D illustrate cross sections of
`commonly used prior art CMOS silicon substrates ; FIG . 3A
`showing a typical prior art IC with two wells ( one n well
`Bipolar Junction Transistors ( BJT ) are classified as minor
`in which p - channel transistors are subsequently fabricated
`ity carrier devices because minority carriers are the principle
`and one p well in which n - channel transistors are subse
`device conduction mechanism . However , majority carriers
`also play a small but finite role in modulating the conduc- 50 quently fabricated ) ; FIG . 3B showing a prior art EEPROM
`tivity in BJTs . Consequently , both carriers ( electrons and
`( Electronically
`Erasable
`Programmable Read - Only
`holes ) play a role in the switching performance of BJTs . The
`Memory ) memory cell having a tunnel insulator ; FIG . 3C
`maximum frequency of operation in BJTs is limited by the
`showing a prior art DRAM memory cell ; and FIG . 3D
`base transit time as well as the quick recombination of the
`showing a prior art NAND flash memory cell ;
`majority carriers when the device is switched off ( prior to 55
`FIG . 4 illustrates the cross section of an IGBT , using one
`beginning the next cycle ) . The dominant carrier mechanism
`embodiment of the invention described here , where the
`in BJTs is carrier diffusion . The carrier drift current com
`dopant is optimally graded in the epitaxial drift region ; and
`ponent is fairly small , especially in uniformly doped base
`FIGS . 5A , 5B , and 5C illustrate the cross sections of a
`BJTs . Efforts have been made in graded base transistors to
`CMOS silicon substrate with two wells and an underlying
`create an aiding drift field to enhance the diffusing minority 60 layer using embodiments of the invention to improve per
`carrier's speed from emitter to collector . However , most
`formance in each application — VLSI logic , DRAM / image
`semiconductor devices , including various power MOSFETs
`nonvolatile memory IC .
`IC ,
`( traditional , DMOS , lateral , vertical and a host of other
`configurations ) , IGBT's ( Insulated Gated Base Transistors ) ,
`DETAILED DESCRIPTION
`still use a uniformly doped ' drift epitaxial region in the 65
`base . FIG . 1 shows the relative doping concentration versus
`The relative doping concentrations of emitter and collec
`distance in a BJT . FIG . 2 shows the uniformly doped epi
`tor regions varies from 1018 to 102 ° / cm " , whereas the base
`
`35
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`5
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`US 10,734,481 B2
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`3
`4
`possible . In a preferred embodiment , the subterranean n
`region is 1014 to 1016 / cm3 depending on the desired char
`layer has a graded donor concentration to sweep the minor
`acteristics of the BJT . In graded base p - n - p transistors , the
`ity carriers deep into the substrate . One or more of such
`donor dopant concentration may be 10 to 100x at the
`layers can also be implemented through wafer to wafer
`emitter - base junction , relative to the base - collector junction
`bonding or similar “ transfer ” mechanisms . This n - layer can
`( 1x ) . The gradient can be linear , quasi linear , exponential or
`complimentary error function . The relative slope of the
`be a deeply - implanted layer . It can also be an epitaxial layer .
`donor concentration throughout the base creates a suitable
`As desired , the n` well and p - wells can also be graded or
`aiding drift electric field , to help the holes ( p - n - p transistor )
`retrograded in dopants to sweep those carriers away from the
`transverse from emitter to collector . Since the aiding drift
`surface as well . The graded dopant can also be implemented
`electric field helps hole conduction , the current gain at a 10 in surface channel MOS devices to accelerate majority
`given frequency is enhanced , relative to a uniformly - doped
`carriers towards the drain . To decrease programming time in
`( base ) BJT . The improvement in cut - off frequency ( or ,
`nonvolatile memory devices , carriers should be accelerated
`frequency at unity gain , fr ) can be as large as 2x - 5x . Similar
`towards the surface when programming of memory cells is
`performance improvements are also applicable to n - p - n
`executed . The graded dopant can also be used to fabricate
`transistors .
`superior Junction Field - Effect transistors where the “ channel
`As illustrated in FIG . 4 , in one embodiment according to
`the invention , a donor gradient is established from the
`pinch - off ” is controlled by a graded channel instead of a
`uniformly doped channel ( as practiced in the prior art ) .
`emitter - drift epitaxial base region junction of the punch
`through IGBT , to the drift epitaxial base region -nt buffer
`One of ordinary skill and familiarity in the art will
`layer boundary ( electrons in this case are accelerated in their 20 recognize that the concepts taught herein can be customized
`transit from emitter to collector ) . The “ average ” base resis
`and tailored to a particular application in many advanta
`tance is optimized so that conductivity modulation and
`geous ways . For instance , minority carriers can be channeled
`lifetime ( for minority carriers ) in the base region are not
`to the surface to aid programming in nonvolatile memory
`compromised . By sweeping the carriers towards the nt
`devices ( NOR , NAND , multivalued - cell ) . Moreover , single
`buffer region a number of advantages are obtained . First , the 25 well , and triple - well CMOS fabrication techniques can also
`be optimized to incorporate these embodiments individually
`frequency of operation ( combination of ton and to as is
`known in the IGBT commercial nomenclature ) can be
`and collectively . Any modifications of such embodiments
`( described here ) fall within the spirit and scope of the
`enhanced . Second , and maybe more importantly , during tops
`invention . Hence , they fall within the scope of the claims
`holes can be recombined much quicker at the n + buffer layer ,
`compared to the uniformly doped n epitaxial drift region by 30 described below .
`establishing a different dopant gradient near the nt buffer
`Although the invention has been described with reference
`to specific embodiments , these descriptions are not meant to
`layer . It should be noted that the drift region can also be a
`non - epitaxial silicon substrate . Although epitaxy enhances
`be construed in a limiting sense . Various modifications of the
`disclosed embodiments , as well as alternative embodiments
`lifetime , it is not mandatory . Different layers of dopant
`regions can be transferred through wafer to wafer bonding 35 of the invention will become apparent to persons skilled in
`( or other similar transfer mechanisms ) for eventual device
`the art upon reference to the description of the invention . It
`should be appreciated by those skilled in the art that the
`fabrication . The " reverse recovery time ” for an IGBT is
`significantly improved due to the optimized graded dopant
`conception and the specific embodiment disclosed may be
`in the so called " drift region ” as well as at the interfaces of
`readily utilized as a basis for modifying or designing other
`the drift region . Graded dopants can also be implemented in 40 structures for carrying out the same purposes of the present
`invention . It should also be realized by those skilled in the
`the nt buffer layer as well as other regions adjacent to the
`respective layers . Two important performance enhance
`art that such equivalent constructions do not depart from the
`ments are the result of dopant gradients . For example , in an
`spirit and scope of the invention as set forth in the appended
`claims .
`n - channel IGBT , electrons can be swept from source to drain
`rapidly , while at the same time holes can be recombined 45
`It is therefore , contemplated that the claims will cover any
`such modifications or embodiments that fall within the true
`closer to the nt buffer layer . This can improve ton and toff in
`scope of the invention .
`the same device .
`As illustrated in FIGS . 5A , 5B , and 5C , donor gradient is
`also of benefit to very large scale integrated circuits
`( VLSI ) —VLSI logic , DRAM , nonvolatile memory like 50
`NAND flash . Spurious minority carriers can be generated by
`clock switching in digital VLSI logic and memory ICs .
`These unwanted carriers can discharge dynamically - held
`“ actively held high ” nodes . In most cases , statically - held
`nodes ( with Vce ) cannot be affected . Degradation of refresh 55
`time in DRAMs is one of the results , because the capacitor
`holds charge dynamically . Similarly , degradation of CMOS
`digital images in digital imaging ICs is another result of the
`havoc caused by minority carriers . Pixel and color resolution
`can be significantly enhanced in imaging ICs with the 60
`embodiments described herein . Creating “ subterranean "
`recombination centers underneath the wells ( gold doping ,
`platinum doping ) as is done in some high - voltage diodes is
`not practical for VLSI circuits . Hence , a novel technique is
`described herein which creates a drift field to sweep these 65
`unwanted minority carriers from the active circuitry at the
`surface into the substrate in a monolithic die as quickly as
`
`What is claimed is :
`1. A semiconductor device , comprising :
`a substrate of a first doping type at a first doping level
`having first and second surfaces ;
`a first active region disposed adjacent the first surface of
`the substrate with a second doping type opposite in
`conductivity to the first doping type and within which
`transistors can be formed ;
`a second active region separate from the first active region
`disposed adjacent to the first active region and within
`which transistors can be formed ;
`transistors formed in at least one of the first active region
`or second active region ;
`at least a portion of at least one of the first and second
`active regions having at least one graded dopant con
`centration to aid carrier movement from the first sur
`face to the second surface of the substrate ; and
`at least one well region adjacent to the first or second
`active region containing at least one graded dopant
`
`Greenthread Ex. 2071, p. 14 of 15
`Semiconductor v. Greenthread
`
`

`

`US 10,734,481 B2
`
`5
`
`15
`
`5
`6
`a second active region separate from the first active region
`region , the graded dopant region to aid carrier move
`disposed adjacent to the first active region and within
`ment from the first surface to the second surface of the
`substrate .
`which transistors can be formed in the surface thereof ;
`transistors formed in at least one of the first active region
`2. The semiconductor device of claim
`1 , wherein the
`substrate is a p - type substrate .
`or second active region ;
`3. The semiconductor device of claim
`1 , wherein the
`at least a portion of at least one of the first and second
`substrate has epitaxial silicon on top of a nonepitaxial
`active regions having at least one graded dopant con
`substrate .
`centration to aid carrier movement from the surface to
`4. The semiconductor device of claim 1 , wherein the first
`the substrate ; and
`active region and second active region contain one of either 10
`at least one well region adjacent to the first or second
`p - channel and n - channel devices .
`active region containing at least one graded dopant
`5. The semiconductor device of claim 1 , wherein the first
`region , the graded dopant region to aid carrier move
`active region and second active region contain either p - chan
`ment from the first surface to the second surface of the
`nel or n - channel devices in n - wells or p - wells , respectively ,
`substrate .
`and each well has at least one graded dopant .
`21. The semiconductor device of claim 20 , wherein the
`6. The semiconductor device of claim 1 , wherein the first
`substrate is an n - type substrate .
`active region and second active region are each separated by
`22. The semiconductor device of claim 20 , wherein the
`at least one isolation region .
`substrate is a p - type substrate .
`7. The semiconductor device of claim
`1 , wherein the
`23. The semiconductor device of claim 20 , wherein the
`graded dopant is fabricated with an ion implantation pro- 20 substrate has epitaxial silicon on top of a nonepitaxial
`cess .
`substrate .
`8. The semiconductor device of claim 1 , wherein the first
`24. The semiconductor device of claim 20 , wherein the
`and second active regions are formed adjacent the first
`first active region and second active region contain at least
`surface of the substrate .
`9. The semiconductor device of claim 1 , wherein dopants 25 one of either p - channel and n - channel devices .
`25. The semiconductor device of claim 20 , wherein the
`of the graded dopant concentration in the first active region
`first active region and second active region contain either
`or the second active region are either p - type or n - type .
`p - channel or n - channel devices in n - wells or p - wells , respec
`10. The semiconductor device of claim 1 , wherein dop
`tively , and each well has at least one graded dopant .
`ants of the graded dopant concentration in the first active
`26. The semiconductor device of claim 20 , wherein the
`region are both p - type and n - type .
`first active region and second active region are each sepa
`11. The semiconductor device of claim 1 , wherein dopants
`rated by at least one isolation region .
`of the graded dopant concentration in the second active
`27. The semiconductor device of claim 20 , wherein dop
`region are both p - type and n - type .
`ants of the graded dopant concentration in the first active
`12. The semiconductor device of claim 1 , wherein dop
`ants of the graded dopant region in the well region are both 35 region or the second active region are either p - type or
`n - type .
`p - type and n - type .
`28. The semiconductor device of claim 20 , wherein dop
`13. The semiconductor device of claim 1 , wherein the
`ants of the graded dopant concentration in the first active
`transistors which can be formed in the first and second active
`region are both p - type and n - type .
`regions are CMOS transistors requiring at least a source , a
`29. The semiconductor device of claim 20 , wherein dop
`drain , a gate and a channel .
`ants of the graded dopant concentration in the second active
`14. The semiconductor device of claim
`1 , wherein the
`region are both p - type and n - type .
`device is a dynamic random access memory ( DRAM ) .
`30. The semiconductor device of claim 20 , wherein dop
`15. The semiconductor device of claim
`1 , wherein the
`ants of the graded dopant region in the well region are both
`device is a complementary metal oxide semiconductor
`p - type and n - type .
`( CMOS ) with a nonepitaxial substrate .
`31. The semiconductor device of claim 20 , wherein the
`16. The semiconductor device of claim 1 , wherein the
`graded dopant is fabricated with an ion implantation pro
`device is a flash memory .
`cess .
`17. The semiconductor device of claim 1 , wherein the
`32. The semiconductor device of claim 20 , wherein the
`device is a logic device .
`18. The semiconductor device of claim 17 , wherein the 50 substrate is a complementary metal oxide semiconductor
`( CMOS ) device .
`device is central processing unit .
`33. The semiconductor device of claim 20 , wherein the
`19. The semiconductor device of claim
`1 , wherein the
`device is a flash memory .
`device is an image sensor .
`34. The semiconductor device of claim 20 , wherein the
`20. A semiconductor device , comprising :
`a substrate of a first doping type at a first doping level 55 device is a logic device .
`35. The semiconductor device of claim 34 , wherein the
`having first and second surfaces ;
`device is central processing unit .
`a first active region disposed adjacent the first surface of
`36. The semiconductor device of claim 20 , wherein the
`the substrate with a second doping type opposite in
`device is an image sensor .
`conductivity to the first doping type and within which
`transistors can be formed in the surface thereof ;
`
`45
`
`30
`
`40
`
`Greenthread Ex. 2071, p. 15 of 15
`Semiconductor v. Greenthread
`
`