( 12 ) United States Patent
`Rao
`
`( 10 ) Patent No .: US 10,510,842 B2
`( 45 ) Date of Patent :
`Dec. 17 , 2019
`
`US010510842B2
`
`( * ) Notice :
`
`( 54 ) SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`( 71 ) Applicant : GREENTHREAD , LLC , Dallas , TX
`( US )
`( 72 ) Inventor : G.R. Mohan Rao , Allen , TX ( US )
`( 73 ) Assignee : GREENTHREAD , LLC , Dallas , TX
`( US )
`Subject to any disclaimer , the term of this
`patent is extended or adjusted under 35
`U.S.C. 154 ( b ) by 0 days .
`( 21 ) Appl . No .: 15 / 590,282
`May 9 , 2017
`( 22 )
`Filed :
`( 65 )
`Prior Publication Data
`US 2017/0243876 A1 Aug. 24 , 2017
`Related U.S. Application Data
`Continuation of application No. 14 / 931,636 , filed on
`Nov. 3 , 2015 , now Pat . No. 9,647,070 , which is a
`continuation of application No. 14 / 515,584 , filed on
`Oct. 16 , 2014 , now Pat . No. 9,190,502 , which is a
`continuation of application No. 13 / 854,319 , filed on
`( Continued )
`
`( 60 )
`
`( 51 )
`
`( 52 )
`
`Int . Cl .
`HOIL 21/02
`HOIL 29/10
`HOIL 27/11524
`HOIL 27/146
`HOIL 27/11521
`HOIL 29/739
`HOIL 29/36
`
`( 2006.01 )
`( 2006.01 )
`( 2017.01 )
`( 2006.01 )
`( 2017.01 )
`( 2006.01 )
`( 2006.01 )
`( Continued )
`
`U.S. CI .
`CPC ... HOLL 29/1095 ( 2013.01 ) ; HOIL 27/11521
`( 2013.01 ) ; HOIL 27/11524 ( 2013.01 ) ; HOIL
`27/14643 ( 2013.01 ) ; HOIL 29/36 ( 2013.01 ) ;
`
`( 58 )
`
`( 56 )
`
`HOIL 29/7395 ( 2013.01 ) ; HOIL 27/0214
`( 2013.01 ) ; HOIL 27/10844 ( 2013.01 )
`Field of Classification Search
`HO1L 29/1095
`CPC
`257/655
`USPC
`See application file for complete search history .
`References Cited
`U.S. PATENT DOCUMENTS
`4,001,864 A
`4,160,985 A
`
`1/1977 Gibbons
`7/1979 Kamins et al .
`( Continued )
`
`OTHER PUBLICATIONS
`P.D. Moor , Advanced CMOS - based pixel sensors , https : // indico .
`cem.ch/event/122027/contributions/88236/ attachments / 69340 / 99377 /
`FEEimecPdM.pdf , 2011 , 41 pages .
`( Continued )
`Ajay Arora
`Primary Examiner
`( 74 ) Attorney , Agent , or Firm — Bill R. Naifeh ; Timothy
`F. Bliss
`
`( 57 )
`ABSTRACT
`Most semiconductor devices manufactured today , have uni
`form dopant concentration , either in the lateral or vertical
`device active ( and isolation ) regions . By grading the dopant
`concentration , the performance in various semiconductor
`devices can be significantly improved . Performance
`improvements can be obtained in application specific areas
`like increase in frequency of operation for digital logic ,
`various power MOFSFET and IGBT ICs , improvement in
`refresh time for DRAMs , decrease in programming time for
`nonvolatile memory , better visual quality including pixel
`resolution and color sensitivity for imaging ICs , better
`sensitivity for varactors in tunable filters , higher drive capa
`bilities for JFETs , and a host of other applications .
`18 Claims , 10 Drawing Sheets
`
`Access Transistor
`
`Storage Capacitor or
`Geosor element
`
`: + + til
`
`Oraded dopant region to pull minority camers from surface
`
`P substrate
`
`CMOS Substrate for a DRAM or image sensor , with one embodiment of the invention
`
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`US 10,510,842 B2
`Page 2
`
`Related U.S. Application Data
`Apr. 1 , 2013 , now abandoned , which is a continuation
`of application No. 11 / 622,496 , filed on Jan. 12 , 2007 ,
`now Pat . No. 8,421,195 , which is a division of
`application No. 10 / 934,915 , filed on Sep. 3 , 2004 ,
`now abandoned .
`( 51 ) Int . Ci .
`HOIL 27/02
`HOIL 27/108
`
`( 56 )
`
`( 2006.01 )
`( 2006.01 )
`References Cited
`U.S. PATENT DOCUMENTS
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`4,481,522 A
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`5,262,345 A
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`5,448,087 A
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`5,496,746 A
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`6,211,028 B1
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`2001/0040622 Al
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`
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`
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`
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`
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`
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`html , Oct. 14 , 2013 , 5 pages .
`Z. Cao , Design of Pixel for High Speed CMOS Image Sensors ,
`http://www.imagesensors.org/Past%20Workshops/2013%20Workshop/
`2013 % 20Papers / 07-11_072 - Cao_paper.pdf , 4 pages .
`M. Tanenbaum , BSTJ : Diffused Emitter and Base Silicon Transis
`tors , The Bell System Technical Journal , Jan. 1956 , 22 pages , vol .
`XXXV , https://archive.org/details/bstj35-1-1 .
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`content / user / File / Brochures / cmos % 20imagers % 20brochure - april26 .
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`IEEE Transactions on Electron Devices , vol . Ed - 14 , No. 2 , Feb.
`1967 .
`Berinder Brar et al . , Herb's Bipolar Transistors , IEEE Transactions
`on Electron Devices , vol . 48 , No. 11 , Nov. 2001 .
`* cited by examiner
`
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 1 of 10
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`US 10,510,842 B2
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`
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`Cm ( per
`
`
`
`
`
`Cindy ( per
`
`
`
`
`
`Dopant Concentration
`
`Collector
`
`3
`1
`
`$
`
`$
`sho
`
`Emitter
`
`1
`
`3
`
`that
`1
`
`1
`ws
`7
`7
`
`BASE
`
`Distance
`
`MAK
`
`
`
`Dopant Concentration
`
`
`
`Figure 1 Prior Art
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 2 of 10
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`US 10,510,842 B2
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`uniform ) .
`
`
`
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`concentration is n epitaxial drift region ( 1 - dopant
`
`
`
`N + buffer layer P + substrate
`
`Collector
`
`FIGURE 2 Prior art
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`
`
`WMMWWWWWWWWWWWWWWW **********
`
`Emitter
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 3 of 10
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`US 10,510,842 B2
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`*
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`
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`Active devices
`
`P well
`
`n well
`
`P well
`
`W P substrate
`
`
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`
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`FIGURE 3A Prior art ( Twin well CMOS ) for a CMOS integrated circuit
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 4 of 10
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`US 10,510,842 B2
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`Tunnel Insulator
`
`D layer ,
`
`
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`Storage gate ( for program / erase )
`
`Access Transistor siste
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`P substrate
`
`
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`
`
`FIGURE 3B Prior art for a two - device EEPROM memory cell
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 5 of 10
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`US 10,510,842 B2
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`
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`Storage capacitor
`
`N +
`
`Access Transistor
`
`P substrate
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`
`
`FIGURE 3C Prior art for a 1T - 1C DRAM memory cell
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 6 of 10
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`US 10,510,842 B2
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`N +
`
`Nato
`
`N +
`
`Control / Select Transistor
`
`Control / Select Transistor
`
`Storage
`
`Storage
`
`Storage
`
`P substrate
`
`Prior art for a NAND flash memory cell
`
`
`
`
`
`Note : Control / Sect transistors have a single insulator - traditional
`
`
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`
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`Storage nodes have a stacked gate structure , typically with a floating gate and control gate comprising the stack .
`
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`
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`MOS transistor .
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 7 of 10
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`US 10,510,842 B2
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`
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`FIGURE 4 A dopant - concentration grinded drift region in a IGBT
`
`
`
`
`
`P ---
`
`nepitaxial drift region
`
`
`graded ) .
`
`( n - dopant concentration is
`
`
`layer Pof substrate
`N + buffer
`
`Collector
`
`Emitter
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 8 of 10
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`US 10,510,842 B2
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`P well
`
`n well
`
`P well
`
`
`
`Active devices
`
`
`
`Graded dopant n layer
`
`P substrate
`
`
`
`
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`FIGURE 5A A CMOS Substrate for digital , mixed , signal , and senors IC's
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 9 of 10
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`US 10,510,842 B2
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`
`
`
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`Capacitor or Ksensor Storage element
`
`
`
`Access Transistor
`
`
`
`
`
`
`
`CMOS Substrate for a DRAM or image sensor , with one embodiment of the invention
`
`
`
`
`
`
`
`P substrate
`
`
`
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`
`
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`Graded dopant region to pull minority carriers from surface
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`U.S. Patent
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`Dec. 17 , 2019
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`Sheet 10 of 10
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`US 10,510,842 B2
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`Control / Select Transistor
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`Storage
`
`ControlSect
`
`Transistor
`
`
`Graded dopant
`
`
`
`
`
`
`
`
`
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`region Accelerates carriers towards surface during programming
`
`P substrate
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`FIGURE SC CMOS Substrate for a NAND flash device to improve programming times
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`5
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`30
`
`US 10,510,842 B2
`
`1
`SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`
`2
`sidewalls in a vertical device . Other device architectures to
`combine planar and vertical conductions are also possible .
`The maximum frequency of operation is dictated primarily
`by source - drain separation distance . Most MOS devices use
`CROSS - REFERENCE TO RELATED
`a uniformly doped substrate ( or a well region ) . When a
`APPLICATIONS
`MOSFET is optimally integrated with a BJT in a monolithic
`fashion , an IGBT results . The IGBT inherits the advantages
`This application is a Continuation of U.S. patent appli
`of both MOSFET and BJT . It also brings new challenges
`cation Ser . No. 14 / 931,636 , filed Nov. 3 , 2015 , published on
`because the required characteristics ( electron transit and
`Jun . 16 , 2016 as U.S. Publication No. 2016-0172447 , now
`U.S. Pat . No. 9,647,070 , issued on May 9 , 2017. Application 10 hole recombination as fast as possible in n - channel IGBT )
`Ser . No. 14 / 931,636 is a continuation of U.S. patent appli
`necessitate different dopant gradients either in the same
`cation Ser . No. 14 / 515,584 , filed Oct. 16 , 2014 , published on
`layer at different positions , or at the interfaces of similar or
`Feb. 5 , 2015 , as U.S. Publication No. 2015-0035004 , now
`dissimilar layers .
`U.S. Pat . No. 9,190,502 , issued on Nov. 17 , 2015. Applica
`Retrograde wells have been attempted , with little success ,
`tion Ser . No. 14 / 515,584 is a Continuation of U.S. patent 15 to help improve soft error immunity in SRAMs and visual
`application Ser . No. 13 / 854,319 filed Apr. 1 , 2013 , published
`quality in imaging circuits . FIG . 3A shows a typical CMOS
`on Aug. 29 , 2013 , as U.S. Publication No. 2013-0221488 .
`VLSI device employing a twin well substrate , on which
`Application Ser . No. 13 / 854,319 is a Continuation of Ser .
`active devices are subsequently fabricated . FIGS . 3B , 3C ,
`No. 11 / 622,496 , filed Jan. 12 , 2007 , published on Jul . 12 ,
`and 3D illustrate device cross sections , as practiced today .
`2007 , as Publication No. 2007-0158790 , now U.S. Pat . No. 20 Retrograde and halo wells have also been attempted to
`8,421,195 , issued on Apr. 16 , 2013. Application Ser . No.
`improve refresh time in DRAMs ( dynamic random - access
`11 / 622,496 , is a Division of U.S. patent application Ser . No.
`memories ) , as well as , reducing dark current ( background
`10 / 934,915 , filed Sep. 3 , 2004 , published on Mar. 9 , 2006 ,
`noise ) and enhance RGB ( Red , Green , Blue ) color resolution
`as U.S. Publication No. 2006-0049464 . U.S. Pat . Nos .
`in digital camera ICs . Most of these techniques either divert
`9,647,070,9,190,502 , and 8,421,195 , and Patent Application 25 the minority carriers away from the active regions of critical
`Publication Nos . 2016-0172447 , 2015-0035004 , 2013
`charge storage nodes at the surface , or , increase minority
`0221488 , 2007-0158790 , and 2006-0049464 , are incorpo
`carrier density locally as the particular application requires .
`rated herein by reference in their entirety .
`BRIEF DESCRIPTION OF THE DRAWINGS
`TECHNICAL FIELD
`For a more complete understanding of the present inven
`tion , and the advantages thereof , reference is now made to
`This present invention relates to all semiconductor
`the following descriptions taken in conjunction with the
`devices and systems . Particularly it applies to diffused
`diodes , avalanche diodes , Schottky devices , power MOS accompanying drawings , in which :
`transistors , JFET's , RF bipolar transistors , IGBTs ( Insulated 35
`FIG . 1 illustrates the relative doping profiles of emitter ,
`Gate Bipolar Transistors ) , varactors , digital VLSI , mixed
`base and collector for the two most popular bipolar junction
`signal circuits and sensor devices including camera ICs
`transistors : namely , uniform base ( “ A ” ) and graded base
`employing CCD ( Charge Coupled Device ) as well as CMOS
`( “ B ” ) ;
`technologies .
`FIG . 2 illustrates the cross section of a commercial IGBT
`40 with a uniform epitaxial drift region ( base ) ;
`BACKGROUND
`FIGS . 3A , 3B , 3C , and 3D illustrate cross sections of
`commonly used prior art CMOS silicon substrates ; FIG . 3A
`showing a typical prior art IC with two wells ( one n well in
`Bipolar Junction Transistors ( BJT ) are classified as minor
`which p - channel transistors are subsequently fabricated and
`ity carrier devices because minority carriers are the principle
`device conduction mechanism . However , majority carriers 45 one p well in which n - channel transistors are subsequently
`also play a small but finite role in modulating the conduc
`fabricated ) ; FIG . 3B showing a prior art EEPROM ( Elec
`tivity in BJTs . Consequently , both carriers ( electrons and
`tronically Erasable Programmable Read - Only Memory )
`holes ) play a role in the switching performance of BJTs . The
`memory cell having a tunnel insulator ; FIG . 3C showing a
`maximum frequency of operation in BJTs is limited by the
`prior art DRAM memory cell ; and FIG . 3D showing a prior
`base transit time as well as the quick recombination of the 50 art NAND flash memory cell ;
`majority carriers when the device is switched off ( prior to
`FIG . 4 illustrates the cross section of an IGBT , using one
`beginning the next cycle ) . The dominant carrier mechanism
`embodiment of the invention described here , where the
`in BJTs is carrier diffusion . The carrier drift current com
`dopant is optimally graded in the epitaxial drift region ; and
`ponent is fairly small , especially in uniformly doped base
`FIGS . 5A , 5B , and 5C illustrate the cross sections of a
`BJTs . Efforts have been made in graded base transistors to 55 CMOS silicon substrate with two wells and an underlying
`create an aiding drift field to enhance the diffusing minority
`layer using embodiments of the invention to improve per
`carrier's speed from emitter to collector . However , most
`formance in each application — VLSI logic , DRAM / image
`semiconductor devices , including various power MOSFETs
`nonvolatile memory IC .
`IC ,
`( traditional , DMOS , lateral , vertical and a host of other
`configurations ) , IGBT's ( Insulated Gated Base Transistors ) , 60
`DETAILED DESCRIPTION
`still use a uniformly doped ' drift epitaxial region in the
`base . FIG . 1 shows the relative doping concentration versus
`The relative doping concentrations of emitter and collec
`distance in a BJT . FIG . 2 shows the uniformly doped epi
`tor regions varies from 1018 to 102 ° / cm " , whereas the base
`region in an IGBT . In contrast to BJTS , MOS devices are
`region is 1014 to 1016 / cm
`depending on the desired char
`majority carrier devices for conduction . The conduction is 65 acteristics of the BJT . In graded base p - n - p transistors , the
`channel dominated . The channel can be a surface in one
`donor dopant concentration may be 10 to 100x at the
`plane in planar devices . The surface can also be on the
`emitter - base junction , relative to the base - collector junction
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`4
`3
`bonding or similar “ transfer " mechanisms . This n - layer can
`( 1x ) . The gradient can be linear , quasi linear , exponential or
`be a deeply - implanted layer . It can also be an epitaxial layer .
`complimentary error function . The relative slope of the
`As desired , the n well and p wells can also be graded or
`donor concentration throughout the base creates a suitable
`retrograded in dopants to sweep those carriers away from the
`aiding drift electric field , to help the holes ( p - n - p transistor )
`transverse from emitter to collector . Since the aiding drift 5 surface as well . The graded dopant can also be implemented
`electric field helps hole conduction , the current gain at a
`in surface channel MOS devices to accelerate majority
`given frequency is enhanced , relative to a uniformly - doped
`carriers towards the drain . To decrease programming time in
`( base ) BJT . The improvement in cut - off frequency ( or ,
`nonvolatile memory devices , carriers should be accelerated
`frequency at unity gain , fz ) can be as large as 2x - 5x . Similar
`towards the surface when programming of memory cells is
`performance improvements are also applicable to n - p - n 10 executed . The graded dopant can also be used to fabricate
`superior Junction Field - Effect transistors where the “ channel
`transistors .
`As illustrated in FIG . 4 , in one embodiment according to
`pinch - off ” is controlled by a graded channel instead of a
`uniformly doped channel ( as practiced in the prior art ) .
`the invention , a donor gradient is established from the
`emitter - drift epitaxial base region junction of the punch
`One of ordinary skill and familiarity in the art will
`through IGBT , to the drift epitaxial base region — nt buffer 15 recognize that the concepts taught herein can be customized
`layer boundary ( electrons in this case are accelerated in their
`and tailored to a particular application in many advanta
`transit from emitter to collector ) . The " average ” base resis
`geous ways . For instance , minority carriers can be channeled
`tance is optimized so that conductivity modulation and
`to the surface to aid programming in nonvolatile memory
`lifetime ( for minority carriers ) in the base region are not
`devices ( NOR , NAND , multivalued - cell ) . Moreover , single
`compromised . By sweeping the carriers towards the nt 20 well , and triple - well CMOS fabrication techniques can also
`buffer region a number of advantages are obtained . First , the
`be optimized to incorporate these embodiments individually
`frequency of operation ( combination of ton and tof as is
`and collectively . Any modifications of such embodiments
`known in the IGBT commercial nomenclature ) can be
`( described here ) fall within the spirit and scope of the
`enhanced . Second , and maybe more importantly , during toffs
`invention . Hence , they fall within the scope of the claims
`holes can be recombined much quicker at the nt buffer layer , 25 described below .
`compared to the uniformly doped n epitaxial drift region by
`Although the invention has been described with reference
`establishing a different dopant gradient near the nt buffer
`to specific embodiments , these descriptions are not meant to
`layer . It should be noted that the drift region can also be a
`be construed in a limiting sense . Various modifications of the
`non - epitaxial silicon substrate . Although epitaxy enhances
`disclosed embodiments , as well as alternative embodiments
`lifetime , it is not mandatory . Different layers of dopant 30 of the invention will become apparent to persons skilled in
`regions can be transferred through wafer to wafer bonding
`the art upon reference to the description of the invention . It
`( or other similar transfer mechanisms ) for eventual device
`should be appreciated by those skilled in the art that the
`fabrication . The “ reverse recovery time ” for an IGBT is
`conception and the specific embodiment disclosed may be
`significantly improved due to the optimized graded dopant
`readily utilized as a basis for modifying or designing other
`in the so called “ drift region ” as well as at the interfaces of 35 structures for carrying out the same purposes of the present
`the drift region . Graded dopants can also be implemented in
`invention . It should also be realized by those skilled in the
`the nt buffer layer as well as other regions adjacent to the
`art that such equivalent constructions do not depart from the
`respective layers . Two important performance enhance
`spirit and scope of the invention as set forth in the appended
`ments are the result of dopant gradients . For example , in an
`claims .
`n - channel IGBT , electrons can be swept from source to drain 40
`It is therefore , contemplated that the claims will cover any
`rapidly , while at the same time holes can be recombined
`such modifications or embodiments that fall within the true
`closer to the nt buffer layer . This can improve ton and toff in
`scope of the invention .
`the same device .
`As illustrated in FIGS . 5A , 5B , and 5C , donor gradient is
`What is claimed is :
`also of benefit to very large scale integrated circuits 45
`1. A semiconductor device , comprising :
`( VLSI ) —VLSI logic , DRAM , nonvolatile memory like
`a substrate of a first doping type at a first doping level
`NAND flash . Spurious minority carriers can be generated by
`having first and second surfaces ;
`clock switching in digital VLSI logic and memory ICs .
`a first active region disposed adjacent the first surface of
`These unwanted carriers can discharge dynamically - held
`the substrate with a second doping type opposite in
`“ actively held high ” nodes . In most cases , statically - held 50
`conductivity to the first doping type and within which
`nodes ( with Vcc ) cannot be affected . Degradation of refresh
`transistors can be formed ;
`time in DRAMs is one of the results , because the capacitor
`a second active region separate from the first active region
`holds charge dynamically . Similarly , degradation of CMOS
`disposed adjacent to the first active region and within
`digital images in digital imaging ICs is another result of the
`which transistors can be formed ;
`havoc caused by minority carriers . Pixel and color resolution 55
`transistors formed in at least one of the first active region
`can be significantly enhanced in imaging ICs with the
`or second active region ; and
`embodiments described herein . Creating “ subterranean "
`at least a portion of at least one of the first and second
`recombination centers underneath the wells ( gold doping ,
`active regions having at least one graded dopant con
`platinum doping ) as is done in some high - voltage diodes is
`centration to aid carrier movement from the first sur
`not practical for VLSI circuits . Hence , a novel technique is 60
`face to the second surface of the substrate .
`described herein which creates a drift field to sweep these
`2. The semiconductor device of claim 1 , wherein the
`unwanted minority carriers from the active circuitry at the
`substrate is a p - type substrate .
`surface into the substrate in a monolithic die as quickly as
`3. The semiconductor device of claim
`1 , wherein the
`possible . In a preferred embodiment , the subterranean
`substrate is an n - type substrate .
`n - layer has a graded donor concentration to sweep the 65
`4. The semiconductor device of claim
`1 , wherein the
`minority carriers deep into the substrate . One or more of
`substrate has epitaxial silicon on top of a nonepitaxial
`such layers can also be implemented through wafer to wafer
`substrate .
`
`Greenthread Ex. 2070, p. 14 of 15
`Semiconductor v. Greenthread
`
`

`

`US 10,510,842 B2
`
`5
`5. The semiconductor device of claim 1 , wherein the first
`active region and second active region contain one of either
`p - channel and n - channel devices .
`6. The semiconductor device of claim 1 , wherein the first
`active region and second active region contain either p - chan- 5
`nel or n - channel devices in n - wells or p - wells , respectively ,
`and each well has a graded dopant .
`7. The semiconductor device of claim 1 , wherein the first
`active region and second active region are each separated by
`at least one isolation region .
`8. The semiconductor device of claim
`1 , wherein the
`graded dopant is fabricated with an ion implantation pro
`cess .
`9. A semiconductor device , comprising :
`a substrate of a first doping type at a first doping level 15
`having first and second surfaces ;
`a first active region disposed adjacent the first surface of
`the substrate with a second doping type opposite in
`conductivity to the first doping type and within which
`transistors can be formed in the surface thereof ;
`a second active region separate from the first active region
`disposed adjacent to the first active region and within
`which transistors can be formed in the surface thereof ;
`transistors formed in at least one of the first active region
`or second active region , and
`at least a portion of at least one of the first and second
`active regions having at least one graded dopant con
`centration to aid carrier movement from the surface to
`the substrate .
`
`20
`
`10
`
`25
`
`9 , wherein the
`
`6
`10. The semiconductor device of claim 9 , wherein the
`substrate is a p - type substrate .
`11. The semiconductor device of claim
`substrate is an n - type substrate .
`12. The semiconductor device of claim 9 , wherein the
`substrate has epitaxial silicon on top of a nonepitaxial
`substrate .
`13. The semiconductor device of claim 9 , wherein the first
`active region and second active region contain at least one
`of either p - channel and n - channel devices .
`14. The semiconductor device of claim 9 , wherein the first
`active region and second active region contain either p - chan
`nel or n - channel devices in n - wells or p - wells , respectively ,
`and each well has a graded dopant .
`15. The semiconductor device of claim 9 , wherein the first
`active region and second active region are each separated by
`at least one isolation region .
`16. The semiconductor device of claim 9 , wherein the
`graded dopant is fabricated with an ion implantation pro
`cess .
`17. The semiconductor device of claim 1 , wherein the first
`and second active regions are formed adjacent the first
`surface of the substrate .
`18. The semiconductor device of claim 1 , wherein the
`transistors which can be formed in the first and second active
`regions are CMOS transistors requiring a source , a drain , a
`gate and a channel region .
`
`Greenthread Ex. 2070, p. 15 of 15
`Semiconductor v. Greenthread
`
`