US009 190502B2
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`(12) United States Patent
`Rao
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`(10) Patent No.:
`(45) Date of Patent:
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`US 9,190,502 B2
`*Nov. 17, 2015
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`(54) SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
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`(71) Applicant: G. R. Mohan Rao, Allen, TX (US)
`
`(72) Inventor: G. R. Mohan Rao, Allen, TX (US)
`(73) Assignee: Greenthread, LLC, Dallas, TX (US)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`This patent is Subject to a terminal dis-
`claimer.
`(21) Appl. No.: 14/515,584
`(22) Filed:
`Oct. 16, 2014
`(65)
`Prior Publication Data
`US 2015/OO35OO4A1
`Feb. 5, 2015
`
`Related U.S. Application Data
`(60) Continuation of application No. 13/854.319, filed on
`Apr. 1, 2013, now abandoned, which is a continuation
`of application No. 1 1/622,496, filed on Jan. 12, 2007,
`now Pat. No. 8,421,195, which is a division of
`application No. 10/934,915, filed on Sep. 3, 2004, now
`abandoned.
`
`(51) Int. Cl.
`HOIL 21/02
`HOIL 29/739
`HOIL 27/5
`HOIL 29/36
`HOIL 27/02
`HOIL 27/108
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`(52) U.S. Cl.
`CPC ...... HOIL 29/7395 (2013.01); HOIL 27/11521
`(2013.01); HOIL 27/11524 (2013.01); HOIL
`29/36 (2013.01); HOIL 27/0214 (2013.01);
`HOIL 27/10844 (2013.01)
`(58) Field of Classification Search
`CPC ................................................... HO1L 29/7395
`USPC ............................................................ 438/37
`See application file for complete search history.
`References Cited
`
`(56)
`
`
`
`U.S. PATENT DOCUMENTS
`4,160,985 A * 7/1979 Kamins et al. ................ 257/443
`2001/0040622 A1* 1 1/2001 Maruyama ...................... 348.64
`2003/0030488 A1* 2/2003 Hueting et al. ................. 33Of 57
`* cited by examiner
`Primary Examiner — Ajay K Arora
`(74) Attorney, Agent, or Firm — Howison & Arnott, LLP
`(57)
`ABSTRACT
`Most semiconductor devices manufactured today, have uni
`form dopant concentration, either in the lateral or vertical
`device active (and isolation) regions. By grading the dopant
`concentration, the performance in various semiconductor
`devices can be significantly improved. Performance improve
`ments can be obtained in application specific areas like
`increase in frequency of operation for digital logic, various
`power MOSFET and IGBTICS, improvement in refreshtime
`for DRAMs, decrease in programming time for nonvolatile
`memory, better visual quality including pixel resolution and
`color sensitivity for imaging ICs, better sensitivity for Varac
`tors in tunable filters, higher drive capabilities for JFETs, and
`a host of other applications.
`
`12 Claims, 10 Drawing Sheets
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`AccessTrausisor
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`Storage Capacitor or
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`Graded dopant region to pull minority carriers from surface
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`P substrate
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`CMOS Substrate for a DRAM or image sensor, with one embodiment of the investigia
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`1.
`SEMCONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
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`US 9, 190,502 B2
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`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This continuation application claims priority to and the
`benefit of U.S. application Ser. No. 13/854.319, filed on Apr.
`1, 2013, which is a continuation of U.S. application Ser. No.
`1 1/622,496, filed Jan. 12, 2007, now U.S. Pat. No. 8,421, 195,
`which is a divisional of U.S. application Ser. No. 10/934,915,
`filed on Sep. 3, 2004, now abandoned, all of which are incor
`porated by reference.
`
`FIELD OF INVENTION
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`This present invention relates to all semiconductor devices
`and systems. Particularly it applies to diffused diodes, ava
`lanche diodes, Schottky devices, power MOS transistors,
`JFETs, RF bipolar transistors, IGBTs (Insulated Gate Bipo
`lar Transistors), Varactors, digital VLSI, mixed signal circuits
`and sensor devices including camera ICs employing CCD
`(Charge Coupled Device) as well as CMOS technologies.
`
`BACKGROUND OF INVENTION
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`Bipolar Junction transistors (BJT) are minority carrier
`devices as the principle device conduction mechanism. How
`ever, majority carriers also a small yet finite role in modulat
`ing the conductivity in BJTs. Consequently, both carriers
`(electrons and holes) play a role in the Switching performance
`of BJTs. The maximum frequency of operation in BJTs is
`limited by the base transit time as well as the quick recombi
`nation of the majority carriers when the device is switched off
`(prior to beginning the next cycle). The dominant carrier
`mechanism in BJTs is carrier diffusion. Carrier drift current
`component is fairly Small, especially in uniformly doped base
`BJTs. Efforts have been made in graded base transistors to
`create an aiding drift field, to enhance the diffusing minority
`carrier's speed from emitter to collector. However, most
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`semiconductor devices, including various power MOSFETs
`(traditional, DMOS, lateral, vertical and a host of other con
`figurations), IGBTs (Insulated Gated Base Transistors), still
`use a uniformly doped drift epitaxial region in the base. FIG.
`1 shows the relative doping concentration versus distance in a
`BJT. FIG. 2 shows the uniformly doped epi region in a
`IGBT. In contrast to BJTs, MOS devices are majority carrier
`devices for conduction. The conduction is channel domi
`nated. The channel can be a surface in one plane in planar
`devices. The surface can also be on the sidewalls in a vertical
`device. Other device architectures to combine planar and
`Vertical conductions are also possible. The maximum fre
`quency of operation is dictated primarily by source-drain
`separation distance. Most MOS devices use a uniformly
`doped substrate (or a well region). When a MOSFET is opti
`mally integrated with a BJT in a monolithic fashion, an IGBT
`results. The IGBT inherits the advantages of both MOSFET
`and BJT. It also brings new challenges because the required
`characteristics (electron transit and hole recombination as
`fast as possible in the case of an n-channel IGBT) require
`different dopant gradients either in the same layer at different
`positions, or at the interfaces of similar or dissimilar layers.
`Retrograde wells have been attempted, with little success,
`to help improve soft error immunity in SRAM's and visual
`quality in imaging circuits. FIG.3(a) shows a typical CMOS
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`VLSI device employing a twin well substrate, on which active
`devices are subsequently fabricated. FIGS. 3(b), 3(c), and
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`3(d) illustrate device cross sections, as practiced today. Ret
`rograde and halo wells have also been attempted to improve
`refresh time in DRAMs (dynamic random access memo
`ries), as well as, reducing dark current (background noise)
`and enhance RGB (Red, Green, Blue) color resolution in
`digital camera Ics. Most of these techniques either divert the
`minority carriers away form the active regions of critical
`charge storage nodes at the Surface, or, increase minority
`carrier density locally as the particular application requires.
`
`BRIEF DESCRIPTION OF DRAWINGS
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`For a more complete understanding of the present inven
`tion, and the advantages thereof, reference is now made to the
`following descriptions taken in conjunction with the accom
`panying drawings, in which:
`FIG. 1 illustrates the relative doping profiles of emitter,
`base, and collector, for the two most popular bipolar junction
`transistors: namely, A uniform base, and B graded base;
`FIG. 2 illustrates the cross section of a commercial IGBT
`with a uniform epitaxial drift region (base);
`FIGS. 3(a), 3(b), 3(c), 3(d) illustrate cross sections com
`monly used CMOS silicon substrate with two wells (one
`n-well in which p-channel transistors are Subsequently fabri
`cated, and, one p-well in which n-channel transistors are
`subsequently fabricated) typical IC, EEPROM using tunnel
`insulator, DRAM and NAND flash:
`FIG. 4 illustrates the cross section of a IGBT, using one
`embodiment of the invention described here, where the
`dopant is optimally graded in the eptaxial drift region; and
`FIGS. 5(a),5(b),5(c) illustrate the cross sections of a MOS
`silicon Substrate with two wells, and, an underlying layer
`using embodiments of the invention to improve performance
`in each application VLSI logic, DRAM/image IC, nonvola
`tile memory IC.
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`DETAILED DESCRIPTION OF THE INVENTION
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`The relative doping concentrations of emitter and collector
`regions varies from 10' to 10'/cm, whereas the base region
`is 10' to 10"/cm depending on the desired characteristics of
`the BJT. In graded base p-n-p transistors, the donor dopant
`concentration may be 10 to 100x at the emitter-base junction,
`relative to the base-collector junction (1X). The gradient can
`be linear, quasi linear, exponential or complimentary error
`function. The relative slope of the donor concentration
`throughout the base, creates a suitable aiding drift electric
`field, to help the holes (p-n-p transistor) transverse from emit
`ter to collector. Since the aiding drift field helps hole conduc
`tion, the current gain at a given frequency is enhanced, rela
`tive to a uniformly-doped-(base) BJT. The improvement in
`cut-off frequency (or, frequency at unity gain, f,) can be as
`large as 2x-5x. Similar performance improvements are also
`applicable to n-p-n transistors.
`As illustrated in FIG. 4, in one embodiment according to
`the invention, a donor gradient is established from the emit
`ter-drift epitaxial base region junction of the punch-through
`IGBT, to the drift epitaxial base region n' buffer layer
`boundary (electrons in this case are accelerated in their transit
`from emitter to collector). The average base resistance is
`optimized, so that conductivity modulation and lifetime (for
`minority carriers) in base region are not compromised. By
`Sweeping the carriers towards the n' buffer region two advan
`tages are obtained—the frequency of operation (combination
`oft, and tas is known in the IGBT commercial nomencla
`ture) can be enhanced. More importantly, during to holes can
`be recombined much quicker at the n' buffer layer, compared
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`to a uniformly doped in epitaxial drift region by establishing
`a different dopant gradient near the n+ buffer layer. It should
`be noted that the drift region can also be a non-epitaxial
`silicon Substrate. Epitaxy enhances lifetime, but, epitaxy is
`not mandatory. Different layers of dopan regions can be trans
`ferred through wafer to wafer bonding (or other similar trans
`fer mechanisms) for eventual device fabrication. The “reverse
`recovery time’ for an IGBT is significantly improved due to
`the optimized graded dopant in the so called “drift region” as
`well as at the interfaces of the drift region. Graded dopants
`can also be implemented in the n+buffer layer as well as other
`regions adjacent to the respective layers. Two important per
`formance enhancements are the result of dopant gradients.
`For example, in an n-channel IGBT, electrons can be swept
`from source to drain rapidly, while at the same time holes can
`be recombined closer to the n+buffer layer. This can improve
`t(on) and t(off) in the same device.
`The following paragraph, beginning on page 5, line 6, and
`ending on page 11, line 28, is amended as indicated in the
`marked up version below:
`As illustrated in FIGS. 5(a), 5(b), 5(c), donor gradient is
`also of benefit to very large scale integrated circuits (VLSI)—
`VLSI logic, DRAM, nonvolatile memory like NAND flash.
`Spurious minority carriers can be generated by clock Switch
`ing in digital VLSI logic and memory ICS. These unwanted
`carriers can discharge dynamically-held actively held high
`nodes. Statically held nodes (with V) can not be affected, in
`most cases. Degradation of refresh time in DRAMs is one of
`the results, because the capacitor holds charge dynamically.
`Similarly, degradation of CMOS digital images, in digital
`imaging ICS is another result of the havoc caused by minority
`carriers. Pixel and color resolution can be significantly
`enhanced in imaging ICs with the embodiments described
`here. Creating Sub Terrain recombination centers under
`neath the wells (gold doping, platinum doping) as is done in
`Some high-voltage diodes is not practical for VLSI circuits.
`Hence, a novel technique has been described hereby creating
`a drift field to sweep these unwanted minority carriers into the
`Substrate as quickly as possible, from the active circuitry at
`the surface. In a preferred embodiment, the subterrain n-layer
`has a graded donor concentration to Sweep the minority car
`riers deep into the substrate. One or more of such layers can
`also be implemented through wafer to wafer bonding or simi
`lar “transfer mechanisms. This n-layer can be a deeply
`implanted layer. It can also be an epitaxial layer. The n-well
`and p-well also can be graded or retrograded in dopants, as
`desired, to Sweep those carriers away from the Surface as well.
`The graded dopant can also be implemented in Surface chan
`nel MOS devices to accelerate majority carriers towards the
`drain. In nonvolatile memory devices, to decrease program
`ming time, carriers should be accelerated towards the Surface
`when programming of memory cells is executed. The graded
`dopant can also be used to fabricate Superior Junction field
`effect transistors where the “channel pinchoff is controlled
`by a graded channel instead of a uniformly doped channel (as
`practiced in prior art).
`One of ordinary skill and familiarity in the art will recog
`nize that the concepts taught herein can be customized and
`tailored to a particular application in many advantageous
`ways. For instance, minority carriers can be channeled to the
`Surface, to aid programming in nonvolatile memory devices
`(NOR, NAND, multivalued-cell). Moreover, single well, as
`well triple-well CMOS fabrication techniques can also be
`optimized to incorporate these embodiments, individually
`and collectively. Any modifications of Such embodiments
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`(described here) fall within the spirit and scope of the inven
`tion. Hence, they fall within the scope of the claims described
`below
`Although the invention has been described with reference
`to specific embodiments, these descriptions are not meant to
`be construed in a limiting sense. Various modifications of the
`disclosed embodiments, as well as alternative embodiments
`of the invention will become apparent to persons skilled in the
`art upon reference to the description of the invention. It
`should be appreciated by those skilled in the art that the
`conception and the specific embodiment disclosed may be
`readily utilized as a basis for modifying or designing other
`structures for carrying out the same purposes of the present
`invention. It should also be realized by those skilled in the art
`that such equivalent constructions do not depart from the
`spirit and scope of the invention as set forth in the appended
`claims.
`It is therefore, contemplated that the claims will cover any
`such modifications or embodiments that fall within the true
`Scope of the invention.
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`What is claimed is:
`1. A semiconductor device comprising:
`a surface layer,
`a Substrate;
`an active region including a source and a drain, disposed on
`one surface of said Surface layer,
`a single drift layer disposed between the other surface of
`said Surface layer and said Substrate, said drift layer
`having a graded concentration of dopants generating a
`first static unidirectional electric drift field to aid the
`movement of minority carriers from said Substrate to
`said Surface layer, and
`at least one well region disposed in said single drift layer,
`said well region having a graded concentration of
`dopants generating a second static unidirectional elec
`tric drift field to aid the movement of minority carriers
`from said Substrate to said surface layer.
`2. The semiconductor device of claim 1 wherein said first
`and second static unidirectional electric fields are adapted to
`respective grading of dopants to aid movements of carriers in
`respective active regions.
`3. The semiconductor device of claim 1 wherein the semi
`conductor device is a central processing unit (CPU).
`4. The semiconductor device of claim 1 wherein the semi
`conductor device is a DRAM device.
`5. The semiconductor device of claim 1 wherein the semi
`conductor device is a flash memory device.
`6. The semiconductor device of claim 1 wherein the semi
`conductor device is an image sensor device.
`7. A semiconductor device comprising:
`a surface layer,
`a Substrate;
`an active region including a source and a drain, disposed on
`one surface of said Surface layer,
`a single drift layer disposed between the other surface of
`said Surface layer and said Substrate, said drift layer
`having a graded concentration of dopants generating a
`first static unidirectional electric drift field to aid the
`movement of minority carriers from said Surface layer to
`said Substrate; and
`at least one well region disposed in said single drift layer,
`said well region having a graded concentration of
`dopants generating a second static unidirectional elec
`tric drift field to aid the movement of minority carriers
`from said Surface layer to said Substrate.
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`8. The semiconductor device of claim 7 wherein said first
`and second static unidirectional electric fields are adapted to
`respective grading of dopants to aid movements of carriers in
`respective active regions.
`9. The semiconductor device of claim 7 wherein the semi- 5
`conductor device is a central processing unit (CPU).
`10. The semiconductor device of claim 7 wherein the semi
`conductor device is a DRAM device.
`11. The semiconductor device of claim 7 wherein the semi
`conductor device is a flash memory device.
`12. The semiconductor device of claim 7 wherein the semi
`conductor device is an image sensor device.
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