John Y. Chen
`
`J/
`
`/✓
`
`CMOS DEVICES
`AND TECHNOLOGY
`FOR VLSI
`
`PRENTICE HALL, Englewood Cliffs, New Jersey 07632
`
`Greenthread Ex. 2065, p. 1 of 47
`Semiconductor v. Greenthread
`
`

`

`TO MY PARENTS
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`l.ihran• of Cm,,:rrn C•1a/o,:i1111•i11- P11J,ljn11i1111 [)11.111
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`C11~i,;. Jo11~ Y.
`CMOS d~,iccs and 1«hnol-,~· for VLSI John Y. 0,,-n
`I'
`cm
`l:libl,ography p
`ln<"ludc, indu
`ISBN 0.11-1~.(,
`lnI~gr3tCd c11cuiis-Vc11 tar~ !<Glk 1n1q;ra.lM>n 1 !',1,:e;,t
`I
`I Ti1Jc
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`or
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`
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`Cover de>ign- DIANI! S,-.XE
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`
`() 1990 by Prentice-Hall. Inc.
`A Division of Simon & Schust,:r
`Englewood Oirr,. New krscy 076..1~
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`w11hout pcrrmss1on m wnung from the publr..her.
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`Printed in the United Swi.:s of America
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`l'Jtn,mc, -H,-.u. m Au~,'RAU,\ f>n . l.lMITI·(), S,·d11n
`PRD-'TI<""•HAI.L CA'IADA 11'1<: .. Turumo
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`
`Greenthread Ex. 2065, p. 2 of 47
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`

`CONTENTS
`
`PREFACE
`
`BIOGRAPHY
`
`1 INTRODUCTION TO CMOS. THE VLSI
`TECHNOLOGY
`
`2 CMOS DEVICE PHYSICS
`2.1 ELECTRONS AND HOLES
`2.2 MOS CAPACITORS
`10
`2.3 MOS TRANSISTORS
`16
`2.4 BURIED CHANNEL DEVICES
`27
`2.5 SHORT-AND NARROW-CHANNEL EFFECTS
`
`6
`
`33
`
`3 MOS MODELLING
`3.1 MODELLING FOR CMOS TECHNOLOGY
`DEVELOPMENT
`38
`3.2 MODELS FOR INDIVIDUAL PROCESS MODULES
`3.3 MODELS FOR PROCESS INTEGRATION
`56
`3.4 TWO-DIMENSIONAL DEVICE MODELS
`61
`3.5 DEVICE PARAMETER EXTRACTION FOR CIRCUIT
`STIMULATION
`70
`
`41
`
`xi
`
`xv
`
`1
`
`5
`
`38
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`ix
`
`323
`
`338
`
`343
`
`viii
`
`Contents
`
`Contents
`
`301
`8.5 AVOIDING LATCHUP
`8.6 LAYOUT CONSIDERATIONS
`8.7 SUMMARY
`317
`
`309
`
`9 CMOS DESIGN RULES
`9.1 DESIGN RULES DERJVATION
`323
`9.2 LAMBDA-BASED DESIGN RULES
`328
`9.3 LIMITATION OF LAMBDA RULES ANO THEIR
`MODIFICATIONS
`331
`9.4 SUBMICRON DESIGN RULES AND THEIR IMPACTS
`9.5 SUMMARY AND FUTURE PERSPECTIVES
`334
`
`332
`
`LIST OF SYMBOLS
`
`INDEX
`
`4 CMOS OPERATION
`INVERTERS
`92
`4.1
`4.2 A CMOS OUTPUT BUFFER
`101
`4.3 TRANSMISSION GATE AS A SWITCH
`105
`4.4 CMOS LOGIC GATES
`4.5 DYNAMIC CMOS LOGIC
`106
`4.6 CMOS RAMS
`110
`
`103
`
`5 CMOS PROCESS TECHNOLOGY
`5.1 PROCESS ARCHITECTURE
`119
`5.2 P-WELL PROCESS
`122
`5.3 N-WELL PROCESS
`125
`5.4 P-WELL VERSUS N•WELL
`5.5 TWIN•TUB PROCESS
`128
`5.6 RETROGRADE-WELL PROCESS
`130
`5.7 CHOICE OF PROCESS ARCHITECTURES
`5.8 SOS TECHNOLOGY
`136
`5.9 SOI TECHNOLOGY
`142
`5.10 BIPOLAR/CMOS INTEGRATION-BICMOS
`
`127
`
`136
`
`149
`
`6 CMOS TRANSISTOR DESIGN
`6.1 MOSFET SCALING
`175
`6.2 NON-SCALABLE DEVICE PARAMETERS
`176
`6.3 TRANSISTOR DESIGN FOR SHORT-CIRCUIT
`MOSfETS
`182
`6.4 HOT CARIUER EFFECTS ANO nMOS DESIGN FOR
`RELIABILITY
`183
`6.5 BURIED-CHANNEL EFFECTS AND pMOS
`DESIGN
`211
`
`7 CMOS !SOLA TION
`7.1 BACKGROUND
`233
`7.2 MOS ISOLATION TECHNIQUES
`7.3
`ISOLATION IN CMOS
`249
`7.4 NEW ISOLATION TECHNIQUES FOR CMOS
`7.5
`ISOLATION DESIGN RULES IN CMOS
`277
`
`238
`
`272
`
`8 LA TCHUP IN CMOS
`INTRODUCTION
`8.1
`285
`8.2 PHYSICS AND LUMPED CIRCUIT MODEL
`8.3 PARASITIC TRANSISTORS AND RESISTORS
`8.4 LATCHUP CHARACTERIZATION
`291
`
`286
`288
`
`92
`
`119
`
`174
`
`233
`
`285
`
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`

`Sec. 2.3
`
`MOS Transistors
`
`19
`
`2.3.2 MOSFET Operation
`
`When a voltage greater than V, is applied to a gate. the semiconductor
`surface is invened to ,Hype and a tv!OSFET channel is formed. as shown in
`Fig. 2.11 . For small drain YOltages, the entire channel is inverted and channel
`conductance is proportional to the in\'ersion charges. This area is the linear
`region in which the drain current f.1 is proportional to V,1 and the FET acts
`as a resistor. As V" increases and reaches a point such that (V" + 2<l>R) is
`just larger than the band bending produced by the gate, oltagc, the inversion
`disappears at point X near the drain (Fig. 2.11 b). The channel is then pinched
`off at this point and the corresponding drain voltage is defined as V,1-c,1 because
`for v., > V,1._11 , f,1 remains essentially constant. As shown in Fig. 2.1 l(c),
`the additional voltage above V,1,.11 is consumed for widening the depletion
`region and the potential at Point X 1 emai ns constant. Point X move!> towa rd
`the source as V,1 exceeds V,1,.11 • but the movement is very slight ; hence, /,1
`increases very little. The drain current basically remains at a constant level,
`l ,1,c,,, for V,1 > V,i-:11 , However, for a device with very short channel length,
`a slight movement of the pinchoff point can be a significant portion of the
`entire channel length, thereby causing significant increase of I.,"11 • Other
`short channel effects will be discussed in Sec. 2.5.
`
`Linear and saturation regions. This section derives the basic t-.lOS(cid:173)
`[fa MOSFET is biased with sufficient gate voltage to
`FET characteristics.
`cause surface inversion, the free charge in the invcn,ion layer at a distance y
`from the source is
`
`(2. 1-l)
`
`Q,,(y) '-' Q,(y) Oo(Y)
`,,here Q,(y) ts the charge induced in the semiconductor per unit area at Point
`y. Because
`Q,(y) = - co,IVi:' - <l>,(y)] = - c o,{Vi,:' - 12<1>11
`
`' V(y)]}
`
`(2.15)
`
`v, > v, v, = v.,..,
`
`V0 > V,
`
`n
`
`'
`
`n·
`
`n 1
`
`X
`
`n'
`
`n X
`
`p
`
`(al
`
`p
`
`(b)
`
`n
`
`•
`
`p
`
`(c)
`
`lllus1rat1on of the operaIIon of a 1'10SFET for \ , > \', • (a) V., <<
`Figure 2.11
`J = V ,,,.: am.I (c) V J> V
`. ~ • ( Ref I )
`, , : (b) V
`
`V
`
`,
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`Sec. 2.4
`
`Buried Channel Devices
`
`27
`
`T he discussion of an inverter circuit in Chapter -l will illw,tratc the significance
`of the body effect on circuit performance.
`
`MOSFET types. All der ivations previously mentioned use 11-channel
`transistors as an example. Similar results can be obtained for p-channel
`devices with reverse polari ty for all terminal voltages and threshold voltage .
`Table 2.1 summarizes important equations for 11- and p-channel MOSF- ETs.
`Jn both cases. the devices are off unles~ a sufficien t gate , oltage is applied.
`T his type of device (normally-off) i~ called an enhancement mode device.
`Another type of transistor is normally on unless reverse-polarity V;r (e.g ..
`negative Vg for an 11-channel) is applied to turn it off. These dc,icc~ (nor(cid:173)
`mally-on) arc called depletion mode devices.
`For an 11-cha11 ncl depiction de, ice. the threshold voltage is made neg(cid:173)
`ative by adding an arsenic ion implantation during device fabrication. A
`total of fo ur different l)pcs of f\lOSFEn re!>ult, as c,hown in Fig. 2.17. The
`corresponding 1-V characteristic~ arc also ~ho,\.n.
`In 11-channel cases. a pos(cid:173)
`itive Vg must be applied to turn on an enhancement-mode device. But. a
`negative Vg must be applied 10 turn a depletion-mode device off. A deple(cid:173)
`tion-mode device delivers cu rrent at Vg = 0 and is often used as the load
`device in NMOS logic circuits.
`In p-channel cases. one applies a negative
`V.r: to turn on an enhancement-moc.Jc device. but a pm,itive \/~ to turn off a
`dcplction-moclc device.
`I lowcver. c.Jcpletion-mode p-channel devices are
`normally not used in present MOS technologies.
`In a CMOS ci rcuit . en(cid:173)
`hancement mode p-channel MOSFET s arc oft en used as load devices. A
`depiction-mode device is commonly made by forming a thi n 11-1ype ~urfacc
`layer in the p-substratc for 11-channel cases or a thin /Hype surface layer in
`the 11-substrate for p-channel case~. T hus. l.0urce and drain arc connected
`with the same type of semiconductor layer unless this layer i~ full y depicted
`by applying the appropriate gate voltage. T he presence of this surface layer
`however changes normal MOSFET operation from surface-channel conduc(cid:173)
`tion to buried-channel conduction.
`
`2.4 BURIED CHANNEL DEVICES
`
`Discussions so far have covered device operations in surface-channel M OS(cid:173)
`FETs in which carriers propagate at the semiconductor surface. Howc,er.
`in some devices such as depiction-mode devices. carri ers propagate slightly
`under the semiconductor surface. This type of device is called a buried(cid:173)
`channel device. Fig. 2. 18 shows the cross-section of a buried-channel nMOS
`device. Notice the 11-type layer with the doping concentration N O and junc(cid:173)
`tion depth xi. The device h:is two depiction regions. The bottom region
`originated from the p-11 junction. and the top region is associated " ith the
`MOS capacitor. The depiction width is not uniform because. under the bias
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`

`, ..
`
`v ...
`
`p-S,
`
`nMOS
`
`(al
`
`AOOAESS (5-81
`
`I
`
`I
`
`TOP LAYER
`
`I
`
`,;-
`._,
`'-
`
`""
`
`g,.'<,
`9
`,$
`
`I
`
`Ooul
`
`CMOS Process Technology
`
`Chap.5
`
`Sec. 5.10
`
`Bipolar/CMOS lntegration-BiCMOS
`
`149
`
`v..,
`
`NMOS
`
`v ..
`
`,;~ ..
`
`I
`
`I
`
`n-S,
`
`pMOS
`
`(bl
`
`BOTTOM
`LAYER
`
`Figure S.:ZI Schematic cross-sections of a 3·0 CMOS/SOI inv~rttr: (a) Joim-gatc
`(JMOS) type; and {b) stacked type (Ref. 33. C 1983. IEEE).
`
`To date. a l.lK gate array\6 and a 256 bit SRAM'' ha\'e been dcm•
`onstrated for 3-0 CMOSiSOl. The 8K bit parallel array multiplier in the
`gate array exhibits complete operation. The 256-bit SRAM 1s configuratcd
`with the NMOS memory cells m the bottom layer and the CMOS peripheral
`circuits in the top layer as shown in Fig. 5.22. Complete mcmor~ operation
`including the intralaycr and interlayer data transfer has been demonstrated.
`Both these circuits were fabricated with a laser recrystallized SOI layer. An
`even larger circuit. a 64K SRAM. was demonstrated"' using ,,-channel loads
`made in a non-crystallized polysilicon SOI layer. The as-deposited polysil·
`icon was hydrogen passivated rather than beam recrystallized for manufac(cid:173)
`turability. Although the p-channel polysilicon FE Ts had low mobility. the
`resultant CMOS configuration provided lower stutic power than that of a
`conventional NMOS RAM with poly load resistors. On the other hand. SOI
`advantages such as latchup free. high density. high alpha pamcle immunity
`also existed in this structure.
`Despite 1he fact that sizable CMOS circuits have been demonstrated in
`two-layer SOI. 3-D VLSI using CMOSfSOI technology has u long wa~ to go
`
`Flgu,... 5.22 Circuit dia11ram of a ~-D Slalii: RAM (Rd. 37, , IYi;i,. IEEE).
`
`for production. A reliable and high-throughput rccryst.alltiatn>n process for
`SOI layers is needed.
`Intra- and in1er-layc:r interconnection \\ith planari(cid:173)
`zat1on must be developed. High yield. fa~t turn-.iroun<l and rc<lun<lancc
`circuits are other concerns for VLSI fabrication.
`
`5.10 BIPOLAR/CMOS INTEGRATION-BiCMOS
`
`As described in Chapter I. CMOS offers low power \\ hich b attracti\·e for
`VLSI. especially in digital application~. Ho\\cvcr. thc ,pccd of CMOS.
`although comparahle with NMOS. is slower than 11.•h;tt hip1));ir can provide.
`It is particularlv true when hcavv-loiJdml!. or Joni!. intcn:unnccb m:cd tll he
`driven. A bipolar transistor not ·onlv ca~ deliver~a larl!.C current. it also has
`well-controlled turn-on voltage. good noise murgin and small logic ~wini for
`
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`

`150
`
`CMOS Process Technology
`
`Chap. 5
`
`Sec. 5.10
`
`Bipolar CMOS lnregration-8iCMOS
`
`151
`
`ECL (Emitter-Coupled Logic). ECL also provides_ a high speed s_ense am•
`plifier for static RAMs. All these advantages ~ake 1t sunahlc tor _high speed
`circuits and analog applications.
`Its major d1sadvanlilges arc: high power.
`poor density and limited circuit options.
`.
`BiCMOS technology is the integration of bipolar and CMOS devices
`on a single chip. The intent is to offer high dens~ty. low power C~OS arrays
`It can also provide analog and dt~ttal syst~m
`with high speed bipolar drivers.
`integration on the same chip. With BiCMOS. the advantage of high denslly
`and low power in CMOS can be combined with the speed ;idvant~~e offered
`by bipolnr. Other improvements include ECL and TTL (Transistor Tran
`sistor Logic) interface, high speed I/Os. less sensitivity to fan-out and ~utput
`load. reduced clock skew and improved internal gate delay. Because hrpolar
`devices offer more current driving ability. for high speed applications. Bi(cid:173)
`CMOS does not have to be down-scaled as much as CMOS. One-to-two
`micron BiCMOS can offer circuit speed as high as submicron CMOS. Con(cid:173)
`sequently. the 5 V power supply can be maintained _amt submicr~n proce\S
`needs are not as high. The major drawbacks to B1CMOS arc higher cost
`and longer fabrication time.
`
`5.10. 1 BiCMOS Operation
`
`Figure 5.23 shows a BiCMOS inverter. When the input ( V;,.) is low.
`both NO and Nl are off but the p-channel device is on and the base of the
`upper npn bipolar rises to V 8 1 and above, turning t_he bipolar on a~d pullin_g
`. , up to V DD - V oF· When the input (V;0 ) 1s switched to high. Q 1 is
`the V0
`cut off. and so is N2; but Nl is turned on and the base of the lower 11p11
`bipolar is charged (V .,..,) to V m, • turning the bipolar on and pulling the output
`voltage (V,,) down to V .11c•
`Because the Bi CMOS output does not swing the full rail ( V no to ground).
`the superior noise margin and zero static power dissipation inherent in CMOS
`are not fully maintained. As the output is pulled down. V,,.., goes to Vo,,;
`although V °"' eventually can be discharged below V ,.,.;, it would lake an
`unreasonably long time. For practical cases. the BiCMOS output does not
`go to ground, noise margin is therefore degraded and whe~ it ~rives !o another
`CMOS input gate, power dissipation for the CMOS gate 1s slightly increased.
`The amount of power dissipation depends on the threshold of the 11-channel
`FET in the CMOS input gate. If 1 µA is used to define the threshold voltage
`(Vr.,), the static current dissipated at then-channel FET of the CMOS gate
`can be approximated as
`Iv = 10 i. -
`(Vr .. - V0 .,)IS, in Amp
`where V r .. is the 11-channel FET threshold voltage and S, is the FET subthres(cid:173)
`hold factor in mV per decade as described in Chapter 2 (Eq. 2.36). The
`static power dissipation of the CMOS gate. which is proportional to / o• can
`
`(5.1)
`
`V .
`
`-
`
`NI
`
`Qt
`
`Q2
`
`v,,.,
`
`81CMOS Inverter
`
`fl,:un 5.Z3 C1rcui1 sch"m~tic of n BiCMOS mv.,rlcr.
`
`be reduced by increasing the threshold voltage and decreasing subthreshold
`swing. However. 100 high a threshold voltage results in lower current driving
`ability. hence poorer circuit speed. As an example. if V1 ,. .. 0.7 V. S, -
`JOO m V /decade. then J v .a I µA because V Ht: ~ 0. 7 V.
`If V 1" is raised 10
`l V, then 10
`1 nA. an improvement o{ three orders of magnitude in power
`dissipation.
`Figure 5.24 shows delay time for the BiCMOS invcner plotted versus load
`capacitances (Ci.).39 Notice that the speed improvemen1 is greater as the load
`capacitance becomes larger. This improvement is due to the fact that a bipolar
`device nonnally delivers much more current than a MOS device. Therefore.
`compared to CMOS. bipolar or BiCMOS is less scnsicive to the output load
`capacitance. In first order approXJmatt0n. the slope of the line 1s roughly
`s,. "" r,,.,tC, - Q!(l, C,_) .. Vj / 1
`"' V.,110 for the CMOS case
`
`(5.2)
`
`= V"llc = V.,!(~/8) for the BiCMOS case
`
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`

`152
`
`CMOS Process Technology
`
`Chap. 5
`
`Sec. 5.10
`
`Bipolar/CMOS lntegration-BiCMOS
`
`153
`
`o CMOS Ln = 1 2. Wn = 15 0.
`lp = 1 2. Wp • 20 0 ,.m
`o e,CMOS Ae • 1 4 pm X 2 6 i,m ( 1 X)
`■ B,CMOS Ae • 1 4 ,.m X 5 2 ,.m ! 2X)
`
`1 4
`
`1 2
`
`1.0
`
`.,
`E.
`
`.;
`
`>-.. 08
`0 .. i 06
`
`,ii
`
`'b
`
`f
`
`04
`
`02
`
`0
`
`0
`
`Load Capacitance(pfl
`o., 0 .2 03 0.4 0.5 0.6 0 .7
`
`2
`
`4
`
`6
`
`8
`
`10
`
`12
`
`Fan-out
`
`F~are 5.24 Prop~gation dclav versus load capacuancc ( Rd W)
`
`Q\
`
`v,
`
`.----------<"Iv..,.
`
`where Q is the charge stored at the load capacitor. V., is the output voltage.
`and IL is the output current, which is the drain current (I,,) for the CMOS
`case, and is the collector current(/, ) in the BiCMOS case. Although 111 and
`:r. A, .. the bipolar
`l e are geometry-dependent. i.e .. I,, x WI L and le x 11:
`current le in general is much larger than the drain current / 11 of a FET of
`similar size. So. for gates that need to drive a heavy load ( ""0.5 pF). BiCMOS
`is faster for a factor of two or more. For a very small load ( < 0. 1 pF in this
`example). the BiCMOS circuit is actually slower because it takes time to
`charge additional bipolar junction capacitances. ln integrated circuits. a large
`fan-out normally corresponds to a high load capacitance. Compared 10 bi(cid:173)
`polar for the same fan-out, CMOS has a larger load capacitance to drive due
`to the higher input capacitance. As shown m Fig. 5.24. delays for CMOS
`inverters increase as 1.28 ns/pF and this loadmg effect decreases to 0 . .5~ and
`0.36 ns/pF for BiCMOS inverters with two different emitter areas. Notice
`for fan-out greater than 2. the BiCMOS inverters run faster than the CMOS
`inverter.
`Slightly more complex BiCMOS logic such as NAND and NOR gates
`are shown in Fig. 5.25. Again. only two bipolar devices are used m spite of
`the increase in FET counts. With respect to the total device count and c>.tra
`
`81CMOS NAND GA TE
`
`(a}
`
`•·i11ul"P S.ic: Schcmauc, £or (al NAND. and (h) t-:OR ll,CMO~ circu,i-
`
`layout area. the penalty of adding bipolar t.lnwrs on a CMO~ log11: c1rcu1t 1s
`reduced as the CMOS circuit component becomes larger.
`
`5.10.2 Bipolar Device Characteristics
`
`In this section. one-dimensional bipolar device operation is discussed.
`lmponant device characteristics and relevant process parameters are also
`described to provide a background for the discussion of BiCMOS technology.
`Shown in Fig. 5.26 are the cross-sectional view of an 11p11 bipolar tran(cid:173)
`sistor. its corresponding one-dimensional representation and the impurity
`doping distribution.
`It is a three terminal device with a heavily doped 11-
`type emitter that emits current. a lightly doped 11-type collector that collects
`current and a p -type base region. As shown in Fig. 5.26(b}, it is like two
`p-11 junctions connected back-to-back. but the p region is very narrow. Dur(cid:173)
`ing normal operation, the emitter-base p11 junction is forward biased and the
`
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`

`154
`
`v,
`
`CMOS Process Technology
`
`Chap. 5
`
`(()li.<,o,
`
`·,
`
`::; •
`
`.
`
`". pl"9
`
`81 CMOS NOR Gate
`
`(b)
`
`f"11u.., 5.25 Cuntmutd
`
`collector-base junction is reverse biased. A transistor biased under this con(cid:173)
`dition operates in the so-c.illed active region. Under forward bias, the emitter
`current (/ e) is caused by the diffusion of electrons from the 11 + emitter to the
`p-type base (ltvd and the diffusion of holes from the base to the emitter(/ NJ·
`The current components governed by diffusion are
`
`/NE= AEqDnB d11~ldx = A"qD,.8 11~(0)/W11
`
`(5.3a)
`
`Ip£= AEqDp£ dp'E;ldx = A,..qDr,. p~(O)IWF
`h - l,vE + In;
`(5.3c)
`assuming W 8 and W £ are very small so that linear approximation can be
`applied. AE is the emitter area, D,, and D,. are the diffusivitics for electrons
`and holes, n~ and p',; are the excess minority carrier concentrations in the
`base and emitter regions due to injection under forward bias at the emitter-
`
`(5.3b)
`
`·-
`Em ne, \
`
`v.,>o
`
`n
`
`Co1tec10,
`
`,,
`
`)
`
`tb)
`
`Col...:tor
`
`n
`
`-
`
`FigurT S.26 An 11p11 bipolar 1r.in,i\lor f.tl crO\,-,,,:tion uf Jn "I"' 1ran,i,tur. (h)
`One-d1mc~<1nJI rcpr.~n1a11u11 Jn<J (cl l mpunl\ <lupin~ ,Ji,1nhut1un m un~ ,J1.
`rn<n,,un
`
`Greenthread Ex. 2065, p. 10 of 47
`Semiconductor v. Greenthread
`
`

`

`156
`
`CMOS Process Technology
`
`Chap. 5
`
`Sec & 10
`
`B,poler CMOS lntegrallon B,CMOS
`
`157
`
`p'()() Orn' (X)
`
`ncollector
`
`Oepl~tion
`recJiOn
`
`l'l,:11~ S.27 Excessive minorily c"rricr di,1rihu1ion in a onc-<lim~n~ion.,1111111 lr:on•
`sistor.
`
`(5.4a)
`
`(5.4h )
`
`base junction. They are calculated as
`llnu = 11,11,[exp(qV/1£/kT) -
`lln(X) = 11n(x) -
`l] at X = 0
`p;,(x) = pra(x) - Pt:.u =- p~Jcxp(qV ulkT) -
`I I at x = 0
`where 118 and PE are the minority carrier concentrations. 11110 and p,;., are the
`minority concentrations at equilibrium. and V nr is the forward bias emitter(cid:173)
`base voltage. Figure 5.27 shows the distribution of minority concentrations
`in the base and emitter regions. The slopes of the curves correspond to
`current values. The excess electron concentration reaches zero at the base(cid:173)
`collector junction because the junction is reverse biased and the electric field
`in the depletion region across the junction sweeps carriers away. Notice that
`n11(0) is much larger than p~-(0) because p11 = 11; and the majority carrier
`concentration (i.e .. the doping concentration) in the base is much less than
`that in the emitter. As a result,/ rr << IN£· The ratio of the current injected
`into the base to the total emitter current is defined as emitter efficiency (y,)
`and is expressed as
`
`JN£1(/NE + J,d ;o, l - 1,,rllNF
`'Y, -
`= I -
`[Dpp~O)W11)1[WFD,,t1n(O))
`Using Einstein relation (D = ,..kT/q). the above equation can be written as
`(µpp 8 W8 )l(µ,.11FWF) ii! l - R_ff lR\H
`'Y, :: 1 -
`(5.6)
`
`(5.5)
`
`where p,, and 11£ are majority carrier densities in the base and the emitter.
`PsWs is the total majority charge in the base and is called the Gummel
`number. The higher the Gummel number. the lower the emitter efficiency.
`~s£ and R58 are the sheet resistances for both the emitter and base. respec-
`11vely. Because typical values of Rst: and R~H are tens and thousands re(cid:173)
`spectively. -r .. is close to but less than unity.
`Not all injected electrons are collected at the collector. Some of them
`are recombined in the base region and the portion which reaches the collector(cid:173)
`base junction is defined as the base transpon factor (T):
`T = INC = (d119/ dx)_.. IYH
`l.v£
`(d,111/dx)., " 0
`Solving the diffusion equation for 1111 with boundary conditions. the above
`equation can also be shown as.i,'
`T = (CoshW1/L,.8 )
`= l - W~/(2L:;,,) since W,, << L,.11
`where LnH is the diffusion length of minority carrier~ in the h.rsc. L,,11 =
`(D,,T,.)' 1 where T,, is the minority lifetime.
`Because the collector-base junction is reverse biased. the total collector
`current (Id is approximately equal to l.w: assuming the junction leakage
`current is negligible. The common b.rse current gain (or) can then be writt~n
`as
`
`(5.7)
`
`(5.8)
`
`'
`
`OI
`
`J ,·, I \ I
`-/
`/
`
`-
`
`Ty~
`
`it W7, (2L~H))(I
`
`R" R\,,)
`
`(5.9)
`
`- IL
`/
`~
`"
`l:.
`Again. a is typically slightly less than one.
`Based on Eqs. 5.3a and 5.4a. the current driving ability is
`I _
`J _
`C - OI E - a
`•
`
`_ TA1,qD,,11;[exp(qV111;/kT) -
`I
`J
`\'t·'Y -
`• •
`PHWH
`,.
`
`I]
`
`(5 . 10)
`
`The denominator is the Gummcl number. The numerator indicates that the
`current of a bipolar transistor is exponentially dependent on the voltage across
`the emitter-base junction. In reality. because of the IR drop from the base
`contact to the emitter-base junction (Figure 5.26a), the V HE term in the above
`equation should be replaced by V BE -
`lnR,1.
`•
`The le_ versus V8 £ curve is known as the Gummel plot. Figure 5.28
`show~ ex~nmental data for le and 18 versus V8 E plotted linearly and semi·
`loganthm1cally. Notice that the curve in Figure 5.28{b) is steep and a tum(cid:173)
`on voltage at about 0. 7 V can be defined. A larger emitter area, a narrow
`ba_s~ and/~~ a lower base doping concentration can increase bipolar currenl
`dnv1ng ab1l11y. However. a narrow base or a low base doping concentration
`can cause significant base width modulation. an undesirable effect similar to
`
`Greenthread Ex. 2065, p. 11 of 47
`Semiconductor v. Greenthread
`
`

`

`le (A)
`
`lE--02
`
`deude
`idtv
`
`,e-12
`0000
`
`1000
`
`10.00
`Jd,v
`
`IE-02
`
`decade
`idtv
`
`lE-12
`
`l 000
`
`v11 0 l/d1v
`
`(II)
`
`(a)
`
`1.00
`
`I 0
`
`010
`dv
`
`.,,
`
`9
`"'
`
`· -
`
`iVll
`
`O 00 L__.J._ _ _,_ _ _,__ . J _ _ . J _ _ _ _ =..;,.__ _ _._ _ _.____. 0 00
`
`0000
`
`v., O 11d1•
`
`0 7
`
`(Ill
`
`1 000
`
`lb)
`f~ure S.28 Colle<:1or and t>.ll'C current ((, ;,n<l I h) ,wsus hasc-.:miucr ,oltag~
`(V,v) for an np11 transistor: (a) Gummcl plo1 in scm1-loi:ari1hm,c. an<l (h) Gummd
`plot in hncar.
`158
`
`Sec. S.10
`
`BipolarlCMOS lntegration-BiCMOS
`
`159
`
`the short-channel effect in MOSFETs. This base width modulation. known
`as Early effect. leads to increased output conductance for the bipolar tran(cid:173)
`sistor.
`The base doping concentration should be much higher than the collector
`doping concentration so that most of the depletion width extends to the
`collector region to minimize Early effect and 10 mamtam sufficient collector(cid:173)
`base breakdown voltage (BV nw) and collector-emitter breakdown voltage
`(BVa 0 ). However. a lightly doped collector gives a high collector resistance
`(Re). resulting in a reduced current at a given bias condition. A common
`way to accommodate both high breakdown and low collector resistance is to
`use a heavily doped buried layer (Fig. 5.26a) under the lightly doped collector
`region so that Re can be greatly reduced.
`The common emitter current gain (fl) is defined a, fe ll H and equal~
`a /( I - a). Depending on a. !l values range from ten:. to hundreds. The
`higher the a. the higher the fl. From Eq. 5 .9. 11 i:. clear that narrow ha,c
`width. low emitter sheet resistance and lo~ Gummel numher in the base can
`all increase the common emitter current gain. Again. the Gummel number
`cannot be too low due to the limitation in output conductance and hreakdown
`voltages.
`While current gains are important DC parameters. 1ransit time (T,) j,;
`important for high frequency operation. T, is the time needed for the carrier;
`to travel across the base region.
`It can be approximated hy
`
`where u is carrier velocity and ( ) means average value. Because
`
`and
`
`equating Eq. (5. 12) and (5.13).
`(I') - 2D., WH
`
`and
`
`T 1 = wi /2D,,
`
`(5. 11)
`
`(5.12)
`
`{5.13)
`
`(5. 14}
`
`(5. 15)
`
`can be obtained.
`The above derivation. based on the concepts of average velocity and
`average minority carrier concentration. is at best an estimation. T, is also
`the time required to remove all minority carriers from the base when the
`It is interesting 10 note that
`emitter-base voltage ( V 8 r,) switches to zero.
`T,.IT, = jl. The reciprocal or the transit time corresponds to the frequency
`In reality. even before
`limitation for the operation o f a bipolar transistor.
`the operating frequency reaches ll'T,. current gain decreases at high frequen-
`
`Greenthread Ex. 2065, p. 12 of 47
`Semiconductor v. Greenthread
`
`

`

`160
`
`CMOS Process Technology
`
`Chap. 5
`
`Sec. 5. 10
`
`Bipolar/CMOS lnte<;ration-BiCMOS
`
`1&1
`
`cies due to additional RC time constants associated with parasitics. The
`cutoff frequency fr, defined as the frequency at which the common emitter
`current gain is unity. is an important parameter for high frequency operation~.
`fr can be expressed as• 1
`
`and
`
`(5.16)
`
`(5. 17)
`
`where C;£ and C;c are the junction capacitances at emitter and collect~r
`junctions and gm is the transconductance defined as 8/cliJV sc· To obtam
`good high frequency response, the parasitic capacitances and resistances must
`In addition, the intrinsic base transit time must be decreased.
`be reduced.
`Along with the use of the buried layer, a thinner collector layer (small W)
`and/or a heavily doped collector plug under the collector contact can further
`decrease Re (Fig. 5.26a).
`The previous discussion assumes that the carrier concentration injected
`to the base is much less than the majority carrier concentration ( p 8 ) which
`equals the base doping concentration (N,.,8). This assumption is often invalid
`at high current levels in which n8 >> N,18. In such cases, the majority carri~r
`concentration must increase 10 maintain charge neutrality in the base. This
`condition is called conductivity modulation. As a consequence, the effective
`base doping concentration becomes higher. resulting in a smaller emiuer
`efficiency and a reduced current gain. High level injection also occurs al the
`collector and is known as Kirk effect.•! For npn devices. it was assumed that
`minority carriers (electrons) that reached the depletion edge of the reversely
`biased collector-base junction were swept across so that electron density (11)
`in the depletion region was negligible. This assumption is not valid at a high
`current density/(/ .. qnv where 1.1 is electron velocity). Because t' is limited
`by the saturation velocity due 10 scattering. a finite amount of II exists when
`J is large. This electron density /Iv adds to the negatively charged ionized
`acceptors in the depletion region at the base side so that the total charge
`density increases.
`At the collector side, where the depletion region was composed of the
`positively charged ionized donors. the injected electrons decreased the charge
`density and even changed the net charge from positive to negative. In fact.
`the concept of the depiction region is not reflected accurately here due to
`the presence of a large number of carriers. It should be described as a space
`charge region. This modulation of charge density. for a constant collector(cid:173)
`base voltage, must be accompanied by a narrowing of the depletion region
`at the base and a widening of the depletion region at the collector side.
`Consequently, the undepicted (or neutral) base widens. resulting in a reduc(cid:173)
`tion of the current gain at high currents and a poorer frequency response.
`
`5.10.3 BiCMOS Process Technology
`
`BiCMOS technology can be developed in two basic ways: adding bipolar
`on CMOS or adding CMOS on bipolar. Because the discu!>S1on. 1hus far.
`has been concentrated on CMOS technology, the former method will he used
`to build BiCMOS. This method has been used for several recent BiCMOS
`It often compromises bipolar performance to be com•
`developments. H • -'6
`patible with existing CMOS and minimize added process steps. In a BiCMOS
`circuit. vertical np11 transistors are needed because they have higher current
`gain compared to a pnp transistor or a lateral device. Furthermore. each
`bipolar transistor should be isolated so that it is not limited to emitter-follower
`type logic only. N-wells are used in CMOS as the isolated collec1ors for the
`vertical 11p11 transistors. Thus. CMOS with 11-well., or twin-tub on p-substrate..,,
`is commonly extended to BiCMOS.
`Because buried-layer is normally used for 11p11 bipolars to reduce col(cid:173)
`lector resistance. a buried-layer mask is defined and followed by a shallow
`arsenic implant (Fig. 5.29a). A p-type epi layer is then grown and 11-wells
`are formed above the 11 + buried layer (Fig. 5.29b). After the standard CMOS
`LOCOS field isolation. another mask and boron implant arc then needed to
`form the 11p11 base (Fig. 5.29c). Subsequent to standard gate oxidation.
`polysilicon deposition and gate definition. the 11 • mask is used 10 implant
`arsenic for the 11MOS S,D. the 11p11 emitter and 11 • contacts for the collector
`and 11-wells (Fig. 5.29d). Similarly. p • mask is used to implam boron for
`the pMOS SID and base contact. Standard contact and metal masks and
`associated process steps finish the entire BiCMOS process (Fig. 5.29e). No(cid:173)
`tice that Masks I and 4 are the additional masks needed for making bipolar
`on a CMOS chip. With buried-layer. it is necessary to grow an epi layer.
`which is often already included in CMOS for latch-up prevention. Boron
`base implant is yet another extra process step. The entire process consists
`of 9 masks: buried layer. 11-wcll, active area. npn base. poly. 11 •. p •. contact
`and metal. This sequence descnhed the hasic BiCMOS proces:. m which
`MOSFETs are not scaled to mm1mile short-channel effects and 111m bipolar~
`are not high performance devices.
`As discussed in Secs. 5.2 and 5.3. for micron or submicron CMOS.
`additional masks and implants are necessary for FET threshold adjustme