UNITED STATES PATENT AND TRADEMARK OFFICE
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`_________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_________________________
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`SEMICONDUCTOR COMPONENTS INDUSTRIES, INC.,
`Petitioner,
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`v.
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`GREENTHREAD, LLC,
`Patent Owner.
`_________________________
`
`Case IPR2024-00265
`U.S. Patent 9,190,502
`_________________________
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`DECLARATION OF ALEXANDER D. GLEW
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`Semiconductor Components Industries, Inc. v. Greenthread, LLC
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`TABLE OF CONTENTS
`INTRODUCTION ...............................................................................................................1 
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`BACKGROUND AND QUALIFICATIONS .....................................................................3 
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`SCOPE OF ASSIGNMENT AND MATERIALS CONSIDERED ....................................6 
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`LEVEL OF ORDINARY SKILL IN THE ART .................................................................9 
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`RELEVANT LEGAL PRINCIPLES .................................................................................10 
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`A. 
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`B. 
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`C. 
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`Claim Construction ................................................................................................10 
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`Anticipation............................................................................................................12 
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`Obviousness ...........................................................................................................12 
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`THE CHALLENGED PATENTS .....................................................................................14 
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`A. 
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`B. 
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`Background Technology Regarding Dopants ........................................................14 
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`Overview of Challenged Patents ............................................................................14 
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`  OVERVIEW OF ALLEGED PRIOR ART .......................................................................19 
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`A. 
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`Kawagoe ................................................................................................................20 
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`B.  Wieczorek ..............................................................................................................22 
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`C. 
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`Payne ......................................................................................................................26 
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`  CLAIM CONSTRUCTION ...............................................................................................28 
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` 
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`THE CITED REFERENCES DO NOT DISCLOSE OR SUGGEST
`ALL THE FEATURES OF THE CHALLENGED CLAIM .............................................29 
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`A. 
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`B. 
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`C. 
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`Dr. Blalock’s Kawagoe-based analysis is incorrect regarding
`the “aid carrier movement” limitations. .................................................................29 
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`incorrect
`is
`Dr. Blalock’s Wieczorek-based analysis
`regarding the “aid carrier movement” limitations. ................................................35 
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`Dr. Blalock’s Payne-based analysis is incorrect regarding the
`“aid carrier movement…” limitations in IPR2024-00265 and
`-00266. ...................................................................................................................37 
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`CONCLUSION ..................................................................................................................72 
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`Semiconductor Components Industries, Inc. v. Greenthread, LLC
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`I, Alexander D. Glew, declare as follows:
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`
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`INTRODUCTION
` My name is Alexander D. Glew. I have been retained on behalf of
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`Greenthread, LLC (“Greenthread”), and its counsel, McKool Smith, P.C., as an
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`expert with regard to this matter. I understand Semiconductor Components
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`Industries, LLC, d/b/a onsemi (“onsemi” or “Petitioner”) filed Petitions (Paper No.
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`1) for inter partes review (IPR) of:
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` U.S. Patent No. 11,316,014 (“the ’014 patent”);
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` U.S. Patent No. 10,734,481 (“the ’481 patent”);
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` U.S. Patent No. 9,190,502 (“the ’502 patent”); and
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` U.S. Patent No. 8,421,195 (“the ’195 patent”) (collectively, the
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`“Challenged Patents”).
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`I have been asked to consider, and provide my independent analysis and
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`opinions regarding: whether the alleged prior art references cited the following
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`proceedings:
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` IPR2024-00263 relating to Claims 1-2, 4-9, 13-28 of the ’014 Patent;
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` IPR2024-00264 relating to Claims 1-9, 13-27, 31-36 of US Patent
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`10,734,481;
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` IPR2024-00265 relating to Claims 7-12 of US Patent 9,190,502; and
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` IPR2024-00266 relating to Claims 1-6 of US Patent 8,421,195
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`(collectively, the “Challenged Claims”);
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`disclose or suggest the features recited in the Challenged Claims. In my view, the
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`alleged prior art references do neither for each of the ’014, ’481, ’502, ’195 patents.
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`My opinions and conclusions are fully discussed in later sections of this declaration.
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`This declaration is based on the information currently available to me.
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`I am an independent consultant, and I am not, and have never been, an
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`employee of Greenthread or Petitioner. I am being compensated at my consulting
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`rate of $700 per hour for my work related to this matter. I received no compensation
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`for this declaration beyond my normal hourly compensation based on my time
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`actually spent analyzing the Challenged Patents, the prosecution history of the
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`Challenged Patents and related applications, the alleged prior art publications relied
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`upon by Petitioner, the declarations of Petitioner’s expert Dr. Travis Blalock, and
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`other related materials (discussed below in Section III). My compensation is not
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`dependent on the outcome of this IPR or the testimony or opinions that I give.
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`I understand a copy of my curriculum vitae is submitted as EX2067,
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`and it sets forth my educational experience, employment history, and publications.
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` BACKGROUND AND QUALIFICATIONS
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`I earned a B.S. degree in Mechanical Engineering in 1985 and a M.S.
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`degree in Mechanical Engineering in 1987 from the University of California,
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`Berkeley.
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`I earned a M.S. degree in Materials Science and Engineering in 1995
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`and a Ph.D. in Materials Science and Engineering in 2003 from Stanford University.
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`I am the Founder and President of Glew Engineering Consulting, Inc.,
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`based in Mountain View, California. I have been President of Glew Engineering
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`Consulting, Inc. since I started the company in 1997. In my role as President, I have
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`provided consulting services to clients in the field of semiconductor manufacturing
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`and materials, as well as to clients in other fields. I have reviewed and analyzed
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`semiconductor technologies and products. My consulting work has involved
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`semiconductor process equipment, thin film deposition and characterization, process
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`development, project turnaround/rescue, gas flow and vacuum metrology, design of
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`experiments, corrosive gas applications, finite element analysis, and related market
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`analysis.
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`I have over 30 years of experience in semiconductor manufacturing and
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`materials, including in semiconductor equipment and processing. I have
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`implemented numerous manufacturing processes
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`for
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`the
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`formation of
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`semiconductors, including chemical vapor deposition (“CVD”), plasma enhanced
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`chemical vapor deposition (“PECVD”), high density plasma chemical vapor
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`deposition (“HDPCVD”), etch processing (including dry plasma and wet
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`processing), reactive-ion etching (“RIE”), chemical-mechanical planarization
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`(“CMP”), spin-on dielectrics (“SOD”), epitaxy (“EPI”), molecular beam epitaxy
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`(“MBE”), rapid thermal processing (“RTP”), and others.
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`In 1987, before receiving my Ph.D., I worked at Applied Materials, Inc.
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`in Santa Clara, California. At Applied Materials, Inc., I served in a number of roles,
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`including Engineering Manager, Core-Technologist Project Manager, CVD Supplier
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`Quality Engineering Manager, Core Technologist, CVD Engineering Manager, and
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`Systems Engineer. In these roles, I provided engineering services and supervised
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`other employees on projects related to technologies used to manufacture
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`semiconductors, including CVD, epitaxy, physical vapor deposition (“PVD”), rapid
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`thermal processing (“RTP”), etch, and thermal. I oversaw gas, vacuum, and
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`chemical component evaluation, testing, and supplier quality management. I
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`successfully proposed and executed a project to develop industry methods to
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`determine the effects of trace chemicals on semiconductor processing and equipment
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`reliability. I worked on the development and release of the Precision 5000 CVD
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`product, the first cluster tool for semiconductor manufacturing.
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`I have used alpha particles to perform hydrogen forward scattering
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`(HFS) and Rutherford Back Scattering (RBS) in materials analysis of thin films on
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`silicon wafers. I am generally familiar with the effects of alpha particles fired at
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`silicon wafers.
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`I am a licensed professional mechanical engineer in the state of
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`California.
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`I have published articles and presented on topics related to
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`semiconductor manufacturing. My curriculum vitae includes a list of selected
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`publications.
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`I am a co-inventor of five U.S. patents: (a) U.S. Patent No. 6,204,174,
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`directed to a method and apparatus to control the deposition rate of material in a
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`semiconductor fabrication process; (b) U.S. Patent No. 9,224,626 and 10,395,593,
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`directed to a method of forming a heater assembly for use in semiconductor
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`processing; and (c) U.S. Patent Nos. 6,679,476 and 7,118,090, both directed to
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`control valves for use in ultra pure applications such as semiconductor processing.
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`I have another patent application pending.
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`I am a member of the American Society of Mechanical Engineers
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`(“ASME”), International Microelectronics and Packaging Society (“IMAPS”),
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`Materials Research Society (“MRS”), Institute of Electrical and Electronics
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`Engineers (“IEEE”), and Semiconductor Equipment and Materials International
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`(“SEMI”).
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`I am qualified to render an opinion regarding the design and
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`development of semiconductor manufacturing devices and semiconductor materials
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`based on my experience. Based on my expertise and qualifications, I am qualified to
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`provide an opinion as to what a person of ordinary skill in the art would have
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`understood, known, or concluded as of 2004.
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` SCOPE OF ASSIGNMENT AND MATERIALS CONSIDERED
` The opinions contained in this declaration are based on the documents
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`that I reviewed, my professional judgment, as well as my education, experience, and
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`knowledge regarding technologies related to the Challenged Patent. In preparing this
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`Declaration, I am relying on my own knowledge and expertise as well as the
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`following documents:
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` The Challenged Patents;
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` The patents that I understand are in the same family as the Challenged
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`Patents, include each of:
`o U.S. Patent No. 8,421,195 to Dr. G.R. Mohan Rao (“the ’195
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`patent”) (Ex. 2068)
`o U.S. Patent No. 9,190,502 to Dr. G.R. Mohan Rao (“the ’502
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`patent”) (Ex. 2069);
`o U.S. Patent No. 10,510,842 to Dr. G.R. Mohan Rao (“the ’842
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`patent”) (Ex. 2070);
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`o U.S. Patent No. 10,734,481 to Dr. G.R. Mohan Rao (“the ’481
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`patent”) (Ex. 2071);
`o U.S. Patent No. 11,121,222 to Dr. G.R. Mohan Rao (“the ’222
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`patent”) (Ex. 2060)
`o U.S. Patent No. 11,316,014 to Dr. G.R. Mohan Rao (“the ’014
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`patent”) (Ex. 2072);
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` Prosecution histories for the Challenged Patent and the other patents in
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`the same family (listed above), which I understand constitute the
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`exchange of correspondence between the Patent Office and the
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`applicant (Ex. 1002; Exs. 2073-2077);
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` Petitioner’s IPR petitions in Nos. IPR2024-00263 (regarding the ’014
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`patent), IPR2024-00264 (regarding the ’481 patent), and IPR2024-
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`00265 (regarding the ’502 patent), and IPR2024-00266 (regarding the
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`’195 patent);
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` Petitioner’s IPR petitions in Nos. IPR2023-01242 (regarding the ’222
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`patent), IPR2023-01243 (regarding the ’842 patent), and IPR2023-
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`01244 (regarding the ’222 patent);
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` Declaration and transcript of deposition testimony (Ex. 2058) of Dr.
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`Travis Blalock, who I understand is Petitioner’s expert in each of the
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`IPRs (declaration in each IPR is Ex. 1003);
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`7
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` Petitioner’s exhibits 1001-1023, 1025-1038 in each IPR; and
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` Any other references/documents cited within this Declaration.
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`8
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` LEVEL OF ORDINARY SKILL IN THE ART
` Based on my review of the Challenged Patents, the types of problems
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`encountered in the art at and prior to the time of the alleged invention, prior solutions
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`to those problems, the pace with which innovations were made during the relevant
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`time period, the sophistication of the technology, and the educational level of active
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`professionals in the field, I believe that a person of ordinary skill in the art (POSITA),
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`at the time of the alleged invention, would have had at least a Bachelor’s of Science
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`degree in electrical or computer engineering, materials science, chemical
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`engineering, applied physics, or a related field, with emphasis on semiconductor
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`manufacturing, or an equivalent degree, and at least four years of experience in
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`semiconductor design and manufacturing. Additional education in a relevant field or
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`industry experience may compensate for a deficit in one of the other aspects of the
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`requirements stated above.
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` All of my opinions in this declaration are from the perspective of a
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`POSITA, as I have defined it above and during the relevant time frame (e.g., late
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`2004, including the period up to September 3, 2004, which I understand is the earliest
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`claimed priority date of the Challenged Patents). During this time frame, I possessed
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`at least the qualifications of a POSITA, as defined above.
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` RELEVANT LEGAL PRINCIPLES
` For the purposes of this Declaration, I have been informed about certain
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`aspects of the law that are relevant to my analysis and opinions. I have applied these
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`legal principles in rendering my opinions below.
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`A. Claim Construction
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`I understand that the ordinary and customary meaning of a claim term
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`is the meaning that the term would have to a POSITA at the time of the effective
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`filing date of the patent application that matured into the patent-at-issue. For the
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`Challenged Patents, this is September 3, 2004. In the absence of an express intent on
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`the part of the inventor to give a special meaning to the claim terms, the words are
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`presumed to take on the ordinary and customary meanings attributed to them by a
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`POSITA.
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`I understand that it is the use of the words in the context of the written
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`description, and as customarily used by those skilled in the relevant art, that
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`accurately reflects both the ordinary and the customary meaning of the terms in the
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`claims.
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`I understand that the basis for a term’s ordinary and customary meaning
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`may be derived from a variety of sources, including the words of the claims
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`themselves, the remainder of the specification, the prosecution history, and extrinsic
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`evidence concerning relevant scientific principles, the meaning of technical terms,
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`and the state of the art at the time of the invention.
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`I have been instructed that dictionary definitions or definitions from
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`technical references can be used to inform or confirm the ordinary and customary
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`meaning of words found in a claim, but that in construing claim terms, the general
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`meanings gleaned from reference sources, such as dictionaries, must always be
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`compared against the use of the terms in the context of the claim itself, and the
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`intrinsic record must always be consulted to identify which of the different possible
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`dictionary meanings is most consistent with the use of the words by the inventor.
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`I understand that a patent applicant is entitled to be his or her own
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`lexicographer (in other words, provide his or her own meaning to a word or phrase)
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`and may rebut the presumption that claim terms are to be given their plain and
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`ordinary meaning. To do so, the applicant must clearly set forth a definition of the
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`term that is different from its ordinary and customary meaning.
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` Where the applicant provides an explicit definition for a term, that
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`definition will control interpretation of the term as it is used in the claim in which it
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`appears. I understand that the specification can also be relied on for more than just
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`explicit lexicography to determine the meaning of a claim term. For example, I
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`understand that the meaning of a particular claim term may also be determined by
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`implication, that is, according to the usage of the term in the context of the
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`specification.
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`B. Anticipation
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`I understand that under U.S. Patent Law, 35 U.S.C. § 102, a claim is
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`invalid as anticipated if a single prior art reference discloses each and every
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`limitation of the claimed invention.
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`I am informed that a reference is anticipatory if it contains the claim
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`elements in the same order as claimed, regardless of whether the prior art and the
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`claimed invention are directed to achieving the same purpose.
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`I understand that a prior art reference may anticipate a claim without
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`expressly disclosing a feature of the claimed invention if that missing feature is
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`necessarily present, or inherent, in the single anticipating reference.
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`I am informed that inherency requires more than a probability or
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`possibility that a claimed feature is present in the prior art, but rather that the feature
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`or characteristic is a necessary part of the prior art. I also am informed that
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`recognition of the inherency by a POSITA— at the time— is not required.
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`C. Obviousness
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`I understand that under U.S. Patent Law, 35 U.S.C. § 103, a claim is
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`invalid as obvious if the differences sought to be patented and the prior art are such
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`that the subject matter as a whole would have been obvious at the time the invention
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`was made to a person having ordinary skill in the art to which said subject matter
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`pertains.
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`I am informed that an obviousness analysis requires an assessment of
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`the scope and content of the prior art, the differences between the art and the claims
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`at issue, and the level of ordinary skill in the art. I am told that it is against this
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`backdrop that obviousness is assessed.
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`I am informed that a person of ordinary skill in the art (POSITA) is a
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`hypothetical person who is presumed to be aware of all the pertinent prior art. I am
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`also informed that an obviousness analysis may take account of the inferences and
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`creative steps that a POSITA would employ.
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` THE CHALLENGED PATENTS
`A. Background Technology Regarding Dopants
` Silicon is an example of a semiconductor. In its pure form, it is
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`typically an insulator, but it can become an electrical conductor when impurities
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`called “dopants” are added into the silicon crystal. These dopants are often
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`phosphorous or boron atoms that have one more or one less valence electron than a
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`silicon atom. If the dopant has one less valence electron, then it creates what is
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`called a “hole” where there was an electron, which can be thought of as a positive
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`unit of charge. The extra electrons or holes disturb the local charge equilibrium in
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`the silicon and can become mobile in response to electric fields. Thus, the electrons
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`and holes are called “charge carriers.” These dopants can also change the local net
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`electrical charge distribution in the surrounding silicon, influencing the motion of
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`other charge carriers passing by. When the dopant concentration is graded in a
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`particular direction, other charge carriers will move in the gradient direction (or
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`opposite direction) depending on the charge carrier’s polarity. This phenomenon is
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`called “carrier drift.”
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`B. Overview of Challenged Patents
` At the time of invention of the Challenged Patents, most semiconductor
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`devices relied on spatially uniform concentrations of dopants. ’014 Patent, Abstract,
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`1:64-2:11.1 Dr. Rao (the inventor named on the Challenged Patent) recognized,
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`however, that graded concentrations of dopants can be used to improve certain
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`aspects of the performance of transistors and other semiconductor devices. Id.,
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`Abstract, 3:36-47, 4:1-3. The claimed invention is clearly disclosed in, e.g., Figs.
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`5B-5C of the Challenged Patent, and the corresponding parts of the specification.
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` A surface-channel MOSFET is a common type of transistor capable of
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`controlling current flow at or along the surface of the semiconductor substrate. Ex.
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`2059, 27 (“carriers propagate at the semiconductor surface”). Figure 5B shows an
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`NMOS2 transistor that is formed in a p-type surface layer. The transistor comprises
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`(1) a gate; (2) a thin oxide separating the gate from the surface layer; and (3) two
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`doped regions called the source and drain (shaded red). ’014 Patent, 3:44-45
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`(“electrons can be swept from source to drain”), 4:10-11 (“accelerate majority
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`carriers towards the drain”). In Fig. 5B, which is annotated below, the N+ means
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`these regions are heavily doped with an n-type dopant that creates a surplus of
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`1 The Challenged Patents share near identical specifications and figures. I cite
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`primarily to the ’014 Patent, though identical disclosures will be found in the other
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`Challenged Patents.
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`2 MOS stands for “metal oxide semiconductor.”
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`negative carriers (i.e., electrons).3 The specification explains that the NMOS
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`transistor in Fig. 5B can be a surface-channel MOSFET.
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`Id., Fig. 5B (annotated); see also id., 4:9-11. Meanwhile, the p-type silicon between
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`the source and drain (shaded blue) has an abundance of positively charged holes
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`(green circles). When the holes separate the source’s electrons from the drain’s
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`electrons, current cannot flow through the transistor, and the transistor is in an “off”
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`state.
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` When a positive voltage is applied to the gate, an electric field forms in
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`the oxide. This positive electric field repels the “positive” holes downwards, while
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`3 An “N” region or layer has more electrons, and thus a “negative charge.” A “P”
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`layer has more holes, and a “positive charge.” A “+” or “-” means heavily or lightly
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`doped.
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`the negative electrons (red circles) are attracted to move into the blue surface layer.
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`When enough electrons have accumulated in the surface layer below the oxide, they
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`form a conductive channel (as annotated in Figure 5B below) of electrons between
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`the source and the drain, and current can begin to flow through the transistor.
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`’014 Patent, FIG. 5B (annotated). 4 In order to turn the transistor “off,” the positive
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`voltage is removed from the gate and the channel disappears as the holes return to
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`the surface layer.
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` Dr. Rao (the inventor named on the Challenged Patent) recognized that
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`by using graded concentrations of dopants in the well region and a drift layer (shaded
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`pink), it is possible to “pull” carriers from the silicon’s surface. ’014 Patent, Fig. 5B
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`4 Because the channel is formed by electrons with a negative charge, the MOSFET
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`is referred to as an n-channel MOSFET, and the “minority carriers” are holes.
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`(annotated above). In this example, pulling the holes from the surface layer when a
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`positive voltage is applied to the gate, allows the transistor to turn “on” more quickly.
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`This improves the speed and performance of the transistor. ’014 Patent, 3:42-47.
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` OVERVIEW OF ALLEGED PRIOR ART
` Dr. Blalock’s declaration relies on Kawagoe, Wieczorek, and Payne as
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`primary references in the IPRs as follows:
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` IPR2024-00263
`o Ground 1 – Kawagoe
`o Ground 2 – Wieczorek in view of Wolf
`o Ground 3 – Kawagoe in view of Gupta
`o Ground 4 – Wieczorek in view of Wolf and Gupta
`o Ground 5 – Kawagoe in view of Silverbrook
`o Ground 6 – Wieczorek in view of Wolf and Silverbrook
` IPR2024-00264
`o Ground I – Kawagoe
`o Ground 2 – Wieczorek in view of Wolf
`o Ground 3 – Kawagoe in view of Gupta
`o Ground 4 – Wieczorek in view of Wolf and Gupta
`o Ground 5 – Kawagoe in view of Silverbrook
`o Ground 6 – Wieczorek in view of Wolf and Silverbrook
` IPR2024-00265
`o Ground 1 – Payne
`o Ground 2 – Sakai in view of Kawagoe
`o Ground 3 – Payne in view of Wolf
`o Ground 4 – Payne in view of Parillo
`o Ground 5 – Sakai in view of Kawagoe and Silverbrook
` IPR2024-00266
`o Ground 1 – Payne
`o Ground 2 – Sakai in view of Kawagoe
`o Ground 3 – Payne in view of Wolf
`o Ground 4 – Payne in view of Parillo
`o Ground 5 – Sakai in view of Kawagoe and Wolf
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`Below, I provide overviews of relevant portions of Kawagoe, Wieczorek, and
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`Payne.
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`A. Kawagoe
` The Petitions rely on Kawagoe as described above. Below is an
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`overview of pertinent portions of Kawagoe relevant to the present dispute.
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` Kawagoe is a patent that:
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`relates to a process for manufacturing a semiconductor wafer, a
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`semiconductor wafer, a process for manufacturing a semiconductor
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`integrated circuit device, and a semiconductor integrated circuit device
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`and, more particularly, to a technique which is effective if applied to
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`the so-called ‘epitaxial wafer manufacturing process’ for forming an
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`epitaxial layer over the surface of a semiconductor substrate body, an
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`epitaxial wafer, a process for manufacturing a semiconductor integrated
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`circuit device by using the epitaxial wafer, and a semiconductor
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`integrated circuit device.
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`Kawagoe, 1:13-23.
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` Figure 16 of Kawagoe (shown below) is “a section showing an essential
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`portion of a semiconductor integrated circuit device according to” Kawagoe’s fourth
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`embodiment. Id., 14:46-49.
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`Id., FIG. 16.
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` Figure 16 shows, in part, an n-well 6n and a p-well 6p. Kawagoe
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`discloses that in p-well 6p:
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`the impurity concentration of the p-well 6p is given such a gradient that
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`it is gradually lowered in the depthwise direction from the surface of
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`the epitaxial layer 2E, so that the influence to be caused by the carriers
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`(or electrons) due to the α-ray is lowered. Specifically, the electrons
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`produced by the α-ray are attracted to the substrate body 2S by that
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`concentration gradient and prevented from entering the p-well 6p so
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`that the soft errors can be reduced in case the MIS memory of the
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`DRAM or the like is formed in the p-well 6p. The impurity
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`concentration NW in the principal surface of the epitaxial layer 2E of
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`the p-well 6p and the n-well 6n is at about 6×1016 atoms/cm3, so that
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`the impurity concentration of the p-well 6p and the n-well 6n is at
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`5×1015 to 6×1016 atoms/cm3.
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`Id., 16:2-15 (emphasis added). Figure 23 (shown below) “is a section of the
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`essential portion of the semiconductor substrate at the step … of manufacturing the
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`semiconductor integrated circuit device of FIG. 16”:
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`Id., 6:1-4.
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`B. Wieczorek
` The Petitions rely on Wieczorek as described above. Wieczorek is a
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`patent publication that “relates to the field of manufacturing integrated circuits, and,
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`more particularly, to a semiconductor device, such as a field effect transistor, having
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`an improved retrograde dopant profile in a channel region of the transistor element,
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`and a method of manufacturing such a semiconductor device.” Wieczorek, ¶[0002].
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` Much of the Petition’s discussion focuses on Figures 1B and 2B (shown
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`below), which are described in a relatively cursory manner in the background section
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`of Wieczorek. The entirety of Wieczorek’s description of Figure 1B is:
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`FIG. 1b schematically shows the semiconductor device 100 in an
`advanced manufacturing stage. In FIG. 1b, the semiconductor
`device 100 comprises within the P-well structure 110 heavily N-
`doped source and drain regions 131, including lightly doped
`extensions 132. In the N-well structure 120, similarly, heavily P-
`doped source and drain regions 141, including lightly doped
`extensions 142, are provided. A gate insulation layer 135, for
`example, a gate oxide layer, is provided on the entire surface of
`the semiconductor device 100 to separate a gate electrode 134
`from a corresponding channel region 136 and a gate electrode
`144 from the corresponding channel region 146. Spacer elements
`133 are provided at the sidewalls of the gate electrode 134 and
`respective spacer elements 143 are located at the sidewalls of the
`gate electrode 144. Thus, the semiconductor device 100 includes
`an N-channel transistor 130 and a P-channel transistor 140.
`Wieczorek, ¶[0012]; see also id., ¶[0020] (“FIGS. 1a-1b show schematic cross-
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`sectional views of an exemplary conventional semiconductor device at different
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`manufacturing stages.”).
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`Id., FIG. 1B.
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` Figure 2B (shown below) is described in the background section of
`Wieczorek:
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`FIG. 2b shows a corresponding graph with a typical dopant
`profile with respect to the depth of the respective well structure.
`Due to the up-diffusion of the dopant atoms during the heat
`treatment, the initially retrograde profile in the vicinity of the
`surface of the semiconductor device 100, as indicated by
`reference number 200, may have become substantially uniformly
`distri