5 0628 01064435 6
`
`for the VLSI Era
`
`
`
`
`
`Kirkland & Ellis Library
`
`a
`
`AUC
`
`Volume 4 - Deep-Submicron Process Technology
`
`ONSEMI EXHIBIT 1008D, Page1
`
`ONSEMI EXHIBIT 1008D, Page 1
`
`

`

`
`
`SILICON PROCESSING
`
`FOR
`
`THE VLSI ERA
`
`VOLUME4:
`
`DEEP-SUBMICRON
`PROCESS TECHNOLOGY
`
`STANLEY WOLF Ph.D.
`
`LATTICE PRESS
`
`Sunset Beach, California
`
`
`
`ONSEMI EXHIBIT 1008D, Page 2
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`ONSEMI EXHIBIT 1008D, Page 2
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`

`

`DISCLAIMER
`
`This publication is based on sources and information believed to bereliable, but the
`authors and Lattice Press disclaim any warranty orliability based onorrelating to the
`contents of this publication.
`
`Published by:
`
`LATTICE PRESS
`Post Office Box 340
`Sunset Beach, California 90742, U.S.A.
`
`Cover design by: S.C. Ross Wolf.
`
`Copyright © 2002 by Lattice Press,
`All rights reserved, No part of this book may be reproducedortransmitted in any form
`or by any means, electronic or mechanical, including photocopying, recording or by any
`information storage and retrieval system without written permission from the publisher,
`except for the inclusion of brief quotations in a review.
`
`PRINTED IN THE UNITED STATES OF AMERICA
`
`Library of Congress Cataloging in Publication Data
`Wolf, Stanley
`
`Silicon Processing for the VLSI Era
`Volume 4: Deep-Submicron Process Technology
`
`Includes Index
`
`1. Integrated circuits-Very large scale
`integration. 2. Silicon.
`I.Title
`
`ISBN 0-9616721-7-X
`
`987654321
`
`ONSEMI EXHIBIT 1008D, Page 3
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`ONSEMI EXHIBIT 1008D, Page 3
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`

`

`
`
`DETAILED TABLE OF CONTENTS
`
`PREFACE
`
`Chap. 1 - THE EVOLUTION OF THE STRUCTURE OF MOSFETS
`1.1 THE STRUCTURE OF DEEP-SUBMICRON MOSFETS:
`
`4
`
`(0.25-um to 0.13-4m) - COMPARED TO THE STRUCTURE OF
`“CONVENTIONAL” MOSFETS(2.0-um to 0.5-um)=2
`1.1.1 Evolution of the MOSFET Gate Stack and Contact Structure
`
`1.1.2 Gate Dielectric Materials in Deep-Submicron MOSFETs
`1.1.3 Doping-Concentration Profiles of the MOSFET Channel
`1.1.4 Evolution of the Drain Structure of MOSFETs
`
`1.2 DEEP-SUBMICRON CMOS STRUCTURES_10
`
`1,2.1 Substrate Issues for Deep-Submicron CMOS
`1.2.2 Well Formation in Deep-Submicron CMOS
`1.2.3 Dual-Doped Poly in Deep-Submicron CMOS
`1,2.4 Shallow Trench Isolation for Deep-Submicron CMOS
`1.2.5 Silicon-On-Insulator (SOT) Technology
`1.3 LIMITS TO CONVENTIONAL MOSFET SCALING=15
`
`REFERENCES
`
`16
`
`Chap. 2 - 300-IMM SILICON WAFERS
`
`17
`
`2.1 300-mm SILICON CRYSTAL GROWTH_17
`2.2 GROWN-IN SILICON DEFECTS:
`21
`
`CRYSTAL-ORIGINATED-PARTICLES (COPS) & DISLOCATION LOOPS
`2.3 DETAILS OF THE FORMATION OF
`
`23
`CRYSTAL-ORIGINATED-PARTICLES (COPS)
`2.3.1 The Radial Distribution of Grown-In Defects on the Wafer Surface
`
`2.4 THE OXYGEN-STACKING-FAULTRING (OSF-RING)
`2.5 MITIGATING EFFECTS OF COPS
`27
`BY USE OF POST-CRYSTAL-GROWTH ANNEALING
`2,6 ELIMINATION OF COPS WITH “PERFECT-SILICON”=29
`
`26
`
`vii
`
`
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`
`
`
`
`viii
`
`CONTENTS
`
`2.9.3.1 “Magic DeNuded Zone”
`2.10 FROM INGOT TO FINISHED WAFER:
`
`2.9.1 Epitaxy-Optimized Substrate (EOS) Wafers
`2.9.2 Comparing the Grown-In Defect Characteristics of the “New” Wafers
`2.9.3 Gettering Methods & Denuded Zone Formation Techniques Used
`with the “New” Wafers
`
`2.7 MINIMIZING PERFORMANCE-DEGRADATION CAUSED BY COPS
`
`THROUGHTHE USE OF HIGH-PULL-SPEED SILICON
`30
`
`
`2.8 GETTERING FOR ULSI PROCESSES=32
`
`
`2.8.1 Basic Gettering Principles
`2.8.2 Extrinsic Gettering
`
`
`2.8.3 Intrinsic Gettering
`
`
`2.8.4 Gettering with Oxygen Precipitates
`
`
`2.8.5 Summaryof Gettering
`
`
`2.9 STATUS OF SILICON WAFER TECHNOLOGY & FUTURE TRENDS=45
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`SLICING, ETCHING, AND POLISHING=52
`
`
`2.10.1 Ingot Evaluation
`2.10.2 Ingot Surface Grinding
`
`
`2.10.3 Grinding Flats or Notches on the Ingot for Orientation Purposes
`
`
`2.10.4 Sawing the Ingot into Slices (Wafers)
`
`
`2.10.5 Laser Marking the Wafers
`
`
`2.10.6 Lapping and Grinding the Wafers
`
`
`2.10.7 Removal of Surface Mechanical Damage by Chemical Etching
`
`
`2.20.8 Rounding the Wafer Edge (and Notch)
`
`
`2.10.9 Edge Polishing of the Wafers
`
`
`2.10.10 Chemical-Mechanical Polishing of the Wafers
`
`
`2.10.11 Cleaning the Wafers
`
`
`2.10.12 Depositing Epitaxial Silicon Layers on the Wafers
`
`
`
`
`2.10.13 Shipping 300-mm Wafers: Its Impact on the Evolution of Wafer
`Shipping Boxes
` 63
`2.11 SPECIFICATIONS OF SILICON WAFERSFOR VLSI
`
`
`2.12 THE ECONOMICS OF SILICON WAFERS
`66
`
`
`REFERENCES
`69
`Chap. 3 - GATE DIELECTRICS: THIN GATE OXIDES
`75
`
`
`
`
`
`
`
`
`3.1 REQUIRED CHARACTERISTICS OF GATE DIELECTRICS FOR
`DEEP-SUBMICRON MOSFETS
`76
`
`
`3.2 THE STRUCTURE OF THERMALLY GROWNSi0,
`AND THE PROPERTIES OF THE Si/SiO, INTERFACE
`
`
`80
`
`
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`
`
`
`
`CONTENTS
`
`DPS
`
`3.2.1 The Microscopic Structure of Thermally Grown SiO
`3.2.2 The Si/SiO3 Interface
`3.2.2.1 Interface Trap Charge
`3.2.2.2 Effect of Interface Traps on IC Characteristics
`3.2.2.3 Oxide Trapped Charge
`3.2.2.3 Effect of Oxide Trapped Charge on Device Characteristics
`3.3 DIELECTRIC BREAKDOWNIN SILICON DIOXIDE FILMS
`
`~—-90
`
`IDS
`
`45
`
`/afers
`
`3.3.1 Electron Trapping in Silicon Dioxide:
`3.3.2 The Electric-Field Driven Model of Oxide Degradation (EF Model)
`3.3.3 The Current-Driven Model of Oxide Degradation (1/E Model)
`3.3.4 The Hole-Trapping Model that Describes How Holesare Injected &
`Trapped in SiO,
`3.3.5 Comparing the Electric-Field Driven and Current Driven Oxide
`Breakdown Models
`3.3.6 Time to Breakdown (Typ) and Charge to Breakdown (Qpp)
`3.4 LEAKAGE CURRENTSIN Si0, FILMS (TUNNELING PHENOMENA)
`3.4.1 Fowler-Nordheim (FN) Tunneling (Tunneling Into Silicon Dioxide)
`3.4.2 Direct Tunneling (Tunneling Through Silicon Dioxide)
`3.5 MODELS OF THIN OXIDE GROWTH—104
`
`99
`
`3.6 SINGLE-WAFER TECHNOLOGY OF THIN OXIDE GROWTH_109
`
`3.6.1 Rapid Thermal Oxidation Tools
`3.6.2 Wet RTO Processes
`
`3.7 NITRIDED & FLUORINATED OXIDES AS GATE DIELECTRICS
`
`=-112
`
`3.7.1 Oxynitridation of Silicon in N40
`3.7.2 Oxynitridation of Oxides in N..O or NO
`3.7.3 Fluorinated Gate Oxides
`3.8 PROJECTIONS OF THICKNESS LIMITS OF GATE OXIDES
`
`121
`
`of Wafer
`
`3.8.1 Minimum Oxide Thickness Due to Defects and Tunneling
`3.8.2 Minimum Oxide Thickness: Stress Induced Leakage Current (SILC)
`3.8.3 Soft-Breakdown of Oxide Films
`3.8.4 Impact of Polysilicon Depletion
`3.8.5 Impact of Process Induced Damage
`3.8.6 Summary of Oxide Thickness Projections
`3.9 MEASURING THIN GATE OXIDES=135
`13
`
`3.10 MANUFACTURING THIN GATE OXIDES
`
`137
`
`3.10.1 Process Control Issues of Growing Ultra-Thin Gate Oxides
`3.10.2 Thin Gate Dielectric Stacks Based on Silicon Dioxide
`
`
` REFERENCES=139
`
`
`
`ONSEMI EXHIBIT 1008D, Page 6
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`

`

`
`
`x
`
`CONTENTS
`
`Chap. 4 - HIGH-A DIELECTRICS
`
`145
`
`4.1 HIGH-k DIELECTRICS AS THE GATE DIELECTRIC IN MOSFETS
`
`145
`
`4.1.1 Integrating High-k Dielectrics into MOSFETStructures:
`4.2 HIGH-k DIELECTRICS AS THE CAPACITOR DIELECTRIC IN DRAMS
`
`150
`
`4.3 HIGH-k DIELECTRICS FOR FeRAM APPLICATONS
`
`154
`
`5.3.2 MOSFETswith Elevated Source/Drains
`
`4.6.1 Atomic Layer Deposition for Depositing Thin High-k Dielectric Films
`4.6.2 Aluminum Oxide (Al,0,) as a Gate Dielectric
`4.6.3 Zirconium Oxide (ZrO.) as a Gate Dielectric
`4.6.4 Hafnium Oxide (HfO,) as a Gate Dielectric
`4.6.5 Praseodymium Oxide (Pr,O3) as a High-k Gate Dielectric
`REFERENCES
`177
`
`154
`4,4 TANTALUM PENTOXIDE (Ta305)
`4.4.1 Tantalum Pentoxide as a DRAM Capacitor Dielectric
`4.4.2 Tantalum Pentoxide as a MOSFET Gate Dielectric
`
`4.5 BARIUM STRONTIUM TITANATE (BST)
`AS A DRAM CAPACITOR DIELECTRIC
`
`162
`
`4.5.1 Deposition of BST Films by CVD
`4.5.2 Microstructure Effects on the Electrical Properties of BST
`4.5.3 BSTIntegration Issues
`4,6 USE OF OTHER HIGH-k MATERIALS AS GATE DIELECTRICS
`
`169
`
`Chan. 5 - THE STRUCTURE OF DEEP-SUBMICRON MOSFETS:
`Retrograde-Wells; Super-Sieep Retrograde Channel Doping; Drain
`Engineering; Punchthrough-Contral Implants
`
`5.1 WELL-FORMATIONIN DEEP-SUBMICRON CMOS
`
`181
`
`5.1.1 Retrograde-Wells for Deep Submicron CMOS
`5.1.2 Process Integration Issues Involving the Use of Retrograde-Wells
`5.2 SUPERSTEEP RETROGRADE CHANNEL(SSR) PROFILES
`191
`5.2.1 Fabricating SSR Profiles for Sub-0.1 mm MOSFETs
`5.3 SOURCE/DRAIN ENGINEERING IN DEEP-SUBMICRON CMOS
`
`195
`
`5.3.1 Parasitic Resistance of Deep-Submicron Source/Drains
`5.3.1.1 Physical Meaning of R,., Rep: and Repg
`5.3.1.2 Comparing the Resistance ofthe SDE Region (Rp + Reng) to Rea
`5.3.1.3 Parasitic Resistance of the Deep Contact Region of the Drain R,,
`
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`145
`
`145
`
`wa
`
`2AMS
`
`150
`
`CONTENTS
`
`xi
`
`5.3.2 MOSFETswith Elevated Source/Drains
`5.3.3 Shallow-Junction Formation for Deep-Submicron Source/Drains
`5.3.3.1 Ultra-Low-Energy Implants
`5.3.3.2 Transient-Enhanced Diffusion
`5.3.3.3 Rapid Thermal Annealing of Shallow Junctions
`5.3.3.4 Dopant Loss for Sub-keV Implants from Self-Sputtering, Out Diffusion,
`and Surface Oxide
`
`5.3.4 Effect of the Overlap of the SDE Region and Gate Edge on
`MOSFETPerformance
`
`5.3.5 SDE Junction Lateral Abruptness
`5.4 ANTI-PUNCHTHROUGH STRUCTURES IN
`DEEP-SUBMICRON CMOS
`
`219
`
`_ 169
`‘ilms
`
`181
`
`1
`
`195
`
`Chap. 6 - ADVANCED LITHOGRAPHY |: DEEP-SUBMICRON RESISTS
`6.1 CHEMICALLY-AMPLIFIED DEEP-UV RESISTS
`227
`FOR OPTICAL LITHOGRAPHY
`6.1.1 248-nm Photoresists
`6.1.1.1 Amine-Contamination of DUV CA Resists
`
`227
`
`6.1.1.2 Current State of 248-nm Resist Technology
`6.1.2 193-nm DUV Photoresists
`6.1.2.1 Problems of 193-nm Resists
`6.1.3 157-nm DUV Photoresists
`6.2 ANTI-REFLECTIVE COATING (ARCs)
`6.2.1 Organic BARCs
`6.2.2 Inorganic Dielectric BARCs
`6.2.3 PVD-Deposited BARCs
`6.2.4 BARCs for Dual-Damascene Applications
`6.3 PHOTORESIST PROCESSING SYSTEMS
`
`244
`
`251
`
`REFERENCES
`257
`Chap. 7 - ADVANCED LITHOGRAPHY fl: OPTICS AND HARDWARE
`7.1 EXCIMER LASER DEEP-UV LIGHT SOURCES
`259
`7.1.1 KrF Excimer Lasers
`7.1.2 ArF Excimer Lasers
`7.1.3 Fy Excimer Lasers
`7.2 EXPOSURE TOOLS For DUV LITHOGRAPHY
`
`265
`
`7.2.1 Exposure Tools for 248-nm Lithography
`
`259
`
`REFERENCES=223
`
`i
`
`
`
`
`
`ONSEMI EXHIBIT 1008D, Page 8
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`
`
`CONTENTS
`
`7.2.2 Exposure Tools for 193-nm Lithography
`7.2.3 Exposure Tools for 157-nm Lithography
`7.2.4 Calcium Fluoride Optical Elements for DUV Lithography
`7.2.5 300-mm Lithography Tools
`7.2.6 Mix-an-Match Lithography
`7.3 RESOLUTION ENHANCEMENT TECHNOLOGIES (RETs)=274
`7.3.1 Off-Axis Illumination
`
`7.3.2 Optical Proximity Correction (OPC)
`7.3.3 Phase Shift Masks (PSM)
`7.4 MASK ERROR FACTOR (MEF, or MEEF)—-292
`7.5 EXTENDING THE LIMITS OF OPTICAL LITHOGRAPHY=296
`
`8.3.6 Efficiency of Planarization (EOP)
`
`8.1.3 Design Rules Related to Intermetal Dielectric-Formatien
`and Planarization Processes
`8.1.4 Step-Height Reduction of Underlying Topography
`as a Technique to Alleviate the
`Needfor Planarization
`8.1.5 Planarization through Sacrificial-Layer Etchback
`8.1.5.1 Sacrificial-Etchback Process Problems
`
`7.6 NON-OPTICAL (or NEXT GENERATION)
`301
`LITHOGRAPHIC TECHNOLOGIES (NGL)
`7.6.1 Extreme Ultra-Violet Reflective Projection Lithography (EUV)
`7.6.2 Electron Beam Projection Lithography (SCALPEL and PREVAIL)
`
`REFERENCES
`
`309
`
`Chap. 8- CHEMICAL MECHANICAL POLISHING (CMP)
`
`8.1 TERMINOLOGY AND EVOLUTION OF
`PLANARIZATION PROCESSES FORICS=313
`
`8.1.1 Defining the Degree of Planarization
`8.1.2 The Need for Dielectric Planarization:
`
`8.2 INTRODUCTION TO CHEMICAL MECHANICAL POLISHING (CMP)
`8.3 THE TERMINOLOGY USED TO CHARACTERIZE CMP PROCESSES
`
`8.3.1 CMP Removal Rate (RR)
`8.3.2 The Degree of Planarization (DOP)
`8.3.3 Within-Die Non-Uniformity (WIDNU)
`8.3.4 Within-Wafer Non-Uniformity(WIWNU)
`8.3.5 Wafer-to-Wafer Non-Uniformity (WIWNU)
`
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`CONTENTS
`
`xii
`
`8.5.1 The Mechanical Aspects of Silicon Dioxide Removal by CMP:
`(Preston’s Law)
`8.5.1.1 Model of WIWNU Effects in Rotary CMP Tools Based on Preston’s Law
`8.5.2 Models Which Describe Factors that Impact Oxide RR in CMP
`Through the Preston Constant
`8.5.2.1 Impact on the Oxide RR fromthe Electrochemical Interactions Between
`the Slurry Particles and the Oxide Surface
`8.5.2.2 Dependence of Oxide RR in CMP on Dielectric Hardness
`8.5.3 Models Which Describe Chemical-Mechanical Phenomenathat
`Give Rise to Planarization Phenomena Associated with CMP of Oxides
`8.5.3.1 Model of the Mechanism That Produces Planarization of
`
`Steps in Oxide CMP
`8.5.3.2 Pattern Dependenceof the Planarization Rate in CMP Processes
`8.5.4 Metal-CMP Mechanisms
`8.6 CMP EQUIPMENT
`352
`8.6.1 CMPPolishing Tools:
`8.6.1.1 CMP Polishing Tool Configurations
`8.6,1.2 Rotary CMP Tools:
`8.6.1.3 Orbital CMP Tools
`8.6.1.4 Linear CMP Tools
`8.6.1.5 Fixed Table CMP Tools
`8.6.1.6 300-mm CMP Tools
`
`t
`
`L)
`
`313
`
`*
`
`|
`
`
`
`8.6.2 Wafer-Carriers in CMP Polishing Tools (and the CMP Edge Effect)
`8.6.2.1 CMP Edge-Effect
`8.6.3 CMP Consumables (Slurries):
`8.6.3.1 Slurries for Oxide-CMP
`8.6.3.2 Slurries for Metal-CMP
`8.6.3.3 Multi-Step Slurries
`8.6.4 Slurry-Distribution Systems
`8.6.5 Environmental, Safety, and Handling Issues of CMPSlutries
`8.6.6 CMP Consumables (Polishing-Pads)
`8.6.7 Pad-Conditioners
`
`SMP)=322 8.6.8 Slurry-Free Pads
`ISBS
`325
`8.6.9 Endpoint-Detection in CMP
`8.7 CLEANING ISSUES INCMP=392.
`8.7.1 Mechanismsof Particle Adhesion and Removal from Surfaces
`
`8.7.1.1 Electrical Repulsion of the Particle and the Wafer Surface
`8.7.1.2 Chemically Assisted Particle Removal
`8.7.1.3 Mechanically Assisted Particle Removal
`8.7.1.4 Steric Stabilization for Suspending Particles in a Solution
`
`
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`xiv
`
`CONTENTS
`
`8.10 CMP SYSTEMS AND PROCESS INTEGRATION=412
`8.11 CMP OF VARIOUS MATERIALS=413
`
`8.9 CMP POLISHER TOOL RELIABILITY
`
`411
`
`8.11.1 CMP of Oxide Interlevel & Intermetal Dielectrics TLDs & IMDs)
`8.11.2 CMP of Tungsten
`8.11.3 CMP of Copper
`8.11.4 CMP of Aluminum
`8.11.5 CMP ofPolysilicon
`8.11.6 CMP of Photoresist
`8.11.7 CMP of Low-k Dielectrics
`
`8.12 MISCELLANEOUS ISSUES CMP
`
`421
`
`8.12.1 Dishing and Erosion
`8.12.2 Thickness Non-Uniformity Within a Wafer After CMP
`REFERENCES
`428
`
`8.7.2 Practical Particle Removal Processes: Brush Scrubbing
`8.7.2.1 Brush Scrubbing to Remove Particles in Post-Oxide-CMPProcesses
`8.7.2.2 Brush Scrubbing to RemoveParticles in Post Metal-CMP Processes
`8.7.3 Vibrational Scrubbing to Remove Particles (Megasonic)
`8.7.4 Secondary (or Buff) Polish Procedure as a CMP Cleaning Step
`8.7.5 Post-CMP Cleaning of Metallic Contaminants
`8.7.6 CMP Cleaning Equipment
`8.8 CMP METROLOGY
`407
`8.8.1 Detection of Defects Associated with the CMP Process
`
`472
`
`Chap. 9 - SHALLOW TRENCH ISOLATION (STI)
`9.1 EARLY SHALLOW TRENCH ISOLATION STRUCTURES
`9.2 STI-ENABLING PROCESSES
`438
`9.3 SHALLOW TRENCH ISOLATION FOR CMOS—s439
`9.4 DETAILS OF THE PROCESS FLOW TO FORM A
`
`435
`
`BASELINE SHALLOW-TRENCH-ISOLATION(STI) STRUCTURE
`9.5 ISSUES INVOLVED WITH STI PROCESS INTEGRATION
`455
`
`446
`
`9.5.1 Issues Involved With Etching Trenches for STI
`9.5.2 Corner-Rounding Techniques in STI Structures
`9.5.3 Trench-Fill Dielectrics for STI
`9.5.4 Dishing Problem Associated with the CMP of STI Trench Dielectrics.
`9.5.5 Corner Engineering and Its Effects on MOSFET TURN-OFF
`Characteristics of MOSFETsFabricated with STI
`
`REFERENCES
`
`ONSEMI EXHIBIT 1008D, Page 11
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`es
`
`CONTENTS
`
`Chap. 10 - SILICON-GERMANIUM (Si-Ge) TECHNOLOGY
`FOR HIGH-PERFORMANCE TELECOMMUNICATIONS ICs
`
`xv
`
`475
`
`10.1 INTRODUCTION TO HETEROJUNCTION BIPOLAR TRANSISTORS—475
`10.2 HETEROJUNCTION BIPOLAR TRANSISTORS WITH
`LARGE-BANDGAP EMITTERS
`10.3 HETEROJUNCTION BIPOLAR TRANSISTORS WITH
`
`480
`
`SMALLER BANDGAP BASE REGIONS(Si-Ge BASE)=482
`10.4 PROCESS TECHNOLOGY FOR FABRICATING SI-GEHBTS=484
`10.5 PROCESS INTEGRATIONISSUES
`FOR BiCMOS TECHNOLOGYWITH Si-Ge HBT=486
`
`10.6 HIGH-QUALITY SI-GE EPITAXIAL FILM GROWTH
`49]
`ON PATTERNED WAFERS
`s) 10.7 THERMAL STABILITY PROCESS INTEGRATION ISSUES=492
`
`10.8 COMPATIBILITY WITH ION IMPLANTATION PROCESSES=492
`10.9 COMPATIBILITY WITH THERMAL OXIDATION PROCESSES=493
`
`10.10 VERTICAL SCALING OF Si:Ge HBTS 493
`10.11 BASE-DURING-GATE AND BASE-AFTER-GATE
`BiCMOS PROCESS FLOWS
`10.12 EXAMPLES OF THE MODULAR INTEGRATION OF
`Si-Ge HBTS INTO A BiCMOS PROCESS FLOW
`
`495
`
`497
`
`REFERENCES
`
`499
`
`
`
`433
`
`‘KB
`
`446
`
`:
`:
`
`501
`
`505
`
`Chap.11 - SILICON-ON-INSULATOR (SOI) TECHNOLOGY
`11.1 WHAT IS SILICON-ON-INSULATOR (SOD?
`501
`11.1.1 Isolation Issues in CMOSin Bulk Silicon
`11.1.2 Isolation in SOI CMOS
`11.2 THE “END OF THE ROAD FOR BULK CMOS” SCENARIO
`PREDICTED BY THE 1999 INTERNATIONAL TECHNOLOGY
`ROADMAP FOR SEMICONDUCTORS
`11.2.1 Source/Drain Junction Scaling
`11.2.2 DopantActivation in Shallow Source/Drain Junctions
`11.2.3 Doping Profile Abruptness in Shallow Source/Drain Junctions
`11.3 WHY SOI?
`510
`11.3.1 The Path of Using SOI May Allow Extension of the ITRS Roadmap
`sctrics.
`11.4 HISTORY OF SILICON-ON-INSULATOR (SOD TECHNOLOGY=516
`11.5 SILICON-ON-INSULATOR DEVICES=518
`
`:
`
`:
`
`11.5.1 Partially-Depleted Thin SOI MOSFETs (PD-SOIs)
`
`
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`ONSEMI EXHIBIT 1008D, Page 12
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`ONSEMI EXHIBIT 1008D, Page 12
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`

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`
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`
`
`xvi
`
`
`CONTENTS
`
`11.5.2 Fully-Depleted Thin SO] MOSFETs (FD-SOIs)
`11.5.3 Process Technologies Used to Fabricate Fully-Depleted SOI Devices
`11.5.3.1 FD-SOLThinning Si-SOI Surface Layer by Thermal Oxidation
`11.5.3.2 FD-SOI Fabrication by LOCOS Recess of the MOSFET Channel Region
`11.6 FABRICATION TECHNOLOGIES USED TO PRODUCESOI-
`STARTING-WAFERS
`
`527
`
`11.6.1 Silicon-on-Sapphire (SOS)
`11.6.2 SOI by Separation by Implanted Oxygen (SIMOX)
`11.6.2.1 High-Dose SIMOX
`11.6.2.2 Low-Dose SIMOX
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`11.6.3 Wafer Bonding
`11.6.3.1 Bond and Etch-back SOI (BESOD
`11.6.3.2 Hydrogen-Implantation-Induced Layer Splitting to Create SOI Substrates
`(SMART-CUT™)
`11.6.3.3 NANOCLEAVE® Wafer Bonding SOI
`11.6.3.4 ELTRAN® Wafer Bonded SOI
`11.7 LATERAL ISOLATION IN SOI
`550
`
`
`
`
`11.8 SOI PRODUCT EVOLUTION
`556
`
`
`11,9 PROBLEMS ASSOCIATED WITH SOI=559
`11.9.1 Floating Body Effects in Partially-Depleted SO] MOSFETs
`11,9.1.1 Kink Effect in Partially Depleted SOI NMOSFETs
`11.9.1.2 Transicnt I Effects
`11.9.1,3 Effect of Building Partially Depleted SOI MOSFETs Without
`Body Contacts
`11.9.2 Short-Channel Effects in SOI MOSFETs
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`11.9.3 Self-Heating Effects in SOJ MOSFETs
`11.9.4 Reliability Issues of SOT
`REFERENCES
`568
`
`
`
`Chap. 12 - MULTILEVEL INTERCONNECTS FOR ULSI
`
`12.1 EVOLUTION OF THE STRUCTURE AND MATERIALS
`
`USED IN IC INTERCONNECTS
`
`
`
`
`
`
`
`
`
`575
`
`12.1.1 Single-Level Metal Interconnects in Early ICs
`12.1.2 Double-Level Metal Interconnects in Early Bipolar ICs
`12.1.3 Double-Level Metal Interconnects in CMOS ICs
`
`(Partial Planarization of the [LD)
`12.1.4 Three-Level Metal Interconnects in CMOS ICs
`(CMPof the ILD & W-Plugs)
`12.1.4,1 Problems of W-plug/Al-line Interconnect Structures
`12.1.5 Dual Damascene Cu/Low-k Interconnects
`
`
`
`
`
`
`
`
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`ONSEMI EXHIBIT 1008D, Page 13
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`

`

`12.1.6 Other Geometrical Aspects of Multilevel ULSI Interconnects
`12.2 PERFORMANCE REQUIREMENTS
`‘vices
`OF ULSI INTERCONNECT SYSTEMS=586
`Region
`
`CONTENTS
`
`xvil
`
`527
`
`Substrates
`
`®
`
`12.2.1 Propagation Delays in ULSI Multilevel Interconnects
`12.2.1.1 Case When the &-Value of the ILD is Constant Throughout
`the Interconnect System
`12.2.1.2 Case When the k-Values of the Interlevel and
`Intralevel ILD are Different
`
`12,2.1.3 Minimizing the RC Delay in the Local Interconnect Region
`12,2.1.4 Minimizing the RC Delay in the Global Interconnect Regions
`12.2.2 Power Dissipation Issues in ULSI Interconnects
`12.2.3 Crosstalk in ULSI Interconnects
`12.2.4 Contact Resistance in ULSI Interconnects
`
`12.2.5 Electrostatic Discharge Protection Issues of Interconnects
`12.3 SUMMARYOF USLI INTERCONNECTISSUES
`AND FUTURE TRENDS
`
`599
`
`REFERENCES
`601
`Chap. 13 - POLYCIDES AND SALICIDES OF TISi,, CoSi, AND NiSi
`13.1 POLYCIDES AND SALICIDES
`603
`
`603
`
`605
`13.2 POLYCIDES FABRICATED BY CVD OF TUNGSTENSILICIDE (WSix)
`13.3 SALICIDE (SELF-ALIGNED SILICIDE) STRUCTURES—608
`13.4 THE EFFECTS OF SALICIDES ON MOSFET PERFORMANCE~612
`
`573
`
`614
`13.5 SALICIDES FORMED WITH TITANIUM SILICIDE(TiSi.)
`13.5.1 Reaction Kinetics of TiSi, Formation (and the Problem of Bridging)
`13.5.2 The TiSi, Narrow-Line Effect
`13.5.3 Proposed Process Modifications to Mitigate the TiSi, Narrow-Line Effect
`13.5.4 Junction Dopant Redistribution and Silicon Consumption
`During TiSi, Formation
`13.6 SALICIDES FORMED WITH COBALTSILICIDE (CoSi,)
`13.6.1 Advantages and Drawbacks of Cobalt Salicides
`13.6.2 Details of the Cobalt Salicide Fabrication Process
`13.6.3 Diode Leakage Issues Involving Cobalt Salicides
`13.6.4 Sensitivity of Cobalt Salicide Films to Degradation by Oxygen Ambients:
`TiN Capping of Cobalt Salicide Films
`13.7 EPITAXIAL CoSi,
`630
`631
`13.8 CoSi, AS A SOURCE/DRAIN DIFFUSION SOURCE
`634
`13.9 NICKEL SILICIDE FILMS FOR SALICIDE APPLICATIONS
`REFERENCES=635
`
`624
`
`
`
`ONSEMI EXHIBIT 1008D, Page 14
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`ONSEMI EXHIBIT 1008D, Page 14
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`

`

`
`
`xviii
`
`CONTENTS
`
`Chap. 14 - LOW-A DIELECTRICS
`14.1 INTRODUCTION TO LOW-k DIELECTRICS
`
`635
`
`14.1.1 Spin-On versus CVD Methods for Forming Low-k Dielectrics
`14.1.2 Silicon-Based versus Carbon-Based Low-k Dielectrics
`14.1.3 Status of Low-k Dielectrics in 2000
`14.2 DESIRED CHARACTERISTICS OF LOW-k DIELECTRIC FILMS
`
`646
`
`14.3 GENERAL PROCESS INTEGRATIONISSUES INVOLVING
`LOW-& FILMS
`
`648
`
`650
`
`14.4 FIRST GENERATION LOW-k& DIELECTRICS(2.8 < k < 3.5)
`14.4.1 Hydrogen Silsesquioxanes (HSQ)
`14.4.2 Spin-On Methyl Silsesquioxanes (MSQ)
`14.4.3 Fluorinated Silicate Glass (FSG) Films
`14.5 SECOND-GENERATION LOW-k DIELECTRICS(2.5 <k <2.8)
`14,5,1 2"-Genereation Spin-On-Dielectrics: (2.5 < k < 2.8)
`14.5.2 2™-Generation CVD-Dielectrics: (2.5<k <2.8)
`14.5,2.1 2" Generation Low-k CVD-Films: Organo-Silicate Glasses
`14.5.2.2 2"! Generation Low-k CVD-Films: FlowFill CVD Films
`14.5.2.3 2"! Generation Low-k CVD-Films: Black Diamond & Coral CVD Films
`14.5.2.4 2™ Generation Low-k CVD-Films: Parylene CVD Films
`14.6 ULTRA-LOW-& DIELECTRICS: (k <2.3)
`663
`REFERENCES
`669
`
`685
`
`655
`
`Chap. 15 - DUAL-DAMASCENE INTERCONNECTS
`15.1 DAMASCENE VERSUS SUBTRACTIVE
`671
`INTERCONNECT STRUCTURES
`15.2 DAMASCENE INTERCONNECTS AS ALTERNATIVE
`DEEP-SUBMICRON INTERCONNECTS
`15.3 SINGLE-DAMASCENE INTERCONNECT STRUCTURES
`15.4 INTRODUCTION TO DUAL-DAMASCENE
`INTERCONNECT PROCESSES
`
`672
`
`674
`
`15.5 THE THREE DUAL-DAMASCENE PROCESS SEQUENCES
`15.6 THE EVOLUTION OF DUAL-DAMASCENEFROM SiO, TO
`LOW-k DIELECTRIC STACKS
`15.7 TRENCH-FIRST DUAL-DAMASCENE PROCESS FLOW 683
`
`676
`
`679
`
`15.8 VIA-FIRST DUAL~-DAMASCENE PROCESS FLOW
`WITH AN SiO, DIELECTRIC STACK
`
`ONSEMI EXHIBIT 1008D, Page 15
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`ONSEMI EXHIBIT 1008D, Page 15
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`

`

`639
`
`>
`
`646
`
`648
`
`150
`
`655
`
`CONTENTS
`
`xix
`
`15.9 PROCESS INTEGRATIONISSUES OF THE VIA-FIRST DUAL-
`DAMASCENE PROCESS FLOW WITH A LOW-k-
`DIELECTRIC STACK
`
`687
`
`15.9.1 Via-First-Damascene Integration Issues: Lithography
`15.9.1.1 Via-Patterning Lithography Issues
`15.9.1,2 Trench-Patterning Lithography Issues - DUV Resist Poisoning
`15.9.1.3 Trench-Patterning Lithography Issues - Trench CD ControlIssues
`15.9.1,4 Trench-Patterning Lithography Issues - BARC Veils
`15.9.1.5 Bi-Layer Resist Process
`15.9.2 Via-First-Damascene Integration Issues: Dielectric Etching
`15.9.2.1 Via-Etching for Low-k Processes
`15,9.2.1 Trench-Etching
`15.9.2.1 Etching the SiN Barrier at the Bottom of Vias
`15.9.3 Via-First-Damascene Integration Issues: Resist Stripping
`15.9.4 Via-First-Damascene Integration Issues: Cleaning
`15.9.4.1 Post-Dielectric-Etch-and-Strip Residue-Removal
`15.9.4.2 Pre-Metal-Deposition Clean
`15.9.4.3 Post-CMP Clean
`
`
`
`) Films
`
`15,9.4,.4 Clean of Top-Surface of Cu Prior to Diffusion-Barrier-SiN-Deposition Process
`15.9.4.5 Supercritical Fluids as Wafer Cleaners
`15.10 VIA-FIRST DUAL-DAMASCENE DIELECTRIC STACK
`WITH NO EMBEDDED ETCH-STOP LAYER
`15.11 PROCESS INTEGRATION ISSUES OF DUAL-DAMASCENE
`671
`DIELECTRIC STACK WITH ULTRALOW-k DIELECTRICS—708
`
`708
`
`REFERENCES=709
`
`Chap. 16 - COPPER INTERCONNECT PROCESS TECHNOLGY
`16.1 WHY COPPER FOR DEEP-SUBMICRON IC INTERCONNECTS?
`
`711
`712
`
`16.1.1 The Advantages of CopperInterconnects
`16.1.2 Technological Challenges of Using Copper Interconnects
`16.2 OVERVIEW OF COPPER PROCESS TECHNOLOGY=723
`16.2.1 The Transition from Aluminum to CopperInterconnects
`16.2.2 The Key Goal of Depositing Copper into Damascene Recesses
`16.3 BARRIER LAYERS FOR COPPER INTERCONNECTS—728
`679
`
`676
`
`16.3.1 The Impact of the Barrier-Layer Deposition Process on the
`Filling of Damascene Recesses with Copper
`16.3.2 Introduction to the Technology of Depositing Barrier-Layers for
`Cu Interconnects
`
`
`
`ONSEMI EXHIBIT 1008D, Page 16
`
`ONSEMI EXHIBIT 1008D, Page 16
`
`

`

`CONTENTS
`
`16.3.3 Ionized Magnetron Sputter Deposition
`16.3.4 Hollow-Cathode Magnetron Sputtering Source
`16.3.5 Self-Ionized-Plasma Sputtering Source
`16.3.6 Material Properties of Tantalum and Refining Tantalum Metal
`For Semiconductor Applications
`16.3.6.1 Material Properties of Tantalum
`16.3.6,2 Refining and Forming Tantalum Metal For Sputtering Targets
`16.3.6.3 The Properties of Tantalum (and TaN & TaSiN) as Cu-Barrier Layers
`16.3.7 Other Candidate Materials for Cu-Barrier Layers
`16.4 SEED-LAYER TECHNOLOGY FOR COPPER INTERCONNECTS=740
`16.5 COPPER INTERCONNECT FILM DEPOSITION=747
`
`16.5.1 Electrolytic-Plating of Copper
`16.5.2 Filling High-Aspect-Ratio Recesses Without Voids Using a
`Cu Electrolytic Electroplating Process
`16.5.2,1 The Electroplating Process Sequence
`16.5.2.2 Additives in Plating Baths for Damascene Cu Interconnects
`16.5.2,3 Models of How Additives in Plating Baths Impact “Bottom-Up” Filling
`16.5.2.4 Electroplating Bath Control
`16.5.2.5 Pulsed Plating
`16.5.2.6 Copper Thickness Variation Within a Wafer After Electroplating
`16.5.3 Post-Electroplating Cu Annealing and Recrystallization
`16.5.4 Electrochemical Mechanical Deposition (ECMD™)
`16.5.5 Electroless-Plating of Copper
`16.5.6 CVD of Copper
`16.6 WET-CHEMICAL ETCHING AND ELECTROPOLISHING COPPER=775
`16.7 CONTAMINATION CONTROL IN COPPER TECHNOLOGY—778
`
`INDEX
`
`16.7.1 Sources of Copper Cross-Contamination in a Wafer Fab
`16.7.2 Effects of Copper-Cross Contamination at the Back-End-of-Line (BEOL)
`16.7.3 Cu Removal from the Wafer Bevel/Edge and Backside
`16.8 RELIABILITY OF COPPER INTERCONNECTS—784
`16.8.1 Reliability of Copper Interconnects: “Missing-Metal” Defects
`16.8.2 Reliability of Copper Interconnects: Plated vs. CVD Cu Films
`16.9 ENVIRONMENTAL, HEALTH, & SAFETY ISSUES OF CU TECHNOLOGY=787
`16.9.1 Copper Waste Handling
`16.9.1.1 Handling Concentrated Waste from Plating and Wafer Reclaim
`16.9.1.2 Handling Copper CMP Effluents
`REFERENCES
`789
`
`ONSEMI EXHIBIT 1008D, Page 17
`
`ONSEMI EXHIBIT 1008D, Page 17
`
`

`

`PREFACE
`
`ayers
`
`‘S740
`
`Filling
`
`ue
`
`
`
`With the dawn of the new millennium, IC technology-nodes have evolved beyond
`0.18-micron. New processes also had to be developed to meet the needs of this
`Deep-Submicron Era,
`including: copper/low-k dual-damascene interconnects;
`high-k MOSFET-gate and DRAM dielectrics; 300-mm wafers; chemical-
`mechanical polishing (CMP); excimer-laser-based DUV-lithography; chemically-
`amplified (CA)resists; silicon:germanium (Si:Ge); and silicon-on-insulator (SOD).
`The semiconductorindustry, however, also experienced an economic decline of
`unprecedented severity at the start of the 2000 decade. It seamsclear that to fuel the
`recovery, chip manufacturers will have to exploit the above innovations. Such
`processes are a path to achieving the performance goals of future IC technology-
`nodes that will be needed for manufacturing new and profitable electronic products.
`This is the first available book dedicated exclusively to describing such deep-
`submicron process technologies (including those listed above). It is intended to
`provide semiconductor engineers and researchers with a comprehensive, state-of-
`the-art reference about these emerging and leading-edge processes. While many
`other books have been written about the “traditional” IC fabrication processes,
`none offer what this volume contains. It’s sole focus is those techniques needed to
`manufacture chips for 0.18-pm (and smaller) generations. Thus, it belongs on the
`shelf of every microelectronic professional whose livelihood depends on having a
`thorough grasp of the latest advances in IC fabrication techniques. There is no
`faster way to gain this information. As with our other volumes, owners will find
`themselvesreferring to this text again and again!
`Readers canstill consult Vol.1, 2" Edition for background material on basic IC
`fabrication modules, as this book (Vol. 4) does not repeat that information. Instead,
`it presents over 800 pages of new content about the process technologies of the
`2000’s. It also has over 900 references (with 200 of these being published since
`2000), and more than 500 illustrations. It is written in the same lucid, user-friendly
`style that has been widely praised in the other volumes of Silicon Processing for
`the VLSI Era.
`SHNOLOGY=787
`As with the previous volumes, this text was produced using an accelerated
`book-production schedule. By employing revolutionary publishing techniques
`made available in the 1990’s, Lattice Press can turn a finished manuscript into a
`published text in less than 3 months (a task that takes most publishers of technical
`books 15-18 months). This allows our books to be released faster, and to contain
`the most-up-to-date informationat the time of publication.
`xxi
`
`775
`
`PER
`
`778
`
`ne (BEOL)
`
`795
`
`
`
`ONSEMI EXHIBIT 1008D, Page 18
`
`ONSEMI EXHIBIT 1008D, Page 18
`
`

`

`
`
`xxii
`
`PREFACE
`
`SILICON PROCESSING FOR THE VLSI ERA is a multi-volumetreatise
`
`designed to provide a comprehensive and up-to-date treatment of this important
`and rapidly changing field. The volumein hand is the fourth in the series.
`Volume 1 (Process Technology, 2" Edition) was published in 2000 and deals
`with individual processes employed in the fabrication of silicon ULSI circuits
`(such as silicon wafering,
`thermal oxidation of silicon, CVD and PVD of
`amorphous and polycrystalline films, diffusion and ion implantation of dopants
`in silicon, microlithography, and patterning technology). Volume 2 (Process
`Integration) was released in 1990, and describes how the individual processes of
`Volume 1 are combined in various ways to produce MOSandbipolar VLSI and
`ULSIcircuits. The task of integrating these various fabrication processes together
`is referred to as process integration.
`In Volume 3 (The Submicron MOSFET,
`published in 1995) the topics of submicron MOSFET device physics and the
`relationship between such device physics and submicron MOSFETfabrication
`are addressed.
`
`It can also be ordered from the LATTICE PRESS website.
`
`A bookof this length and diversity would not have been possible without the
`indirect and direct assistance of many others. From an indirect perspective,
`virtually all of the information presented here is based on the research efforts of
`countless numbers of scientists and engineers. Their contributions are recognized
`to a small degree in citations of their articles given in the references at the end of
`each chapter. The direct help was also provided by many pcople, and the
`resulting text is thus significantly better. The author expresses heartfelt thanks to
`those who gavetheir time, energy, andintellect.
`Important direct help came from members of my immediate family. My wife,
`Carrol, read the manuscript for grammatical and stylistic correctness. My son,
`Ross, designed the cover and improved many of the graphics. My daughter,
`Jennifer, helped in marketing the book. Thus,
`it
`truly represents a family
`enterprise.
`
`Stanley Wolf
`
`For additional copies of the books contact:
`LATTICE PRESS
`Post Office Box 340
`Sunset Beach, CA 90742 USA
`www.latticepress.com
`
`For your convenience an order form is provided on the final leaf of the book.
`
`ONSEMI EXHIBIT 1008D, Page 19
`
`ONSEMI EXHIBIT 1008D, Page 19
`
`

`

`
`
`L
`f
`
`a
`o
`1
`&
`
`Chapter 5
`
`THE STRUCTURE OF DEEP-SUBMICRON MOSFETS:
`ing:
`a
`Retrograde-Welis; Super-Steep Retrograde Channel Doping;
`m
`.
`2
`Drain Engineering; Punchthrough-Conitrol Structures
`
`, Formed
`247.
`romise,”
`
`itors,”
`acmers
`RAMs,”
`
`tric Film
`;
`"ropertles
`+ CMOS
`
`yer HfO
`ech. Di¢.
`lectric.”
`electric,
`
`h-k Gate
`
`id — The
`
`f
`!
`'
`‘
`a
`ay
`
`a
`
`
`
`'
`|
`
`|
`:
`:
`L
`
`L |f
`
`:
`i
`
`In Chapter 1 we discussed the evolution of MOSFETstructures down to the sub-
`micron technology nodes in production at the time publication of this text. In this
`chapter we delve further into the details of the MOSFET regions that are
`fabricated in such deep-submicron MOSFETs, namely: 1) retrograde wells for
`CMOStwin-well technology; 2) super-steep retrograde (SSR) channel doping
`profiles; 3) drain engineering issues in deep-submicron MOSFETs; and 4)
`punchthrough-control structures.
`5.1 WELL-FORMATION IN DEEP-SUBMICRON CMOS
`Twin-well CMOS is now the dominant CMOStechnology in IC production. In
`twin-well CMOS each well is formed separately by implanting the well dopants
`into a lightly doped substrate region. Having two well implants allows each well-
`type to be tailored separately, permitting independent device performance
`adjustments for both PM