wii
`
`for the VLSI Era
`Volume 3 - The Submicron MOSFET
`
`ONSEMI EXHIBIT 1008C, Page1
`
`ONSEMI EXHIBIT 1008C, Page 1
`
`

`

`THE COMPANION VOLUMES TOTHIS BOOK
`aa
`
`for the VLSI Era
`
`- Process Technology
`Volume 1
`By STANLEY WOLF and RICHARD N. TAUBER
`
`ONSEMI EXHIBIT 1008C, Page 2
`
`TABLE of CONTENTS- Ch.1 Silicon: Single-Crystal Growth and Wafering;
`Ch.2 Crystalline Defects, Thermal Processing, and Gettering; Ch. 3 Vacuum
`Technology for VLSI Applications; Ch. 4 Basics of Thin Films; Ch. 5 Silicon
`Epitaxial Film Growth; Ch. 6 Chemical Vapor Deposition of Amorphous and
`Polycrystalline Films; Ch. 7 Thermal Oxidation of Silicon Ch. 8 Diffusion in
`Silicon; Ch. 9 lon Implantation for VLSI; Ch. 10 Aluminum Thin Films and
`Physical Vapor Deposition in VLSI; Ch. 11 Refractory Metals and Their
`Silicides in VLSI; Ch. 12 Lithography |: Optical Photoresists - Material
`Properties and Process Technology; Ch. 13 LithographyII: Optical Aligners
`and Photomasks; Ch. 14 Advanced Lithography: E-Beam and X-Ray;
`Ch. 15 Wet Processing: Cleaning, Etching, and Lift-Off; Ch. 16 Dry Etching
`for VLSI; Ch. 17 Material Characterization Techniques for VLSI! Fabrication;
`Ch. 18 Structured Approach to Design of Experiments for Process
`Optimization.
`
`1986 LATTICE PRESS
`
`660 pp.
`
`ISBN 0-9616721-3-7
`
`Volume 2 - Process Integration
`By STANLEY WOLF
`
`TABLE of CONTENTS - Ch. 1 Process Integration for VLSI and ULSI;
`Ch. 2 Isolation Technologies for Integrated Circuits; Ch.3 Contact Technology
`and Local Interconnects for VLSI; Ch. 4; Multilevel Interconnect Technology
`for VLSI and ULSI; Ch. 5 NMOS Devices and ProcessIntegration;
`Ch. 6 CMOSProcessIntegration; Ch. 7 Bipolar and BICMOS
`Process Integration; Ch. 8 Semiconductor Memory Process Integration;
`Ch. 9 Process Simulation.
`
`1990 LATTICE PRESS
`
`752 pp.
`
`ISBN 0-9616721-4-5
`
`o
`
`last page of book
`
`ONSEMI EXHIBIT 1008C, Page 2
`
`

`

`

`

`CONTENTS
`
`PREFACE
`
`Chap. 1 - THE ROLE OF PROCESS AND DEVICE
`MODELS IN MICROELECTRONICS TECHNOLOGY
`
`1
`
`1.1 MODELS IN MICROELECTRONIC TECHNOLOGY
`
`1
`
`1.1 .1 Development of Physically Based Models 3
`1. 1.2 Development of Empirically Based Models 4
`1.1.2.1 Empirically Based versus Physically Based Models.
`1.1.2.2 Deriving Empirically Based Models.
`1.1.2.3 Role of Empirical Models in Semiconductor Simulation.
`1.1.2.4 Examples of Quantitative Empirically Based Models.
`1.1.2.5 PREDICT-I: A Process Simulator Based on Empirical Models.
`
`1.2 MATHEMATICAL FORMULATION OF THE PHYSICALLY(cid:173)
`BASED MODELS OF SEMICONDUCTOR PROCESSES AND
`DEVICES 9
`
`1.2.1 The Physically Based Model of Impurity Diffusion in Silicon
`- Fick's Second Law Equation 11
`1.2.2 The Physically Based Model of Semiconductor Device Behavior 12
`1 .2.3 The Poisson Equation 15
`
`1.3 CLOSED-FORM ANALYTICAL SOLUTIONS VERSUS
`NUMERICAL SOLUTIONS OF THE PDES THAT ARE THE
`PHYSICALLY BASED MODELS OF MICROELECTRONICS 1 6
`
`1.3.1 Closed-Form Analytical Solutions - Mathematical Aspects 16
`1 .3.2 Numerical Solutions - Mathematical Aspects 16
`1.3.3 Comparing the Analytical and Numerical
`Solutions in Semiconductor Simulation Applications 17
`1.3.4 Role of Analytical Solutions in Submicron
`Semiconductor Technology 17
`1.3.5 Analytic Solutions of Fick's 2nd Law Equation 19
`
`V
`
`ONSEMI EXHIBIT 1008C, Page 4
`
`

`

`vi
`
`CONTENTS
`
`1.3.6 Analytical Solutions of the One-Dimensional Form of the Poisson
`Equation in the Depletion Approximation 23
`
`1.4 CIRCUMSTANCES UNDER WHICH THE ANALYTIC
`SOLUTIONS OF THESE PDES BECOME INADEQUATE
`FOR SIMULATION PURPOSES
`24
`
`1 .4.1 The Inadequacy of the Analytic Solutions of Fick's 2nd Law
`Equation for Simulating Diffusion in Submicron Device Structures 24
`1.4.2 The Inadequacy of Using a One-Dimensional Form of the Poisson
`Equation and the Depletion Approximation to Model Submicron
`MOSFET Behavior 27
`
`REFERENCES
`
`28
`
`Chap. 2 - NUMERICAL METHODS FOR SOLVING
`THE PARTIAL DIFFERENTIAL EQUA T/ONS
`WHICH MODEL THE PHYSICS OF
`SUBMICRON DEVICES AND PROCESSES
`
`29
`
`2.1 NUMERICAL SOLUTIONS OF DIFFERENTIAL EQUATIONS
`
`31
`
`2.2 NUMERICAL METHODS FOR SOLVING NONLINEAR PARTIAL
`DIFFERENTIAL EQUATIONS
`32
`
`2.3 GRID GENERATION AND REFINEMENT PROCEDURES
`
`34
`
`2.4 DISCRETIZATION OF DIFFERENTIAL EQUATIONS
`
`36
`
`2.4.1 Space Discretization 39
`2.4.2. The Finite-Difference Method 39
`2.4.2.1 The Difference Operator Method
`2.4.2.2 Taylor Series.
`2.4.2.3 One-Dimensional Finite Difference Approximations
`of Derivatives.
`2.4.2.4 Two-Dimensional Space Discretization.
`2.4.3 The Finite Element Method 45
`2.4.4 Time Discretization 47
`2.4.4.1 Explicit Time Discretization.
`2.4.4.2 Implicit Time Discretization.
`
`2.5 ORDERING THE SET OF DISCRETIZED PDEs INTO
`APPROPRIATE MATRIX FORM
`50
`
`ONSEMI EXHIBIT 1008C, Page 5
`
`

`

`CONTENTS
`
`vii
`
`2.6 LINEARIZING NONLINEAR ALGEBRAIC EQUATIONS 52
`
`2.7 MATRIX METHODS FOR SOLVING SIMULTANEOUS LINEAR
`ALGEBRAIC EQUATIONS
`55
`
`2.8 VISUALIZATION OF THE RESULTS
`
`57
`
`2.9 DATA BASE OF THE SIMULATION PACKAGES
`
`58
`
`2.10 EXAMPLES OF THE PROCEDURES USED TO
`NUMERICALLY SOLVE THE MODEL PARTIAL-
`DIFFERENTIAL EQUATIONS OF MICROELECTRONICS
`2.10.1 Outline of a Numerical Analysis Procedure for Solving the Two(cid:173)
`Dimensional Poisson Equation to Simulate the Electrostatic
`Potential in a MOSFET 59
`2.10.1.1 Example of How Device Simulation Programs are Used to Obtain
`the Two-Dimensional Solution of the Poisson Equation in a MOSFET
`Structure Operating in Subthreshold.
`2.10.2 Example of a Numerical Procedure for Solving the One-Dimensional
`Form of Fick's 2nd Law Equation as a Model for Impurity Diffusion
`in Silicon 70
`
`59
`
`2.11 SYSTEMS OF COUPLED EQUATIONS 74
`
`2.11.1 Gummel's Iterative Method 75
`2.11.2 Newton's Direct Method 76
`
`2.12 EVOLUTION OF MOSFET DEVICE SIMULATORS 77
`2.12.1 CADDET 78
`2.12.2 MINIMOS 78
`2.12.3 GEMINI 78
`2.12.4 PISCES-II 80
`2.12.5 Three-Dimensional Device Simulators 80
`
`REFERENCES
`
`81
`
`Chap. 3 - MOS TRANSISTOR DEVICE PHYSICS:
`PART 1 - BASICS MOS PHYSICS and
`THE MOS CAPACITOR
`
`83
`
`3.1 BASIC MOS THEORY and
`PHYSICS of IDEAL MOS CAPACITORS (MOS-C)
`
`84
`
`3.1.1 The Structure of the MOS-C and the MOSFET 85
`3.1. 1. 1 Comparison of MOS-Cs and Conventional Capacitor Structures.
`3.1.1.2 Why is the MOS-C Studied First?
`
`ONSEMI EXHIBIT 1008C, Page 6
`
`

`

`viii
`
`CONTENTS
`
`3.2 QUALITATIVE DESCRIPTION OF MOS-C DEVICE BEHAVIOR 89
`
`3.2.1 Energy-Band Diagram Representation of Semiconductor Devices 90
`3.2.2 Energy Band Diagram of the Ideal MOS Capacitor 91
`3.2.2.1 Accumulation.
`3.2.2.2 Depletion.
`3.2.2.3 Inversion.
`3.2.2.4 Strong Inversion.
`3.2.2.5 Microscopic Perspective of the Mobile Charge Behavior in a MOS-C.
`
`3.3 QUANTITATIVE DESCRIPTION OF MOS-C BEHAVIOR
`
`96
`
`3.3.1 The Electrostatic Potential in MOS Structures 98
`3.3.2 General Approach to Deriving MOS-C Characteristics 100
`3.3.3 Finding the Quantitative Characteristics of a MOS-C when the
`Depletion Approximation is Invoked 103
`3.3.4 More Accurate and General Model
`for MOS-C Behavior 106
`3.3.5 Charge-Sheet Model for Determining the Characteristics of the
`Ideal MOS-C 112
`3.3.5.1 Approximation of Q1 in Weak Inversion.
`3.3.5.2 Approximation of Q1 in Strong Inversion.
`
`3.4 THRESHOLD VOLTAGE OF IDEAL MOS CAPACITORS
`
`116
`
`3.5 PHYSICS OF NON-IDEAL MOS CAPACITORS
`(n+PolySi-SiO2"Si MOS Capacitors)
`117
`
`3.5.1 Workfunction Difference Between Gate and Semiconductor 117
`3.5.2 Oxide Charges and Traps 119
`3.5.2.I Mobile Ionic Charges.
`3.5.2.2 Fixed Oxide Charge.
`3.5.2.3 lnte,face Trapped Charge.
`3.5.2.4 Oxide Trapped Charge.
`3.5.2.5 Combined Effect of Oxide Charges on VT of
`Submicron MOSFETs.
`
`3.6 THE THRESHOLD VOLTAGE EQUATION OF
`Si-SiO2 MOS CAPACITORS
`127
`
`3.7 VISUALIZATION OF MOS-C AND MOSFET PHENOMENA
`USING POTENTIAL VERSUS POSITION DIAGRAMS
`129
`
`REFERENCES
`
`130
`
`ONSEMI EXHIBIT 1008C, Page 7
`
`

`

`CONTENTS
`
`Chap. 4 - MOS TRANSISTOR DEVICE PHYSICS:
`PART 2 - LONG-CHANNEL MOSFETS
`
`4.1 TERMINOLOGY OF MOSFET DEVICE STRUCTURES 135
`
`4.1 .1 Basics of MOSFET Operation 136
`
`4.2 BIASING THE INVERSION LAYER (BODY EFFECT)
`
`138
`
`~
`
`134
`
`4.2.1 Qualitative Discussion of the Effect of Applying a Bias to the
`Inversion Layer of a MOS Structure 138
`4.2.1.1 Case When Both Ven and Ven= 0V.
`4.2.1.2. Case When Vcn2Vrand Ven= 0V
`4.2.1.3. Case When Ven= 0V, But Ven>0V.
`4.2.1.4. Case When Vcn2Vrand Ven>0V.
`4.2.1.5 Summary of the Behavior of the Three-Terminal MOS Structure
`and the Significance of Such Behavior on the Operation
`of the MOSFET.
`4.2.1.6 Body Effect.
`
`4.2.2 Quantitative Description of Effects of Biasing the Inversion Layer of
`MOS Structures
`144
`4.2.2.1 General Case.
`4.2.2.2 Strong Inversion Case.
`
`4.3 DEFINITION OF THE TERM: LONG-CHANNEL MOSFET 147
`
`4.3.1 The Gradual Channel Approximation (GCA) 149
`4.3.1.1 Verifying the Validity of the GCA as a Function of the Geometrical
`Factors of the MOSFET Device Structure and Bias Conditions.
`4.3.2 Circuit Characteristics of Long-Channel MOSFETs 152
`
`4.4 QUALITATIVE DESCRIPTION OF MOSFET OPERATION 153
`
`4.4.1 MOSFET Behavior in Response to Gate Bias Alone 153
`4.4.2 Qualitative MOSFET Behavior when both
`Gate and Drain Bias are Applied 158
`
`4.5 QUANTITATIVE BEHAVIOR OF MOSFETS:
`DC CIRCUIT MODELS OF LONG-CHANNEL MOSFETS 162
`
`4.5.1 General Approach to Deriving the DC Drain-Current Relationships in
`Long-Channel MOSFETs 163
`4.5.2 Pao-Sah Model 166
`4.5.3 The Charge Sheet Model 170
`4.5.4 Variable Depletion-Charge (or Bulk-Charge) Model 173
`
`ONSEMI EXHIBIT 1008C, Page 8
`
`

`

`X
`
`CONTENTS
`
`4.5.5 Square-Law Model 175
`4.5.6 Comparison of the Four MOSFET Circuit Models 177
`4.5.6.1 MOSFET Models of the SPICE Circuit Simulator.
`
`4.6 THRESHOLD-VOLTAGE CONTROL
`
`IN MOSFETS 182
`
`4.6.1 Measuring Threshold Voltage 182
`4.6.2 Adjusting Threshold Voltage 182
`4.6.3 Ion Implantation for Adjusting Threshold Voltage 183
`4.6.3.1 Impact of the Vradjust Implant on the Body Effect.
`4.6.4 Impact of VrAdjust Implant on Other MOSFET Characteristics 188
`
`4.7 SUBTHRESHOLD CURRENTS
`(lost when Vas< IVTI) 191
`
`IN LONG-CHANNEL MOSFETs
`
`4.7.1 Subthreshold Swing St 196
`4.7.2 Gate-Induced Drain Leakage (GIDL) 198
`
`4.8 SUMMARY OF LONG-CHANNEL MOSFET BEHAVIOR
`
`200
`
`REFERENCES
`
`201
`
`Chap. 5 - MOS TRANSISTOR DEVICE PHYSICS:
`PART 3 - THE SUBMICRON MOSFET
`
`205
`
`5.1 DEVICE CHARACTERISTICS OF LONG-CHANNEL VERSUS
`SHORT-CHANNEL MOSFETS
`207
`
`5.2 EFFECT OF GATE DIMENSIONS
`ON THRESHOLD VOLTAGE
`208
`
`5.2.1 Short-Channel Threshold-Voltage Shift 208
`5.2.1.J Numerical Solution of the 2-D Poisson Equation for Calculating
`LIVrsc·
`5.2.1.2 Charge-Sharing Models.
`5.2.1.3 Barrier-Lowering Models and DIEL.
`5.2.1.4 Quasi-Two-Dimensional Analytical Solution for LIVrsc·
`5.2.1.5 Measuring Swface-DIBLEffects.
`5.2.J.6 Dependence ofVron V8s in Short-Channel MOSFETs.
`5.2.2 Narrow Gate-Width Effects on Threshold Voltage 222
`5.2.2.1 Devices Exhibiting Both Short- and Narrow-Width Effects.
`
`ONSEMI EXHIBIT 1008C, Page 9
`
`

`

`CONTENTS
`
`xi
`
`5.2.3 Reverse Short-Channel Effects on Threshold Voltage 226
`5.2.3.1 Model which Proposes RSCE is Due to lateral Dopant Nonuniformity
`at the Channel Si-SiO, lnte,face (Arising from Enhanced Diffusion of
`Channel Dopants Caused by Interstitial Injection During Poly Reox,
`Salicide Formation, or Implant Damage).
`5.2.3.2 Model Which Proposes RSCE Arises from Boron Segregation to
`Implant Damaged Regions at the Edge of the Channel.
`5.2.3.3 Model Which Attributes RSCE to Transient Enhanced Diffusion of
`Channel Dopants to the Silicon Su,face Arising from Implant Damage.
`5.2.3.4 Model which Attributes RSCE to Silicon Interstitial Capture in the
`Gate Oxide.
`
`5.3 SHORT-CHANNEL EFFECTS ON SUBTHRESHOLD SWING,
`St (Subsurface Punchthrough)
`232
`
`5.3.1 Experimentally Characterizing Punchthrough 240
`5.3.2 Modeling Punchthrough 242
`5.3.3 Modeling the Simultaneous Occurrence of Surface-DIBL and
`Subsurface-DIBL 245
`
`5.4 SHORT-CHANNEL EFFECTS ON THE 1-V
`CHARACTERISTICS OF MOSFETS OPERATED IN
`THE STRONG THRESHOLD REGIME
`247
`
`5.4.1 Impact of the MOSFET Electric Fields on Mobility 248
`5.4.1.1 Models of Mobility Degradation Due to Gate-Induced Electric Fields.
`5.4.1.2 Models of the Carrier-Velocity Dependence on Drain Electric Field
`(Velocity Saturation).
`5.4.2 A Simple, Analytic DC Circuit Model of the
`Short-Channel MOSFET in Strong Inversion 254
`5.4.2.1 DC Circuit Model of the Short-Channel MOSFET in the Linear
`Regime.
`5.4.2.2 Effects of Scaling on gmsat·
`5.4.2.3 Comparing the Values of Iv Calculated with the Long- and Short(cid:173)
`Channel MOSFET Models as a Function of Channel Length.
`5.4.3 Modeling the Saturation Region of Operation in Short-Channel
`MOSFETs 260
`5.4.3.1 Modeling Short-Channel MOSFET Saturation Behavior Using the
`Abrupt Junction and Depletion Approximations.
`5.4.3.2 Constant Field-Gradient Model.
`5.4.3.3 Pseudo-Two-Dimensional Model.
`
`5.5. SHORT-CHANNEL MOSFET MODELS
`USED IN THE SPICE CIRCUIT SIMULATOR
`
`271
`
`ONSEMI EXHIBIT 1008C, Page 10
`
`

`

`xii
`
`CONTENTS
`
`5.5.1 BSIM Model Equations 272
`5.5.J.I BSIM Threshold Voltage Equation.
`5.5.J.2 BSIM Equations for 10 wizen the MOSFET is Operated in Strong
`Inversion.
`5.5.1.3 BSIM Equations for I0 when the MOSFET is Operated in Weak
`Inversion (Subthreshold Regime).
`
`5.6 MOSFET SCALING
`
`274
`
`5.6.1 Design of Submicron MOSFETs: Scaling Guidelines 274
`5.6.I.I Constant Electric-Field, Constant Voltage & Electrostatic Scaling.
`5.6.1.2 Subthreshold Scaling.
`5.6.J.3 Off-Current Scaling Approach.
`5.6.2 Manufacturing Considerations in Submicron MOSFET
`Device Design 285
`
`5.7 DESIGN OF SUBMICRON MOSFETS
`
`286
`
`5.7.1 Design Methodology Based on the Subthreshold
`Scaling Equation 286
`5.7.2 Design Methodology Based on Required Off-Current Value 287
`
`5.8 p-CHANNEL DEVICES IN CMOS
`
`288
`
`5.8.1 PMOS Devices with n+-Polysilicon Gates 289
`5.8.J.I Punchthrough Susceptibility.
`5.8.2 Why PMOS Devices with n+-Polysilicon Gates and Implanted
`p-Surface Layers Exhibit Enhanced Susceptibility to
`Short-Channel Effects 291
`5.8.2.1 Threshold-Voltage Roll-Off in Buried-Channel PMOS.
`5.8.2.2 Subthreshold Swing (S1) in Buried-Channel PMOS.
`5.8.2.3 Punchthrough Susceptibility of Buried-Channel PMOS.
`5.8.3 Techniques Used to Suppress Short-Channel Effects in Buried(cid:173)
`Channel PMOS 305
`5.8.3.1 Techniques Used to Keep the Implanted p-Layer as Thin as Possible.
`5.8.3.2 Shallow p+ Source/Drain Junctions to Suppress Punchthrough in
`PMOSFETs.
`5.8.3.3 LDD Structures in PMOS to Limit Punchthrough.
`5.8.3.4 New PMOS Device Structures Designed to Suppress Punchthrough.
`5.8.4 PMOS Devices with p+--Polysilicon Gates
`311
`
`REFERENCES
`
`313
`
`ONSEMI EXHIBIT 1008C, Page 11
`
`

`

`xiii
`
`321
`
`CONTENTS
`
`Chap. 6 - ISOLATION STRUCTURES
`IN SUBMICRON CMOS
`6.1 CHARACTERIZING MOS ISOLATION
`
`6.1.1 Test Structures for NMOS Isolation Structures 322
`6.1.2 Punchthrough Prevention between
`Adjacent Devices in MOS Circuits 325
`
`6.2 THE BASIC LOCOS ISOLATION PROCESS
`
`330
`
`6.2.1 Details of the Basic Semi-recessed LOCOS Process 332
`6.2.1.1 Pad-Oxide Layer.
`6.2.1.2 CVD of Silicon Nitride Layer.
`6.2.1.3 Mask and Etch Pad-Oxide/Nitride Layer to Define Active Regions.
`6.2.1.4 Channel-Stop Implant.
`6.2.1.5 Problems Arising from the Channel-Stop Implants.
`6.2.J.6 Grow Field Oxide.
`6.2.1.7. Factors Which Impact Bird's Beak Length and Shape.
`6.2.1.8 Use of High-Energy Jon Implantation to Introduce the
`Channel-Stop Dopant After Field Oxide Growth.
`6.2.1.9 Strip the Masking Nitride/Pad-Oxide Layer.
`6.2.1. JO Regrow Sacrificial Pad Oxide and Strip (Kooi Effect).
`6.2.2. Planarizing Semirecessed LOCOS Structures 348
`
`6.3 MODELING THE TOPOGRAPHY OF LOCOS STRUCTURES 349
`
`6.3.1 Empirical Models of 2-D Thermal Oxidation 350
`6.3.2 Physically Based Models of 2-D Oxidation 351
`6.3.3 Simulating Thermal Oxidation in 3-D
`Using Physical Models 355
`
`6.4 POLY-BUFFERED LOCOS
`
`357
`
`6.4.1. Modified Poly-Buffered LOCOS Processes 361
`6.4.1.1 Framed-Mask PEL (FMPBL)
`6.4.1.2 Polysilicon-Encapsulated LOCOS (PELOX)
`6.4.1.3 Nitride-Clad LOCOS (NCL)
`6.4.1.4 Mitigating the Field-Thinning Problem of LOCOS
`
`6.5 SHALLOW TRENCH AND REFILL ISOLATION
`
`367
`
`6.5.1 Early Shallow Trench and Refill Isolation 368
`6.5.2 Improved Shallow Trench
`and Refill Isolation Processes 371
`
`ONSEMI EXHIBIT 1008C, Page 12
`
`

`

`xiv
`
`CONTENTS
`
`6.6 CMOS ISOLATION TECHNOLOGY
`
`373
`
`6.6.1 Qualitative Description of Isolation in CMOS 374
`6.6.1.1 Leakage Currents in CMOS Gates Due to Active Device
`Phenomena and Intra-Well Isolation Loss
`6.6.1.2 Leakage Currents in CMOS Gates Due to Loss of Isolation Among
`Opposite-Type FETs
`6.6.1.3 Why n+-to-p+ Isolation Spacing is Greater than n+ -to-n+ Spacing in
`NMOS (or p+-to-p+ Spacing in PMOS)
`6.6.1.4 Effects on n+-to-p+ Spacing of Dopant Redistribution at the Well
`Borders
`6.6.1.5 Threshold Voltage Roi/off, DIEL, and Lateral Punclzthrough in
`Submicron CMOS Parasitic Field FETs
`6.6.2 Quantitative Modeling of CMOS Isolation 384
`6.6.3 Experimental Characterization of Isolation in CMOS 387
`6.6.3.1 Experimental Characterization of Isolation inn+ -to-n-well Parasitic FETs.
`6.6.3.2 Experimental Characterization of Isolation in p+-to-p-substrate Parasitic
`FETs.
`6.6.4 Establishing the Minimum n+-to-p+ Isolation Spacing in CMOS from
`Modeling and Experimental Data 398
`6.6.4.1 Isolation Spacing Design Rulesfor0.35 and 0.25 µm CMOS.
`6.6.5 Vertical Isolation in CMOS 402
`6.6.6 LOCOS-Based Isolation in CMOS 405
`6.6.7 Trench Isolation for CMOS 407
`
`421
`
`REFERENCES
`
`414
`
`Chap. 7 - THIN GA TE OXIDES:
`GROWTH AND RELIABILITY
`7.1 GATE OXIDE CHARACTERISTICS NEEDED
`FOR SUBMICRON MOSFETS
`422
`
`7.2 PHYSICAL PICTURE OF SiO2
`AND THE Si/SiO2
`INTERFACE 423
`
`7.2.1 Physical and Chemical Properties of SiO2
`7.2.2 The Si/SiO2 Interface
`425
`
`423
`
`7.3 CARRIER INJECTION IN THE Si/SiO2 SYSTEM 429
`
`430
`7.3.1 Channel Hot Electrons (CHE)
`7.3.2 Injection of Drain Avalanche Hot Carriers (DAHC) 434
`7.3.3 Fowler-Nordheim (FN) Tunneling 435
`
`ONSEMI EXHIBIT 1008C, Page 13
`
`

`

`CONTENTS
`
`xv
`
`7.3.4 Direct Tunneling
`
`437
`
`7.4 TESTS FOR GATE OXIDE RELIABILITY
`
`438
`
`7.4.1 Measuring Dielectric Strength 438
`7.4.2 Measuring Time-Dependent Breakdown Behavior 440
`7.4.2.1 Time-to-Breakdown under Constant-Voltage Stressing.
`7.4.2.2 Time-to-Breakdown under Constant-Current Stressing.
`7.4.2.3 Charge to Breakdown (QsD)-
`7.4.3 Mathematics of Reliability Characteristics
`7.4.3.1 The Failure Unit ( FIT).
`7.4.3.2. The Cumulative Distribution Function.
`7.4.3.3 Probability Density Function.
`7.4.3.4 The Instantaneous Failure Rate.
`7.4.3.5 The Mean Time to Failure.
`7.4.3.6 The Weibull Cumulative Distribution Function.
`7.4.3. 7 The Log-Normal Cumulative Distribution Function.
`7.4.3.8 Characterizing the Reliability of Oxides in Terms of the
`Mathematical Reliability Functions.
`
`441
`
`7.5 THE PHENOMENON OF OXIDE BREAKDOWN
`
`448
`
`7.5.1 Qualitative Physical Models of Intrinsic Oxide Breakdown 451
`7.5. I.I Hole Generation and Trapping Model.
`7.5.1.2 Wolters' Electron Lattice-Damage Model.
`7.5.2 Qualitative Models for the Physical Origin of B-Mode Failures
`in Oxides 458
`7.5.2.1 Test Structure for Intrinsic Oxide Breakdown Measurements.
`7.5.2.2 Damage at the Gate Periphery Resulting from the Polysilicon Etch
`Process.
`7.5.3 Empirical Quantitative Model of Intrinsic Oxide Breakdown 462
`7.5.4 Quantitative Models for B-Mode Failures 467
`7.5.4.1 Reduced Barrier Height Model.
`7.5.4.2 Oxide Thinning Model.
`7.5.4.3. The Cumulative Defect Density Function D( !Jt0x!-
`7.5.4.4. Using D(!Jt0 x! to Predict Oxide Breakdown Reliability.
`7.5.4.5. Ramp-Voltage Breakdown Test for Obtaining D(!Jt0 x! Data.
`7.5.4.6. Correlating Ramp-Voltage Test Data and Constant-Voltage
`TDDB Data.
`7.5.4.7 Interface Trap Generation as a Measure of Oxide Damage
`Due to Charge Injected into the Oxide.
`7.5.5 Applications of the Oxide Breakdown Reliability Model
`7.5.5.1 Projecting the Reliability of Gate Oxides with Various
`Thicknesses.
`
`477
`
`ONSEMI EXHIBIT 1008C, Page 14
`
`

`

`xvi
`
`CONTENTS
`
`7.5.5.2 If a MOS IC is to have a Specific Lifetime (e.g., IO-Years}, What is
`the Minimum Oxide Thickness that can be Used? (Assume the
`Maximum Cumulative Failure Percentage, Operating
`Temperature, and Oxide Area are Specified.)
`
`7.6 SCREENING TESTS FOR OXIDE BREAKDOWN (BURN-IN) 482
`
`7.6.1 Modeling the Effect of the Burn-In Stress on the Post-Burn-In
`Reliability of the Oxides 485
`7.6.2 Procedure for Selecting an Optimal Set of Burn-In Conditions for
`Oxide Breakdown Screening
`486
`7.6.3 Example of Applying the Procedure for
`Determining an Optimal Set of Burn-In Conditions 489
`
`7.7 OXIDE BREAKDOWN MODULE IN BERKELEY RELIABILITY
`TOOL (BERT) 492
`
`7.8 MODELS OF THIN OXIDE GROWTH
`
`492
`
`7.9 TECHNOLOGY OF THIN OXIDE GROWTH
`
`495
`
`7.9.1 Oxidation Furnaces 495
`7.9.2 Control of Gate Oxide Growth Rates 495
`7.9.3 Factors Impacting Gate-Oxide Thickness Uniformity 496
`7.9.4 Gate Oxide Growth Processes for 10-20 nm thick Gate Oxides on
`150-200 mm Wafers 499
`7.9.5 Alternative Gate Oxide Growth Processes 502
`7.9.5. I Stacked Gate Oxide Films (Thermally Grown Layer and CVD Layer).
`
`7.10 GATE OXIDE DAMAGE FROM PLASMA PROCESSING 504
`
`7.10.1 How Isolated Conductor Regions on a Wafer Surface Can be Charged
`Up by an RF Plasma 504
`7.10.2 Causes of Non-Uniformities in Plasmas 506
`7.10.3 Test Structures used to Characterize Plasma-Induced Oxide Damage 507
`7.10.4 Electrical Tests for Measuring Oxide Damage 509
`7. I 0.4.1 Wafer Mapping to Determine Positional Dependence of Damage on the
`Wafer Surface.
`7.10.5 Oxide Damage Models in Various Plasma Etching Processes 511
`7.10.5. 1 Oxide Damage During Polysilicon or Metal Etch Processes.
`7.10.5.2 Oxide Damage During Resist Stripping.
`7.10.5.3 Radiation Induced Oxide Damage.
`7.10.6 Procedures for Reducing Plasma-Induced Oxide Damage 514
`
`REFERENCES
`
`51 5
`
`ONSEMI EXHIBIT 1008C, Page 15
`
`

`

`CONTENTS
`
`Chap. 8 - WELL FORMATION IN CMOS
`8.1 p-WELL, n-WELL, and TWIN-WELL TECHNOLOGIES
`
`524
`
`xvii
`
`523
`
`8.1.1 p-Well CMOS 525
`8.1.2 n-Well CMOS 527
`8.1.3 CMOS on Epitaxial Substrates 528
`8.1.4 Twin-Well CMOS 530
`8.1.5 Summary of CMOS Well-Technology Issues 532
`
`8.2 CONVENTIONAL FORMATION OF WELLS AND CHANNEL
`STOPS
`532
`
`8.2.1 Aligning Subsequent Patterns to the Wells 532
`8.2.2 Twin-Well and Channel-Stop Formation 535
`8.2.3 Split Well-Drive-In Process 538
`
`8.3 RETROGRADE-WELL CMOS
`
`539
`
`8.3.1 Retrograde Well Technologies to Improve Isolation 546
`
`8.4 FUTURE TRENDS IN WELL FORMATION
`
`552
`
`8.5 AFTER-GATE IMPLANTATION (AGI)
`
`554
`
`REFERENCES
`
`555
`
`Chap. 9 - HOT-CARRIER RESISTANT PROCESSING
`AND DEVICE STRUCTURES
`
`559
`
`9.1 MODEL FOR THE MAXIMUM LATERAL ELECTRIC FIELD
`tymax IN NON-GRADED-DRAIN MOSFETS
`561
`
`9.2 SUBSTRATE CURRENTS DUE TO HOT CARRIERS 563
`
`9.3 MODELS OF HOT-CARRIER DEGRADATION PHENOMENA
`
`566
`
`9.3.1. Si-H Bond Breaking Model 569
`9.3.2 Hot-Hole and Hot-Electron Trapping Model 569
`9.3.3 Location of the Hot-Carrier Damaged Region 571
`
`9.4 CHARACTERIZING MOSFET DEGRADATION DUE TO HOT-
`CARRIER EFFECTS
`572
`
`9.4.1 Device Parameters that are Impacted by Hot-Carrier Damage 573
`
`ONSEMI EXHIBIT 1008C, Page 16
`
`

`

`xviii
`
`CONTENTS
`
`9.4.2 How to Determine if a MOSFET Can be Operated with out Failing
`due to Hot-Carrier Effects Under Normal Operating Conditions? 574
`9.4.2.1 Selecting a Criterion that Identifies Device Failure Due to Hot-
`Carrier Damage.
`9.4.3 Accelerated Testing of Hot-Carrier Device Lifetime 576
`9.4.4 Hot-Carrier Lifetime Under AC Stressing 580
`9.4.5 Effect of Device Degradation on Circuit Performance 581
`9.4.6 Hot-Carrier Reliability Simulation 582
`9.4.6.J SCALE.
`9.4.6.2 Simulators that Relate the Device-Level Degradation
`Parameters to Circuit Pe,formance (CAS and HOTRON).
`
`9.5 DECREASING HOT CARRIER DEGRADATION BY MODIFYING
`THE MOSFET STRUCTURE
`586
`
`9.5.1 Phosphorus-Drain Structure 588
`9.5.2 Double Diffused Drain (DDD) 588
`
`9.6 LIGHTLY DOPED DRAIN (LDD) STRUCTURES
`
`591
`
`9.6.1 Modeling Eymax in LDD MOSFETs 592
`9.6.1.1 Simple Model for Estimating Eymax in LDD MOSFETs
`9.6.1.2 Analytical Mode/for Calculating Eymax in LDD
`MOSFETs Using the Pseudo-2D Approach to Solving the
`Poisson Equation.
`9.6.1.3 Model for the Series Resistance Introduced by the 11· Region
`of the LDD.
`9.6.2 Overview of the Process Sequence to Form LDDs 595
`
`9.7 PERFORMANCE AND HOT-CARRIER LIMITATIONS OF THE
`CONVENTIONAL LDD
`598
`
`9.7.1 Performance Degradation in LDD MOSFETs 599
`9.7.1.1 JD Decrease Due to Added Resistance ofn· Regions.
`9.7.1.2 Doping Compensation Effects that can Increase R11- in Deep
`Submicron LDD MOSFETs.
`9.7.1.3 Increase of Rs!, by Weak Overlap of the Gate and Drain.
`9.7.1.4 The Impact of Poly Re-Ox on Weak Overlap in MOSFETs.
`9.7.1.5 Off-Axis Implant Effects in MOSFETs, Leading to Weak
`Overlap Problems and Asymmetrical MOSFET Device
`Characteristics.
`9.7.1.6 Jmplanter Issues that Impact the LDD Process Sequence.
`9. 7.1. 7 Process integration issues which arise when an LDD is
`integrated into a CMOS Technology.
`9.7.2 Hot Carrier Reliability Issues in Early LDDs 606
`
`ONSEMI EXHIBIT 1008C, Page 17
`
`

`

`CONTENTS
`
`xix
`
`9.8 DISPOSABLE SPACERS
`
`608
`
`9.9 SUMMARY OF THE LIMITATIONS OF EARLY LDD DEVICES 611
`
`9.10 SUMMARY OF THE METHODS TO BE USED IN DESIGNING
`EFFECTIVE LDD STRUCTURES 612
`
`9.11
`
`IMPROVED CONVENTIONAL (OXIDE-SPACER-BASED) LDD
`STRUCTURES
`613
`
`9.11.1
`
`Increasing the Doping in the n· Region of the LDD 614
`9.11.1.1 Moderate Lightly Doped Drain (M-LDD).
`9.11.1.2 Metal-coated LDD (MLD).
`9.11.2 Tailoring the Vertical Doping Profile of the
`n· Implant to Improve the Conventional LDD 616
`9.11.2.1 Buried-LDD (B-LDD).
`9.11.2.2 Profiled-LDD (P-WD).
`9.11.3 Improving the Short-Channel Performance of the Conventional
`NMOSLDD 621
`
`9.12 FULLY OVERLAPPED LDD STRUCTURES
`
`623
`
`9.12.1 lnverse-T Gate LDD (ITLDD) and Gate-Drain Overlapped Device
`(GOLD) Structures 623
`9.12.1.1 lnverse-T Gate LDD Structure.
`9.12.1.2 Gate-Drain Overlapped LDD (GOLD).
`9.12.1.3 Modified JT-LDD Structures.
`9.12.2 Large-Angle-Tilt Implanted Drain (LATID) 630
`9.12.3 High Dielectric Spacers 634
`9.12.4 Asymmetrical MOSFET Structure: Halo-Source-GOLD
`(HS-GOLD) 636
`
`9.13 HOT-CARRIER EFFECTS IN PMOS TRANSISTORS
`
`637
`
`9.13.1 Model for Hot-Carrier Damage in PMOSFETs 638
`9.13.2 Hot-Electron Induced Punchthrough (HEIP) 638
`9.13.3 Hot-Electron Induced Degradation in
`p+-Poly PMOSFETs 641
`
`9.14 STRENGTHENING OXIDES AGAINST HOT-CARRIER
`INJECTION 641
`
`9.14.1 Minimizing Hydrogen and H2O at the Si-SiO2 Interface 643
`9.14.1.1. The role of hydrogen in hot-carrier degradation.
`
`ONSEMI EXHIBIT 1008C, Page 18
`
`

`

`xx
`
`CONTENTS
`
`9.14.1.2 Hydrogen introduced at high temperatures.
`9.14.1.3 Moisture in Gate Oxides as a Contributor to Hot~Carrier
`Degradation.
`9.14.2 Gate-Oxide Damage by Metal Etching 647
`9.14.3 Nitrided Oxides 648
`9. 14.3.1 Thermal nitridation of Si02•
`9.14.3.2 NH3 Oxides as MOSFET Gate Dielectrics.
`9.14.3.3 low-Pressure and RTP NH3 Oxides (Lightly Nitrided
`Reoxidized NH,-Nitrided Oxides).
`9.14.3.4 Oxynitridation of Silicon in N20 Ambients.
`9.14.3.5. Oxynitridation of Oxides in N20.
`9.14.3.6 Fluorinated Oxides.
`
`REFERENCES
`
`661
`
`675
`
`APPENDIX A - MATRIX METHODS
`A.1
`INTRODUCTION TO MATRICES
`675
`A.2 MATRIX MULTIPLICATION
`677
`A.3 MATRIX INVERSION
`678
`A.4 MATRIX METHODS FOR SOLVING SIMULTANEOUS LINEAR
`ALGEBRAIC EQUATIONS
`680
`A.5 NON-LINEAR ALGEBRAIC EQUATIONS
`
`691
`
`APPENDIX B - MAXIMIZING THE CIRCUIT PERFORMANCE OF
`LONG-CHANNEL MOSFETS THROUGH DEVICE DESIGN AND
`PROCESSING TECHNOLOGY
`695
`
`8.1 CHARACTERISTICS OF DIGITAL IC MOSFETS
`8.2 DESIRED CIRCUIT CHARACTERISTICS OF IC
`INTERCONNECTS 697
`
`695
`
`APPENDIX C - DERIVATION OF THE BSIM 10 MODEL 705
`
`APPENDIX D · DERIVATION OF THE DISCRETIZED
`POISSON EQUATIONS USING THE BOX-INTEGRATION
`METHOD 708
`
`2-D
`
`INDEX
`
`709
`
`ONSEMI EXHIBIT 1008C, Page 19
`
`

`

`PREFACE
`
`SILICON PROCESSING FOR THE VLSI ERA now represents a series of texts
`designed to provide a comprehensive and up-to-date treatment of this important and
`rapidly changing field. The volume in hand is the third of this series. Volumes I
`(Process Technology) and 2 (Process Integration) were published in 1986 and 1990,
`respectively. Volume I deals with the individual processes employed in the fabrication
`of silicon VLSI circuits, such as epitaxial growth, thermal oxidation of silicon, CVD
`and PVD of amorphous and polycrystalline films, diffusion and ion implantation of
`dopants in silicon, microlithography, and patterning technology. Volume 2 describes
`how the individual processes of Volume 1 are combined in various ways to produce
`MOS and bipolar VLSI and ULSI circuits. The task of integrating these various
`fabrication processes together is referred to as process integration.
`Here, we treat the topics of submicron MOSFET device physics and the
`relationship between such device physics and submicron MOSFET fabrication. That is,
`an understanding of device physics has become even more important now that
`MOSFETs have crossed the long-channel frontier into the submicron realm. Device
`aspects that could once be ignored (because they cause only second-order effects in large
`MOS devices) are now significant. Many device effects observed in submicron
`MOSFETs are impacted by the process technology used to fabricate them. Some of
`such effects include: short-channel effect on VT; RSCE (reverse-short-channel effect on
`VT); DIEL (drain-induced barrier lowering); narrow-width effect; reverse-narrow-width
`effect; subsurface punchthrough in NMOSFETs; punchthrough in PMOSFETs; impact
`of the V,adjust implant on subthreshold swing, S1; boron penetration of gate oxides in
`p+-poly-gate PMOSFETs - and the polysilicon depletion effect that this causes; GIDL
`(gate-induced drain leakage); impact of process technology on the reliability and wearout
`of thin gate oxides, including damage from plasma processing; hot-carrier degradation
`and drain-engineered MOSFET structures developed to combat the problem (including
`LDDs, LATID, "halo" implants, and asymmetrical MOSFETs); well-engineering by
`high-energy implants (including retrograde-well CMOS); ROXNOX (re-oxidized-nitrided
`oxides); and very-lightly-nitrided gate oxides. These and many other phenomena
`associated with submicron MOS fabrication can only be understood in the context of
`short-channel MOSFET physics. Only with such an understanding can the relationship
`between circuit behavior, device design, and process technology of submicron
`MOSFETs be grasped. Consequently, by gaining such an understanding process
`engineers (and other microelectronic professionals) will be better able to contribute to
`the task of successfully designing and manufacturing submicron !Cs. One of our main
`purposes is thus to provide a text that treats both the topics of submicron MOSFET
`device physics and the phenomena associated with fabricating such devices.
`Chapter I introduces the process and device models employed in the early days of
`the semiconductor industry. Such models were based on empirical data and/or simplified
`physical equations (e.g., differential equations in their one-dimensional form). In the
`
`xxi
`
`ONSEMI EXHIBIT 1008C, Page 20
`
`

`

`xxii
`
`submicron era, however, the more general forms of these differential equations must be
`used to obtain accurate predictive capability of both the fabrication processes and the
`device physics. Since this generally means that partial differential equations in two- or
`three-dimensional form must be solved, this can only be carried out by numerical
`analysis, performed with the aid of high-speed digital computers. Thus, chapter 2
`outlines the methodology of this approach.
`To facilitate the discussion of submicron MOSFET device physics, we divide the topic
`up into three chapters: The first of these, chapter 3, deals with basic MOS theory and
`the MOS capacitor. The next, chapter 4, covers long-channel MOSFETs and the circuit
`models developed to predict the drain current characteristics of such devices. Finally,
`chapter 5 describes the characteristics of the short-channel (i.e., submicron) MOSFET.
`This is the longest chapter of the book, and it includes the following topics: DIBL,
`subsurface punchthrough, the drain current in saturation, simplified short-channel
`MOSFET circuit models, MOSFET scaling, andsubmicron PMOSFETs.
`Chapter 6 is concerned with isolation issues in integrated circuits with an emphasis
`on CMOS technology. Chapter 7 covers thin gate oxides, primarily with respect to their
`reliability and growth. Chapter 8 deals with well formation in CMOS. Chapter 9
`focuses on hot-carrier effects in MOS ICs, as well as on device structures and processing
`techniques that mitigate the d