`

`ae
`ORM=
`[mse
`= hs
`MD
`>
`coe=
`
`TK 2Aen
`
`TK
`7874
`.W635
`
`ONSEMI EXHIBIT 1008B, Page 2
`
`2m
`
`aea
`m
`
`Volume2
`
`Process
`
`Integration
`
`SAAell
`
`ONSEMI EXHIBIT 1008B, Page 2
`
`

`

`SILICON PROCESSING FORT $45.SS
`
`11!1111~/llllm~ l!~~m
`
`t'H CTU.1 f"\I
`
`?~n'F<t.~1
`
`....__ - -
`
`ONSEMI EXHIBIT 1008B, Page 3
`
`

`

`CONTENTS
`
`PREFACE
`
`CHAP. 1 • PROCESS INTEGRATION FOR
`VLSI AND ULSI
`
`1
`
`1.1 PROCESS
`
`INTEGRATION
`
`5
`
`1 .1.1 Process Sequence Used lo Fabricate an
`Integrated-Circuit MOS Capacitor, 5
`1.1.2 Specifying a Process Sequence, 6
`1.1.3 Levels of Process Integration Tasks, 7
`
`1.2
`
`PROCESS-DEVELOPMENT AND
`PROCESS-INTEGRATION ISSUES
`
`8
`
`REFERENCES
`
`11
`
`CHAP. 2 - /SOLA TION TECHNOLOGIES FOR
`INTEGRATED CIRCUITS
`
`12
`
`2.1 BASIC ISOLATION PROCESSES FOR BIPOLAR ICs
`
`13
`
`2.1.1 Junction Isolation, 13
`2.1.1.1 Junction lsolation in the SBC Process
`2.1.1.2 Collector-Diffusion Isolation
`
`2.2 BASIC ISOLATION PROCESS FOR MOS ICs
`(LOCOS
`ISOLATION)
`17
`
`2.2.1 Punchthrough Prevention between Adjacent Devices in MOS
`Circuits, 20
`2.2.2 Details of the Semi recessed Oxide LOCOS Process, 20
`2.2.2.1 Pad-Oxide Layer.
`2 .2.2 .2 CVD of Silicon Nitride Layer.
`2.2.2.3 Mask and Etch Pad-Oxide/Nitride Layer to Define Active
`Regions.
`
`vii
`
`ONSEMI EXHIBIT 1008B, Page 4
`
`

`

`Viii
`
`CONTENTS
`
`2.2.2.4 Channel-Stop Implant.
`2.2.2.5 Problems Arising from the Channel-Stop Implants.
`2.2.2.6 Grow Field Oxide.
`2.2.2.7 Strip the Masking Nitride/Pad-Oxide Layer.
`2.2.2.8 Regrow Sacrificial Pad Oxide and Strip (Kooi Effect).
`2.2.3 Limitations of Conventional Semi-Recessed Oxide LOCOS for
`Small-Geometry !Cs, 27
`
`2.3 FULLY RECESSED OXIDE LOCOS PROCESSES
`
`28
`
`2.3.1 Modeling the LOCOS Process, 31
`
`2.4 ADVANCED SEMIRECESSED OXIDE LOCOS ISOLATION
`PROCESSES
`3 1
`
`2.4.1 Etched-Back LOCOS, 31
`2.4.2 Polybuffered LOCOS, 32
`2.4.3 SILO (Sealed-Interface Local Oxidation), 33
`2.4.4 Laterally Sealed LOCOS Isolation, 35
`2.4.5 Bird's Beak Suppression in LOCOS by Mask-Stack Engineering, 38
`2.4.6 Planarized SILO with High-Energy Channel-Stop Implant, 38
`
`2.5 ADV AN CED FULLY RECESSED OXIDE LOCOS
`PROCESSES
`39
`
`ISOLATION
`
`2.5.1 SWAMI (Sidewall-Masked Isolation Technique}, 39
`2.5.2 SPOT (Self-Aligned Planar-Oxidation Technology), 41
`2.5.3 FUROX (Fully Recessed Oxide}, 41
`2.5.4 OSELO II, 43
`
`2.6 NON-LOCOS ISOLATION TECHNOLOGIES I:
`(TRENCH ETCH AND REFILL)
`45
`
`2.6.1 Shallow Trench and Refill Isolation, 45
`2.6.1.I BOX Isolation.
`2.6.1.2 Modifications 10 Improve BOX Isolation.
`2.6.2 Moderate-Depth Trench and Refill Isolation, 48
`2.6.2.1 U-Groove Isolation.
`2.6.2.2 Toshiba Moderate-Depth Trench Isolation for CMOS.
`2.6.3 Deep, Narrow Trench and Refill, 51
`2.6.3.l Reactive Ion Etching of the Substrate.
`2.6.3.2 Refilling the Trench.
`2.6.3.3 Planarization after Refill.
`
`ONSEMI EXHIBIT 1008B, Page 5
`
`

`

`CONI'ENTS
`
`ix
`
`2.7 NON-LOCOS ISOLATION TECHNOLOGIES, II: SELECTIVE
`EPITAXIAL GROWTH
`(SEG)
`58
`
`2.7.1 Refill by SEG of Windows Cut into Surface Oxide, 59
`2.7.2 Simultaneous Single-Crystal/Poly Deposition (SSPD), 60
`2.7.3 Etching of Silicon Trenches and Refilling with SEG to Form Active
`Device Regions, 61
`2.7.4 Selective-Epitaxial-Layer Field Oxidation (SELFOX), 61
`2.7.5 SEG Refill of Trenches (as an Alternative to Poly Refill), 62
`2.7.6 Epitaxial Lateral Overgrow1h (ELO), 62
`
`2,8 MISCELLANEOUS NON-LOCOS
`ISOLATION TECHNOLOGIES
`
`63
`
`2.8.1 Field-Shield Isolation, 63
`2.8.2 Buried Insulator between Source/Drain Polysilicon (BIPS), 64
`
`2.9 SUMMARY: CANDIDATE ISOLATION TECHNOLOGIES FOR
`SUBMICRON DEVICES
`65
`
`2.9.1 Basic Requirements of VLSI and ULSI Isolation Technologies, 65
`2.9.2 The Need for Planarity, 65
`2.9.3 How the Various Isolation Technologies Meet the Requirements, 66
`
`2.10 SILICON-ON-INSULATOR (SOI)
`TECHNOLOGIES
`66
`
`ISOLATION
`
`2.10.1 Dielectric Isolation, 67
`2.10 .2 Wafer Bonding, 70
`2.10.3 Silicon-on-Sapphire (SOS), 72
`2.10.4 Separation by Implanted Oxygen (SIMOX), 72
`2.10.5 Zone-Melling Recrystallization (ZMR), 75
`2.10.6 Full Isolation by Porous Oxidized Silicon (FIPOS), 76
`2.10.7 Novel SOI CMOS Processes with Selective Oxidation and Selective
`Epitaxial Grow1h, 77
`
`REFERENCES
`
`79
`
`ONSEMI EXHIBIT 1008B, Page 6
`
`

`

`X
`
`CONTENrS
`
`CHAP. 3 • CONTACT TECHNOLOGY AND
`LOCAL INTERCONNECTS FOR VLSI
`
`84
`
`3.1 THE ROLE OF CONTACT STRUCTURES IN DEVICE AND
`84
`CIRCUIT BEHAVIOR
`
`3.1.1 Contact Structures in Planar MOSFETs and Bipolar Transistors, 85
`
`3.2 THEORY OF METAL-SEMICONDUCTOR CONTACTS
`
`87
`
`3.3 EXTRACTING VALUES OF SPECIFIC CONTACT RESISTIVITY
`91
`FROM MEASUREMENTS
`
`3.3.1 Extraction of the Specific Contact Resistivity from an Ideal Contact
`Structure, 92
`3.3.2 Current Flow in Actual Contact Structures, 93
`3.3.3 Contact Structures Used to Extract Pc, 94
`3.3.4 Procedure for Accurately Extracting Pc from
`CBKR Test Structures, 97
`3.3.5 Reported Values of Pc for Various Contact Structures, 100
`3.3.6 Use of a Simple Contact-Chain Structure to Monitor Contact
`Resistance, 101
`
`3.4 THE EVOLUTION OF CONVENTIONAL METAL-TO-SILICON
`CONTACTS
`101
`
`3.4.1 The Basic Process Sequence of Conventional Ohmic-Contact
`Structures to Silicon, 102
`3.4.2 Additional Details Concerning the Processing Steps, 103
`3.4.2.1 Formation of the Heavily Doped Regions in the Silicon.
`3.4.2.2 Formation of Contact Openings (Etching).
`3.4.2.3 Sidewall Contouring of the Contact Holes by Ref/ow.
`3.4.2.4 Sidewall Contouring by Etching.
`3.4.2.5 Deposition.
`3.4.2.6 Metal Deposition and Pauerning.
`3.4.2.7 Sintering the Contacts.
`3.4.3 Aluminum-Silicon Contact Characteristics, 111
`3.4.3.1 The Kinetics of the Al-Si Interface During Sintering.
`3.4.4 Use of Aluminum-Silicon Alloys to Reduce Junction Spiking, 116
`3.4.5 Platinum Silicide-to-Silicon Contacts, 117
`3.4.5.1 Process Sequence Used to Form PtSi-Si Contacts.
`3.4.5.2 Limitations of the PtSi-Si Contact Structure.
`
`ONSEMI EXHIBIT 1008B, Page 7
`
`

`

`CONTENI'S
`
`xi
`
`3.5 DIFFUSION BARRIERS
`
`121
`
`3.5.1 Theory of Diffusion Barner Layers, 121
`3.5.2 Materials Used as Diffusion Barners, 124
`3.5.2.1 Spuuer-Deposited Titanium-Tungsten (Stuffed Barrier).
`3.5.2.2 Polysi/icon (Sacrificial Barrier).
`3.5.2.3 Titanium (Sacrificial Barrier).
`3.5.2.4 Titanium Nitride (Passive Barrier).
`3.5.2.5 CVD Tungsten.
`3.5.2.6 Experimental Diffusion Barrier Materials.
`
`3.6 MULTILAYERED OHMIC-CONTACT STRUCTURES TO
`SILICON
`131
`
`3.6.1 AI-Ti:W-P!Si-Si Contacts, 132
`3.6.2 Al-TIN-TI-Si Contacts, 132
`3.6.3 Mo-Ti:W-Si and Mo-Ti-Si Contacts, 134
`
`3.7 SCHOTTKY-BARRIER CONTACTS 134
`
`3.8 THE IMPACT OF THE INTRINSIC SERIES RESISTANCE ON
`MOS TRANSISTOR PERFORMANCE
`137
`
`3.8.1 The Impact of Rs on MOSFET Performance, 137
`3.8.2 Estimates of Rsh, Rsp, Rae, and Rco, 138
`3.8.3 Impact of Rs on Device Characteristics, 142
`3.8.4 Summary of the Impact of Intrinsic Series- Resistance Effects on
`MOSFET Performance, 142
`
`3.9 ALTERNATIVE (SELF-ALIGNED) CONTACT STRUCTURES
`FOR ULSI MOS DEVICES
`143
`
`3.9.1 Self-Aligned Silicide Contacts, 144
`3.9.1.1 Self-Aligned Titanium Silicide Contacts.
`3.9.J .2 Self-Aligned Cobalt Silicide Contacts.
`3.9.1.3 Measuring re of Self-Aligned Silicide Contacts.
`3.9.2 Buried-Oxide MOS Contact Structure (BOMOS), 153
`
`3.10 FORMATION OF SHALLOW JUNCTIONS AND THEIR IMPACT
`ON CONTACT FABRICATION
`154
`
`3.10.1 Conventional Shallow-Junction Formation, 154
`3.10.2 Alternative Approaches to Forming Shallow Junctions, 155
`3.10.3 Impact of Shallow Junctions on Contact Formation, 160
`
`ONSEMI EXHIBIT 1008B, Page 8
`
`

`

`xii
`
`CONTENTS
`
`3.11 BURIED CONTACTS AND LOCAL INTERCONNECTS
`
`160
`
`3.11.1 Butted Contacts and Buried Contacts, 160
`3.11.2 Local Interconnects, 162
`3.11.2.1 Selectively Formed TiSiz.
`3.11.2.2 Ti:W over C0Si2.
`3.11.23 TiN Formed over TiSiz.
`3.1 I .2.4 Dual-Doped Polysilicon U with Diffused Source/Drain
`Junctions.
`3.11.2.5 CVD W-Ciad Polysilicon U.
`
`REFERENCES
`
`CHAP. 4 • MUL Tl LEVEL INTERCONNECT
`TECHNOLOGY FOR VLSI AND ULSI
`
`176
`
`INTERCONNECT
`4.1 EARLY DEVELOPMENT OF
`TECHNOLOGY FOR INTEGRATED CIRCUITS
`
`176
`
`4.1.1 Interconnects for Early Bipolar ICs, 176
`4.1.2 Interconnects in Silicon-Gate NMOS ICs, 178
`4.1,3 Evolution of Interconnects for Bipolar !Cs, 179
`4.1.4 Evolution of Interconnects for CMOS !Cs, 180
`
`4.2 THE NEED FOR MULTILEVEL INTERCONNECT
`TECHNOLOGIES
`180
`
`4.2.1 Interconnect Limitations of VLSI, 181
`4.2.1 .I Functional Density.
`4.2.1.2 Propagation Delay,
`4.2.1.3 Ease of Design and Gate Utilization for AS!Cs and Wafer Scale
`Integration.
`4.2.1.4 Cost.
`4.2.2 Problems Associated with Multimetal Interconnect Processes, 187
`4.2.3 Terminology of Multilevel Interconnect Structures, 188
`
`4.3 MATERIALS FOR MULTILEVEL INTERCONNECT
`TECHNOLOGIES 189
`
`4.3.1 Conductor Materials for Multilevel Interconnects, 189
`4.3.1.1 Requirements of Conductor Materials Used for VLSI Interconnects.
`4.3.1.2 Local Interconnect Conductor Materials (Polysi/icon, Metal-Silicides,
`and Polycides).
`
`ONSEMI EXHIBIT 1008B, Page 9
`
`

`

`CONTENTS
`
`xiii
`
`4.3.1.3 Aluminum Metallization.
`4.3.1.4 Tungsten and Other Conductor Materials for VLSI Interconnects.
`4.3.2 Dielectric Materials for Multilevel Interconnects, 194
`4.3.2.1 Requirements of Dielectric Layers in Multilevel Interconnects.
`4.3.2.2 Poly-Metal Inter/eve/ Dielectric (PMD) Materials.
`4.3.2.3 CVD SiOz Films as Intermetal Dielectrics.
`4.3.2.4 Low-Temperature-TEOS SiO2 Films as Intermeta/
`Dielectrics.
`4.3.25 Other Materials and Deposition Processes Used to Form lntermetal
`Dielectrics.
`
`4.4 PLANARIZATION OF INTERLEVEL DIELECTRIC LAYERS 199
`
`4.4.1 Terminology of Planarization in Multilevel Interconnects, 199
`4.4.1.1 Degree of P/anarization.
`4.4.1.2 The Need for Dielectric Planarization.
`4.4.1.3 The Price that Must be Paid as the Degree of Dielectric Planarizalion
`is Increased.
`4.4.1.4 Design Rules Related to lntermetal Dielectric-Formation and
`P/anarization Processes.
`4.4.2 Step Height Reduction of Underlying Topography as a Technique to
`Alleviate the Need for Planarization, 208
`4.4.2.1 Provide Substrate Topography that is Completely Planar.
`4.4.2.2 Provide a Planar Surface over Local Interconnect Levels.
`4.4.2.3. Minimize the Thickness of the Metal I Layer.
`4.4.2.4 Achieve Smoothing of Steps in DMJ by Sloping the Sidewalls of
`Metal-I Lines.
`4.4.3 Deposition of Thick CVD SiO2 Layers and Etching Back Without a
`Sacrificial Layer, 211
`4.4.4 Oxide Spacers, 212
`4.4.5 Polyimides as lntermetal Dielectrics, 214
`4.4.6 Planarizing by Use of Bias-Sputtered SiO2, 217
`4.4.7 CVD SiO2 and Bias-Sputter Etchback, 220
`4.4.8 Planarization by Sacrificial Layer Etchback, 222
`4.4.8.1 Degree of P/anarization Achleved by Sacrificial Etchback.
`4.4.8.2 Advantages of the Sacrificial Etchback Process.
`4.4.8.3 Sacrificial Etchback Process Problems.
`4.4.8.4 Alternative Sacrificial Etchback Processes.
`4.4.9 Spin-On Glass (SOG}, 449
`4.4.9.1 SOG Process Integration.
`4.4.9.2 The Etchback SOG Process.
`4.4.9.3 The Non-Etchback SOG Process.
`4.4.10 Electron-Cyclotron-Resonance Plasma CVD, 237
`4.4.11 Chemical-Mechanical Polishing, 238
`
`ONSEMI EXHIBIT 1008B, Page 10
`
`

`

`xiv
`
`CONTENTS
`
`4.5. METAL DEPOSITION AND VIA FILLING
`
`240
`
`4.5.1 Conventional Approach to Via Fabrication and Formation of Metal(cid:173)
`lo-Metal Contacts through the Vias, 240
`45.1.1 Design Rules of Multilevel Metal Systems which are Impacted by
`Conventional Via Processing Limitations.
`4.5.2 Advanced Via Processing (Vertical Vias and Complete Filling of Vias
`by Metal), 244
`45.2.1 Increases in Packing Density Resulting from Advanced Via
`Process Technology.
`4.5.3 Processing Techniques which Allow
`Vertical Vias to be Implemented, 245
`45.3.1 Required Degree of Via Filling by Plugs.
`4.5.4 CVD W Techniques for Filling Vertical Vias and Contact Holes, 245
`45.4.1 General Information on the CVD Tungsten Process.
`4.5.4.2 Blanket CVD Wand Etchback.
`4.5.4.3 Selective CVD W.
`4.5.5 Other CVD Via Filling Processes, 253
`4.5.5.1 Blanket CVD Polysi/icon and Etchbackfor Contact Hole Filling.
`4.5.5.2 Selective Deposition of Poly.
`4.5 5.3 Selectively Formed Silicide Contact Plugs.
`4.5.5.4 CVD Aluminum.
`4.5.6 Alternatives to CVD for Filling of Vias, 254
`4.5.6.1 Bias Sputtering of Al to Achieve Complete Filling of Via !lo/es.
`45.6.2 Laser Planarization of Al Films.
`4.5.6.3 Contact Hole and Via Filling by Selective Electroless Metal
`Deposition.
`4.5.7 Pillar Formation as an Alternative
`to Filling Contact Holes and Vias, 258
`
`4.6 FILLED GROOVES IN A DIELECTRIC LAYER
`
`259
`
`4.7 MANUFACTURING YIELD AND
`RELIABILITY ISSUES OF VLSI INTERCONNECTS
`
`260
`
`4.7.1 Factors Which Impact Manufacturing Yield, 261
`4.7.2 Multilevel Interconnect-Related Yield Issues, 261
`4.7.3 General Reliability Issues Associated with IC Interconnects, 264
`4.7.3.1 Electromigration.
`4.7.3.2 Electromigration at the Contacts.
`4.7.3.3 Stress-Induced Metal Cracks and Voids.
`4.7.3.4 Corrosion.
`4. 7.4 Reliability Issues Associated with Multilevel Interconnects, 268
`
`ONSEMI EXHIBIT 1008B, Page 11
`
`

`

`CONTENTS
`
`xv
`
`4.7.4.1 Hillock Formation and Prevention Measures.
`4.7.4.2 Dielectric Void Reliability Problems.
`
`4.8 PASSIVATION LAYERS
`
`273
`
`4.9 SURVEY OF MULTILEVEL METAL SYSTEMS
`
`276
`
`4.9.1 Bipolar Double-Level Metal Systems, 276
`4.9.2 CMOS Double-Level-Metal Systems, 277
`4.9.2.1 Non-Planarized DLM (2.0 µm CMOS).
`4.9.2.2. Non-Planarized DLM: CVD-W Metal (2.0-µm NMOS).
`4.9.2.3 Resist Etchback, Bias-Spullered SiO2, and SOG DLM for 1.5 µm
`CMOS.
`4.9.2.4 Non-Sacrificial layer Etchback DLM (1.0-µm CMOS).
`4.9.25 Alternative CMOS DLM Process with Ti:W!Mo as Metal I.
`4.9.2.6 DLM Processes for Submicron CMOS.
`4.9.3 Three-Level Metal Systems, 283
`4.9.4 Four-Level Metal Systems, 285
`
`4.10 SUMMARY OF MULTILEVEL INTERCONNECT
`TECHNOLOGY REQUIREMENTS FOR VLSI
`
`286
`
`REFERENCES
`
`287
`
`CHAP. 5
`
`- MOS DEVICES AND
`NMOS PROCESS INTEGRATION
`
`298
`
`5.1 MOS DEVICE PHYSICS
`
`298
`
`5.1.1 The Structure and Device Fundamentals of MOS Transistors, 298
`5.1.2 The Threshold Voltage of the MOS Transistor, 301
`5.1.3 Impact of Source-Body Bias on VT (Body Effect), 304
`5.1.4 Current-Voltage Characteristics of
`MOS Transistors, 305
`5.1.5 The Capacitances of MOS Transistors, 307
`
`5.2 MAXIMIZING DEVICE PERFORMANCE THROUGH DEVICE
`DESIGN AND PROCESSING TECHNOLOGY
`307
`
`5.2..1 Output Current (lo) and Transconductance (9m), 308
`5.2.2 Controlling the Threshold Voltage through Process
`and Circuit-Design Techniques, 309
`5.2.3 Subthreshold Currents (lost when VG < IVTI). 311
`
`ONSEMI EXHIBIT 1008B, Page 12
`
`

`

`xvi
`
`CONTENTS
`
`5.2.4 Switching Speed, 313
`5.2.5 Junction Breakdown Voltage (Drain-to-Substrate). 313
`5.2.6 Gate-Oxide Breakdown Voltage, 314
`5.2.7 High Field-Region Threshold-Voltage Value, 315
`
`5.3 THE EVOLUTION OF MOS TECHNOLOGY
`315
`(PMOS AND NMOS)
`
`5.3.1 Aluminum-Gate PMOS, 316
`5.3.2 Silicon-Gate MOS Technology, 318
`5.3.3 Reduction of Oxide-Charge Densities, 319
`5.3.4 Ion Implantation for Adjusting Threshold Voltage, 321
`5.3.5
`Isolation Technology for MOS, 323
`5.3.6 Short-Channel Devices, 323
`
`5.4 PROCESS SEQUENCE FOR FABRICATING NMOS
`INVERTERS WITH DEPLETION-MODE LOADS
`324
`
`5.4.1 Operation of an NMOS Inverter with a Depletion-Mode Load, 324
`5.4.2 Process Sequence of a Basic E-D NMOS IC Technology, 327
`5.4.2.1 Starting Material.
`5.4.2.2 Active Region and Field Region Definitions.
`5.4.2.3 Gate-Oxide Growth and Threshold-Voltage Adjust Implant
`5.4.2.4 Polysilicon Deposition and Patterning.
`5.4.25 Formation of the Source and Drain Regions.
`5.4.2.6 Contact Formation.
`5.4.2.7 Metallization Deposition and Pallerning.
`5.4.2.8 Passivation Layer and Pad Mask.
`
`5.5 SHORT-CHANNEL EFFECTS AND HOW THEY IMPACT MOS
`PROCESSING
`338
`
`5.5.1 Effect of Gate Dimensions on Threshold Voltage, 338
`55.1.1 Short Channel Threshold Voltage Effect.
`55.1.2 Narrow Gate-Width Effect on Threshold Voltage.
`5.5.2 Short-Channel Effects on Subthreshold Currents (Punchthrough
`and Drain-Induced Barner Lowertng), 341
`5.5.3 Short-Channel Effects on 1-V Characteristics, 343
`5.5.4 Summary of Short-Channel Effects
`on the Fabrication of MOS ICs, 346
`
`5.6 HOT-CARRIER EFFECTS IN MOSFETS
`
`348
`
`5.6.1 Substrate Currents Due to Hot Carriers, 349
`
`ONSEMI EXHIBIT 1008B, Page 13
`
`

`

`CON1ENI'S
`
`xvii
`
`5.6.2 Hot-Carrier Injection into the Gate Oxide, 350
`5.6.3 Device-Performance Degradation Due to Hot-Carrier Effects, 352
`5.6.4 Techniques for Reducing Hot-Carrier Degradation, 354
`5.6.5 Lightly Doped Drains, 354
`5.6.5.1 Drain Engineering for Optimum LDD Structures.
`5.6.5.2 Asymmetrical Characteristics of LDD MOSFETs.
`5.6.6 The Impact of IC Processing
`on Hot-Carrier Device Degradation, 361
`5.6.7 Hot-Carrier Effeqts in PMOS Transistors, 362
`5.6.8 Gate-Induced Drain-Leakage Current, 363
`
`REFERENCES
`
`363
`
`CHAP. 6 • CMOS PROCESS INTEGRATION
`
`368
`
`6.1
`
`INTRODUCTION TO CMOS TECHNOLOGY
`
`368
`
`6.1.1 The Power-Dissipation Crisis of VLSI and How CMOS Came to the
`Rescue, 368
`6.1.2 Historical Evolution of CMOS, 370
`6.1.3 Operation of CMOS Inverters, 373
`6.1.4 Advantages (and Disadvantages)
`of Modern CMOS Technologies, 376
`6.1 .4.1 Device/Chip Performance Advantages.
`6.1.4.2 Reliability Advantages of CMOS.
`6.1.4.3 Circuit Design Advantages of CMOS.
`6.1.4.4 Cost Analysis of CMOS.
`6.1.5 Disadvantages of CMOS, 380
`
`6.2 THE WELL CONTROVERSY IN CMOS
`
`381
`
`6.2.1 The Need for Wells in CMOS, 381
`6.2.2 p-Well CMOS, 383
`6.2.3 n-Well CMOS, 384
`6.2.4 CMOS on Epitaxial Substrates, 385
`6.2.5 Twin-Well CMOS, 387
`6.2.6 Retrograde-Well CMOS, 389
`6.2.7 Summary of CMOS Well-Technology Issues, 392
`
`6.3 p·CHANNEL DEVICES IN CMOS
`
`392
`
`6.3.1 PMOS Devices with n+-Polysilicon Gates, 392
`63.1.1 Punchthrough Susceptibility.
`
`ONSEMI EXHIBIT 1008B, Page 14
`
`

`

`xviii
`
`CONTENrS
`
`6.3.2 PMOS Devices with p+-Polysilicon Gates, 397
`6.3.3 Gate Materials having Symmetrical Work Functions (with Respect to
`both NMOS and PMOS Devices), 398
`
`6.4 LATCHUP IN CMOS
`
`400
`
`6.4.1 Parasitic pnpn Structures in CMOS Circuits, 400
`6.4.2 Circuit Behavior of pnpn Diodes, 402
`6.4.3 Device Physics Behavior of pnpn Diodes, 403
`6.4.4 Summary of Conditions That Must Exist
`in Order for Latchup to Occur, 406
`6.4.5 Circuit Behavior of Actual pnpn Structures in CMOS Circuits, 406
`6.4.5.1 Value of /3 in CMOS Vertical Parasitic Bipolar Transistors.
`6.45.2 Value of /3 in CMOS Lateral Parasitic Bipolar Transistors.
`6.4.6 Circuit and Device Effects that Induce Latchup, 408
`6.4.6.J An external stimulus forward-biases the emitter-base of one transistor,
`and its coiiector current then turns-on the second transistor.
`6.4.6.2 An external stimulus causes current to flow through both bypass
`resistors.forward-biasing one or both bipolar transistors.
`6.4.6.3 Current is shunted through one of the parasitic transistors by some
`degradation mechanism, and the resulting collector current flows
`through the bypass resistor of the second transistor and turns ii on.
`6.4.7 Test Methods for Characterizing Latchup, 410
`6.4.7.1 Modelling Latchup in CMOS Technology.
`6.4.8 Techniques for Reduction
`or Elimination of Latch up Susceptibility, 413
`6.4.8.1 Processing Techniques thot Reduce the Current Gains of the Parasitic
`Bipolar Transistors.
`6.4.8.2 Processing Techniques that Reduce Rsub and Rw or Eliminate the
`pnpn Structure.
`6.4.8.3 Circuit Layout Techniques used to Decouple Parasitic Bipolar
`Transistors.
`
`6.5 CMOS ISOLATION TECHNOLOGY
`
`419
`
`6.5.1 Trench Isolation for CMOS, 425
`6.5.2 Isolation by Selective-Epitaxial Grow1h for CMOS, 426
`
`6.6 CMOS PROCESS SEQUENCES
`
`428
`
`6.6.1 Basic n-Well CMOS Process Sequence, 428
`6.6.2 Twin-Well CMOS Process Sequence, 431
`6.6.2.1 Starting Material.
`6.6.2.2 Forming the Wells and Channel Stops.
`
`ONSEMI EXHIBIT 1008B, Page 15
`
`

`

`CONTENTS
`
`XIX
`
`6.6.2.3 Active and Field Region Definition.
`6.6.2.4 Gate Oxide Growth and Threshold Voltage Adjustment.
`6.6.25 Polysilicon Deposition and Patterning.
`6.6.2.6 Formation of the Source/Drain Regions.
`6.6.2.7 CVD Oxide Deposition and Contact Formation.
`6.6.2.8 Metal 1 Deposition and Patterning.
`6.6.2.9 lntermetal Dielectric Deposition/Planarization and Via Patterning.
`6.6.2.10 Metal 2 Deposition and Patterning.
`6.6.2.11 Passivation Layer Deposition and Patterning.
`
`6.7 MISCELLANEOUS CMOS TOPICS
`
`441
`
`6.7.1 Electrostatic Discharge Protection for CMOS, 441
`6.7.1.1 Diode Protection.
`6.7.1.2 Node-to-Node Punchthrough.
`6.7.1.3 Gate-Controlled Breakdown Structure.
`6.7.1.4 pnpn-Diode ESD Protection for Advanced CMOS Circuits.
`6. 7.2 Power Supply Voltage Levels for Future CMOS, 446
`6.7.3 Low-Temperature CMOS, 446
`6.7.4 Three-Dimensional CMOS, 447
`
`REFERENCES 447
`
`CHAPTER 7 " BIPOLAR AND
`BICMOS PROCESS INTEGRATION
`
`453
`
`7.1 BIPOLAR TRANSISTOR STRUCTURES
`FOR INTEGRATED CIRCUITS
`453
`
`7.1.1 The Transistor Action 454
`7.1.1.1 Basic Bipolar Transistor Physics.
`7.1.1.2 Bipolar Transistor Current Gain.
`7 .1.2 Integrated-Circuit Transistor Stuctures 458
`
`7.2 DIGITAL CIRCUITS USING BIPOLAR TRANSISTORS
`
`459
`
`7.2.1 Basic Bipolar-Transistor Inverter Circuits 459
`7.2.2 Bipolar Digital-Logic-Circuit Families 460
`
`7.3 MAXIMIZING BIPOLAR TRANSISTOR PERFORMANCE
`THROUGH DEVICE DESIGN & PROCESSING TECHNOLOGY
`
`464
`
`ONSEMI EXHIBIT 1008B, Page 16
`
`

`

`xx
`
`CONTE!IITS
`
`7.3.1 Current Gain 464
`7.3.2 Early Voltage 466
`7.3.3 High-Level Injection Effects (Kirk Effect) 467
`7.3.4 Operating-Voltage Limits in Bipolar Transistors 468
`7.3.4.1 Reachthrough Breakdown.
`7.3.4.2 Punchthrough Breakdown.
`7.3.4.3 Breakdown Voltage and High-Level Injection Limits in Advanced
`Bipolar Transistors.
`7.3.5 Parasitic Series Resistances in Bipolar Transistors 472
`7.3.5.1 Collector Series Resistance, Re.
`7.3.5.2 Base Series Resistance, RB,
`7.3.5.3 Base-Spreading Resistance, RB2 (and Emitter Current Crowding).
`7.3.5.4 Emitter Series Resistance, Rg
`7.3.6 Parasitic Junction Capacitances in Bipolar Transistors 475
`7.3.6.1 Storage Capacitances in Bipolar Transistors.
`7.3.7 Bipolar Transistor Unity-Gain Frequency, tr 477
`7.3.8 First Order npn Device Design 477
`7.3.9 Switching Speed Behavior in Bipolar !Cs 478
`7.3.9.J Propagation-Delay Time Calculation in Bipolar Transistors.
`7.3.9.2 Propagation Delay in Digital MOS versus Digital Bipolar Circuits.
`7.3.9.3 General Switching Speed Behavior of Digital Bipolar Circuits.
`
`7.4 NON-OXIDE-ISOLATED BIPOLAR npn TRANSISTOR
`STRUCTURES
`482
`
`7.4.1 Triple-Diffused (3D) Process 483
`
`7.5 STANDARD-BURIED-COLLECTOR PROCESS
`
`483
`
`7.5.1 Characteristics of npn Transistors Fabricated with the Standard(cid:173)
`Buried-Collector (SBC) Process 483
`7.5.1.1 Limitations of Junction-Isolated SBC Transistors for VLSI Circuits.
`7.5.2 Standard-Buried-Collector Process Flow 486
`7.5.2.J Starting Material.
`7.5.2.2 Buried Layer Formation.
`7.5.2.3 Epitaxial Growth.
`7.5.2,4 Formation of Isolation Regions.
`7.5.2.5 Deep-Collector Contact Formation (Optional).
`7.5.2.6 Base Region Formation.
`7.5.2.7 Emitter Region Formation.
`7.5.2.8 Contact and Interconnect Layer Formation.
`7.5.2.9 Washed Emillers.
`7.5.2.10 Schottky Contacts.
`
`7.6 OXIDE-ISOLATED BIPOLAR TRANSISTORS
`
`498
`
`ONSEMI EXHIBIT 1008B, Page 17
`
`

`

`CONTENTS
`
`xxi
`
`7.7 ADVANCED BIPOLAR TRANSISITOR STRUCTURES FOR
`VLSI AND ULSI
`500
`
`7.8 ADVANCED EMITTER STRUCTURES
`
`501
`
`7.8.1 Polysilicon Emitters 501
`7.8.1.1 Models that Describe Polysilicon-Emiller Behavior.
`7.8.1.2 Process Technology for Polysilicon-Emiller Fabrication.
`7.8.2 Heterojunction Bipolar Transistors (HBTs) 506
`
`7.9 SELF-ALIGNED BIPOLAR STRUCTURES
`
`51 0
`
`7.9.1 Double-Polysilicon Sett-Aligned Structures 51 O
`7.9.1.1 Limitations of Double-Polysilicon SA Structures.
`7.9.1.2 Current-Gain Degradation Due to Sidewall Injection in SA Bipolar
`Structures.
`7.9.1.3 Link-Up Region Formation.
`7.9.2 Single-Polysilicon Self-Aligned Bipolar Structures 516
`7.9.3 l;ildewall-Base-QQntact ,Structures (SICOS) 520
`
`7.10 TRENCH-ISOLATED BIPOLAR TRANSISTORS
`
`522
`
`7.11 BiCMOS TECHNOLOGY
`
`523
`
`7 .11.1 Device and Circuit Advantages of BiCMOS 524
`7.11.1.J Comparison of BiCMOs and CMOS Propagation Delay Times.
`7.11.1.2 Power Consumption of BiCMOS versus CMOS Gates.
`7.11.13 Capability of Providing Either TTL or ECL Outputs From a
`BiCMOS Chip.
`7.11.1.4 Process Complexity Increases Associated with BiCMOS.
`7.11.15 Extending Process Equipment Life by Fabricating BiCMOS.
`
`7.12 CLASSIFICATION OF BICMOS TECHNOLOGIES
`
`529
`
`7.12.1 Digital BiCMOS Technology 531
`7.12.1.1 Low-Cost Digital BiCMOS Technology.
`7.12.1.2 High-Performance Digital BiCMOS.
`7.12.13 Device-Design Issues Related to Optimizing a High-Performance
`Digital Modified-Twin-Well BiCMOS Process.
`7.12.1.4 An Example Process Sequence for Fabricating High-Performance 5-V
`Digital BiCMOS !Cs.
`7.12.2 Process Integration of Analog/Digital BiCMOS 543
`7.12.2.l Process-Integration Issues of Medium-Voltage Analog BiCMOS.
`7.12.2.2 An Example of an Analog/Digital BiCMOS Process.
`
`ONSEMI EXHIBIT 1008B, Page 18
`
`

`

`XXii
`
`CONTENTS
`
`7.12.3 BiCMOS Applications 551
`7.12.3.J Digital Logic Circuits and Gate Arrays.
`7.12.3.2 lnterface Driver Circuits.
`7.12.3.3 BiCMOS SRAMs.
`7.12.3.4 Analog/Digital Applications.
`7.13 Trends in BiCMOS Technology 556
`
`7.13 COMPLEMENTARY BIPOLAR (CB) TECHNOLOGY
`
`557
`
`REFERENCES
`
`560
`
`CHAP. 8 • SEMICONDUCTOR MEMORY PROCESS
`INTEGRATION
`
`557
`
`8.1 TERMINOLOGY OF SEMICONDUCTOR MEMORIES
`
`557
`
`8.1.1 Random-Access and Read-Only Memories
`(RAMs and ROMS) 568
`8.1.2 Semiconductor-Memory Architecture 568
`8.1.3 Semiconductor-Memory Types 570
`8.1.4 Read Access Times and Cycle Times in Memories 571
`8.1.5 Recently Introduced On-Chip Peripheral Circuits 571
`8.1.6 Logic-Memory Circuits 571
`
`8.2 STATIC RANDOM-ACCESS MEMORIES ($RAMS)
`
`572
`
`8.2.1 MOS SRAMs 575
`8.2.1 .1 Circuit Operation of MOS SRAM Celis.
`8.2.1.2 SRAM Processing and Cell Layout Issues.
`8.2.1.3. High-Valued Polysilicon Load-Resistors for MOS SRAMs
`8.2.2 Bipolar and BiCMOS SRAMS 584
`8.2.2.1 BiCMOS SRAMs.
`
`8.3 DYNAMIC RANDOM ACCESS MEMORIES (DRAMS)
`
`587
`
`8.3.1 Evolution of DRAM Technology 587
`8.3.1.1 One-Transistor DRAM Ceil Design.
`8.3 .J .2 Operation of the One-Transistor DRAM Cell.
`8.3.1.3 Writing, Reading, and Refreshing DRAM Cells.
`8.3.1.4 Quantity of Charge Stored on DRAM Cells and Their Capacitance.
`8.3.15 lJigh-Capacity (Hi-C) DRAM Celis.
`8.3.1.6 CMOS DRAMs.
`8.3.2 Design and Economic Constraints on Advanced DRAM Cells 597
`
`ONSEMI EXHIBIT 1008B, Page 19
`
`

`

`CONTENTS
`
`xxili
`
`8.3.3 Trench Capacitor DRAM Cells 600
`8.3.3.1 Trench Capacitor Processing for DRAMs.
`8.3.3.2 First Generation Trench Capacitor-based DRAM Cells.
`8.3.3.3 Trench Capacitor Structures with the Storage Electrode Inside the
`Trench (Inverted Trench Cell).
`8.3.3.4 Trench Capacitor Cells with the Access Transistor Stacked Above the
`Trench Capacitor.
`8.3.4 Stacked Capacitor DRAM Cells 609
`8.3.5 Soft-Error Failures in DRAMs 615
`8.3.5.1 Techniques Used to Reduce the Soft-Error Rates in DRAMs.
`8.3.6 The DRAM as a Technology Driver 618
`
`8.4 MASKED READ-ONLY MEMORIES (ROMs)
`
`619
`
`8.4.1 Masked ROM Implementation 620
`
`8.5 PROGAMMABLE ROMS (PROMS)
`
`621
`
`8.6 ERASABLE PROGRAMMABLE
`READ-ONLY MEMORIES (EPROMS)
`
`623
`
`8.7 ELECTRICALL Y·ERASABLE PROMS (EEPROMS)
`
`628
`
`8.7.1 MNOS-Based EEPROMs 628
`8.7.2 FLOTOX EEPROMs 629
`8.7.3 Textured-Polysilicon EEPROMs 631
`
`8.8 FLASH EEPROMS
`
`632
`
`8.9 NONVOLATILE FERROELECTRIC MOS RAMS
`
`635
`
`REFERENCES
`
`637
`
`CHAP. 9
`
`- PROCESS SIMULATION
`
`643
`
`9.1 OVERVIEW OF PROCESS SIMULATION 644
`
`9.1.1 Hierarchy of Simulation Tools for IC Development 644
`9.1.2 Benefits and Limitations of Process Simulation 645
`9.1.3 Overview of Process Simulators 647
`9.1.3.J Simulator Availability.
`9.1.4 General Aspects of Process Simulation 650
`9.1.4.1 Analytical and Numerical Methods of Solving the Equations that
`Describe Processes.
`
`ONSEMI EXHIBIT 1008B, Page 20
`
`

`

`xxiv
`
`CONTENT'S
`
`9.1.4.2 Phenomenological versus Physical Models.
`9.1.4.3 Gridding.
`9.1.4.4 Interfacing One Simulator with Another.
`
`9.2 ONE-DIMENSIONAL PROCESS SIMULATORS
`
`653
`
`9.2.1 SUPREM Ill (Stanford .University PRocess Engineering Model Ill) 655
`9.2.1.1 The Basic Operation and Capabilities of SUPREM lfl.
`9.2.1.2 Additional Comments on the Use of SUPREM Ill.
`9.2.2 SUPREM Ill Models: Ion Implantation 658
`9.2.3 SUPREM Ill Models: Diffusion in Silicon and SiO2, and Segregation
`Effects at the Si/SiO2 Interface 663
`9.2.3.1 Diffusion Models Used in SUP REM Ill.
`9.2.3.2 Modeling Low Impurity-Concentration (Intrinsic) Diffusion in Silicon.
`9.2.3.3 Modeling High-Impurity Concentration (Extrinsic) Diffusion in
`Silicon.
`9.2.3.4 Oxidation-Enhanced Diffusion Modeling in SU PREM III.
`9.2.3.5 Dopant Segregation Effects at the Si-Si02 Interface and Diffusion in
`Si02.
`9.2.4 SUPREM Ill Models: Thermal Oxidation of Silicon
`in One-Dimension 669
`9.2 .4.1 High Dopant-Concentration Cases.
`9.2.4.2 Modeling Other Factors Which Impact the Oxide Growth Rate.
`9.2.4.3 Accuracy of Modeling Oxide Growth with SU PREM Ill.
`9.2.5 SUPREM Ill Models: Epitaxial Growth 674
`9.2.6 SU PREM Ill Models: Deposition, Oxidation, and Material Properties
`of Polysilicon Films 675
`9.2.7 Creating a SUPREM Ill Input File 677
`9.2.8 PREDICT 679
`
`9.3
`
`INTRODUCTION TO 2-DIMENSIONAL PROCESS
`SIMULATORS
`680
`
`9.3.1 Classes of 2-Dimensional Process Simulators 683
`
`9.4 TWO-DIMENSIONAL DOPING-PROFILE AND OXIDATION
`PROCESS SIMULATORS
`684
`
`9.4.1 SUPRA (.Stanford .University .EBocess Analysis Program) 684
`9.4.1.1 SUPRA Ion Implantation Models.
`9.4.1.2 SUPRA Diffusion Models.
`9.4.J .3 SUPRA Oxidation Models.
`9.4.1.4 SUPRA Epitaxial Model.
`9.4.1.5 SUPRA Input File.
`9.4.2 SUPREM IV 687
`
`ONSEMI EXHIBIT 1008B, Page 21
`
`

`

`CONTENI'S
`
`XXV
`
`9.4.2.1 SU PREM IV Models of Diffusion.
`9.4.2.2 SU PREM IV Models of Oxidation.
`9.4.2.3 SUP REM JV Models of Ion Implantation, Epitaxy, Deposition, and
`Etching.
`9.4.2.4 SUPREM JV Input File Format.
`9.4.2.5 Comparison of SUPRA and SU PREM JV for 2-D Process
`Simulation.
`9.4.3 Two-Dimensional Simulation of Thermal Oxidation 690
`9.4.3.I Empirical Models of2-D Thermal Oxidation.
`9.4.3.2 Physical-Based Models of2-D Thermal Oxidation.
`
`9.5 TWO-DIMENSIONAL TOPOGRAPHY SIMULATORS
`
`696
`
`9.6 SAMPLE (SIMULATION ANO MODELING OF PROFILES IN
`LITHOGRAPHY ANO ETCHING) 697
`
`9.6.1 Simulating Optical Lithography Processes with SAMPLE 697
`9.6.1 ,1 Optical Imaging Subprogram.
`9.6.I .2 Resist Exposure Subprogram.
`9.6.1.3 Resist Development Subprogram.
`9.6.2 Simulating Etching and Deposition with SAMPLE 706
`9.6.3 Creating Input Files for SAMPLE 708
`
`9.7 OTHER 2·0 TOPOGRAPHY SIMULATORS
`
`710
`
`9.7.1 PROLITH 710
`9.7.2 DEPICT 710
`9.7.3 PROFILE 711
`9.7.4 SIMBAD 713
`9.7.5 SIMPL (Simulated Programs from the Layout) 714
`9.7.6 SIM PL-DIX 716
`9.7.7 Manufacturing-Based Process Simulators 718
`
`9.8 DEVICE SIMULATORS
`
`718
`
`9.8.1 Simulation of MOS Device Characteristics under Subthreshold and
`Linear Oporation (GEMINI) 719
`9.8.2 Simulation of MOS Device Under All de Operating Conditions
`(MINIMOS, CADDET, CANDE) 719
`9.8.3 Bipolar Device Simulators (SEDAN, BIPOLE) 720
`9.8.4 Combined MOS and Bipolar Device Simulators (PICSES, SIFCOD,
`PADRE, and FIELDAY) 721
`
`ONSEMI EXHIBIT 1008B, Page 22
`
`

`

`xxvl
`
`CONTENTS
`
`9.9 CIRCUIT SIMULATORS AND ELECTRICAL PARAMETER
`EXTRACTORS 723
`
`9.10 FUTURE CHALLENGES IN PROCESS SIMULATION
`
`723
`
`REFERENCES
`
`724
`
`APPENDIX A
`
`IC RESISTOR FABRICATION
`
`APPENDIX B PROPERTIES OF SILICON AT 300 °K
`
`APPENDIX C PHYSICAL CONSTANTS
`
`INDEX
`
`731
`
`737
`
`738
`
`739
`
`ONSEMI EXHIBIT 1008B, Page 23
`
`

`

`LIST OF TECHNICAL REVIEWERS
`
`Each of the chapters was reviewed for technical correctness. The following persons
`graciously undertook the review task for the chapters indicated:
`
`Chapter 2
`
`Dr. Joseph R. Monkowski
`Lam Research Corp.
`• CVD Division
`Fremont, CA
`
`Dr. Haiping Dun
`Intel Corp.
`Santa Clara, CA
`
`Chapter 3
`
`Dr. Robert S. Blewer
`Sandia National Laboratories
`Albuquerque, NM
`
`Dr. Stan Swirhun
`Honeywell SSPL
`Bloomington, MN
`
`Chapter 4
`
`Dr. Farhad K. Moghadam
`Intel Corp.
`Santa Clara, CA
`
`Dr. Terry Herndon
`MIT • Lincoln Laboratory
`Lexington, MA
`
`Chapter 5 Mr. Andrew R. Coulson
`TRW Electronic Systems Group
`Redondo Beach, CA
`
`Chapter 6
`
`Dr. John Y. Chen
`Boeing Electronics
`Seattle, WA
`
`Dr. Samuel T. Wang
`International CMOS Technology, Inc.
`San Jose, CA
`
`Chapter 8
`
`Chapter 9
`
`Professor Al F. Tasch, Jr.
`University of Texas
`Austin, TX
`
`Dr. Michael Kump
`Technology Modeling Associates, Inc.
`Palo Alto, CA
`
`xxvll
`
`ONSEMI EXHIBIT 1008B, Page 24
`
`

`

`PREFACE
`
`SILICON PROCESSING FOR THE VLSI ERA is a text designed to provide a
`comprehensive and up-to-date treatment of this important and rapidly changing field.
`T