Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC,
`Petitioner
`v.
`
`GREENTHREAD LLC,
`Patent Owner
`
`U.S. PATENT NO. 9,190,502
`
`Case IPR2024-00265
`
`DECLARATION OF TRAVIS BLALOCK, PH.D.
`
`ONSEMI EXHIBIT 1003, Page 1
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`

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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
`
`TABLE OF CONTENTS
`
`IV.
`V.
`VI.
`
`BACKGROUND AND QUALIFICATIONS ................................................. 4
`I.
`II. MATERIALS AND OTHER INFORMATION CONSIDERED ................... 8
`III. UNDERSTANDING OF PATENT LAW ....................................................11
`A.
`Claim Construction..............................................................................11
`B.
`Obviousness .........................................................................................12
`C.
`Cumulativeness ...................................................................................14
`SUMMARY OF OPINIONS .........................................................................15
`OVERVIEW OF THE TECHNOLOGY .......................................................16
`THE ’502 PATENT .......................................................................................19
`A.
`Claims ..................................................................................................19
`B.
`Summary of the Specification .............................................................20
`C.
`Summary of the Prosecution History ..................................................23
`VII. LEVEL OF ORDINARY SKILL IN THE ART ...........................................23
`VIII. CLAIM CONSTRUCTION ..........................................................................25
`IX. OVERVIEW OF THE PRIOR ART .............................................................26
`A.
`Payne ...................................................................................................26
`B.
`Sakai ....................................................................................................28
`C.
`Kawagoe ..............................................................................................29
`D. Wolf .....................................................................................................30
`E.
`Parrillo .................................................................................................31
`F.
`Silverbrook ..........................................................................................31
`SPECIFIC GROUNDS FOR PETITION ......................................................32
`
`X.
`
`Active 105207896.2
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`A.
`
`B.
`
`C.
`
`D.
`
`3.
`
`4.
`
`5.
`
`6.
`
`Ground I: .............................................................................................32
`1.
`Independent Claim 7 .................................................................32
`2.
`Claim 12: “The semiconductor device of claim 7 wherein the
`semiconductor device is an image sensor device.” ...................60
`Ground II .............................................................................................62
`1.
`Independent Claim 7 .................................................................62
`2.
`Claim 8: “The semiconductor device of claim 7 wherein said
`first and second static unidirectional electric fields are adapted
`to respective grading of dopants to aid movements of carriers in
`respective active regions.” ........................................................89
`Claim 9: “The semiconductor device of claim 7 wherein the
`semiconductor device is a central processing unit (CPU).” .....91
`Claim 10: “The semiconductor device of claim 7 wherein the
`semiconductor device is a DRAM device.” ..............................91
`Claim 11: “The semiconductor device of claim 7 wherein the
`semiconductor device is a flash memory device.” ....................92
`Claim 12: “The semiconductor device of claim 7 wherein the
`semiconductor device is an image sensor device.” ...................94
`Ground III ............................................................................................96
`1.
`Claim 9: “The semiconductor device of claim 7 wherein the
`semiconductor device is a central processing unit (CPU).” .....96
`Claim 10: “The semiconductor device of claim 7 wherein the
`semiconductor device is a DRAM device.” ..............................98
`Claim 11: “The semiconductor device of claim 7 wherein the
`semiconductor device is a flash memory device.” ....................99
`Ground IV ..........................................................................................101
`1.
`Claim 8: “The semiconductor device of claim 7 wherein said
`first and second static unidirectional electric fields are adapted
`
`2.
`
`3.
`
`Active 105207896.2
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`to respective grading of dopants to aid movements of carriers in
`respective active regions.” ......................................................101
`Grounds V/VI ....................................................................................109
`E.
`XI. CUMULATIVENESS .................................................................................113
`XII. CONCLUSION ............................................................................................117
`
`Active 105207896.2
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
`
`I, Dr. Travis Blalock, declare as follows:
`
`1.
`
`2.
`
`My name is Travis Blalock.
`
`I have been retained as an expert witness on behalf of Semiconductor
`
`Components Industries, LLC (“onsemi” or “Petitioner”) for the above-captioned
`
`Petition for Inter Partes Review (“Petition”) of U.S. Patent No. 9,190,502 (the “’502
`
`Patent”) (EX1001). I am being compensated for my time in connection with this
`
`Petition at my standard consulting rate of $450 per hour. My compensation is not
`
`affected by the outcome of this matter.
`
`3.
`
`I have been asked to provide my opinions regarding whether claims 7-
`
`12 of the ’502 Patent (the “Challenged Claims”) are invalid as obvious to a person
`
`having ordinary skill in the art at the time of the alleged invention.
`
`4.
`
`The ’502 Patent issued on November 17, 2015, from Application No.
`
`14/515,584, filed on October 16, 2014. The ’502 Patent claims priority to
`
`Application No. 10/934,915, filed on September 3, 2004.
`
`5.
`
`I am not currently, and have not at any time in the past been, an
`
`employee of onsemi. I have no financial interest in onsemi.
`
`I.
`
`BACKGROUND AND QUALIFICATIONS
`6.
`I am currently an Associate Professor at the University of Virginia. I
`
`served as an Associate Professor from 1998 until 2013 when I moved to a non-
`
`resident Associate Professor position so I could lead a Handheld Ultrasound R&D
`
`4
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`team for Analogic, Inc. I earned my Bachelor of Science and Master of Science in
`
`Electrical Engineering from the University of Tennessee at Knoxville in 1985 and
`
`1988 respectively. I earned my Ph.D. from Auburn University in 1991. The primary
`
`emphasis of my doctoral research was CMOS analog and digital integrated circuit
`
`design.
`
`7.
`
`From 1991 through August 1998, I worked at Hewlett Packard
`
`Laboratories, first as a Member of the Technical Staff, and then as a Principal
`
`Scientist. My work at Hewlett Packard Laboratories involved design and
`
`implementation of digital and analog integrated circuits. I was the principal architect
`
`and designer of integrated circuits having a diverse range of applications, including
`
`CMOS analog signal processing integrated circuits for mass storage devices and
`
`optoelectronic image-acquisition and processing integrated circuits. I also have
`
`experience with software and custom design tools that allow for improved analysis,
`
`modeling, and simulation of integrated circuit analysis and design.
`
`8. While I was employed at Hewlett-Packard Laboratories (now Keysight
`
`Laboratories) I was the lead designer on several mixed-signal CMOS chips. One of
`
`these was an optical imaging and signal processing prototype integrated circuit. The
`
`chip measures position with an accuracy of better than 100 µm over 10 inches by
`
`cross-correlating past and present images acquired by the integrated photo-array.
`
`The photodetector design was based on an understanding of dopant profiles and the
`
`5
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`resulting effects on detector sensitivity. This was incorporated into the detection
`
`circuit design to optimize response. The chip has a 2048 element 25,000
`
`frame/second photoreceiver array coupled with an analog signal processing cross-
`
`correlation array. The array performs a set of 9 nearest-neighbor cross-correlations
`
`between the two images at a total computation throughput of 1.5 billion operations
`
`per second. Over 100 million second generation versions of this chip have been sold
`
`and the architecture forms the core of most optical mice.
`
`9.
`
`I was also the technical lead in the design of a 1024 x 768 silicon
`
`backplane ferro-electric liquid-crystal microdisplay. The chip also includes 1024
`
`compact, offset-corrected column amplifiers and high-speed analog signal
`
`distribution. Both of the above chip designs were the highest density mixed-signal
`
`integrated circuits ever produced within Hewlett-Packard (at that time) and were
`
`fully functional at first silicon. I was also directly involved in the testing and
`
`verification of these chips in the laboratory.
`
`10. At the University of Virginia, I led research in design of low-power
`
`mixed-signal integrated circuits. This work covered a broad range of application
`
`areas including medical ultrasound, subthreshold RFID for mobile health
`
`applications, wearable sensors, custom RFID for bio-tracking of plaque propagation,
`
`infrared imaging, cryptographic hardening, and sensors for CMOS process
`
`reliability.
`
`6
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`11. More recently, I have led the development of a CMOS 600 channel low
`
`power medical imaging front-end integrated circuit. The chip simultaneously
`
`amplifies, filters, and digitizes signals from 600 independent ultrasound transducer
`
`elements. The chip development was part of an independent medical ultrasound
`
`startup (PocketSonics, Inc.) I founded which was acquired by Analogic, Inc in 2013.
`
`This work led to the development and release of a handheld medical ultrasound
`
`product by Analogic, Inc. This device was powered by a lithium-ion battery and
`
`included circuits to manage high peak currents, pulse-width modulation for
`
`controlled power delivery, charge management, and battery protection circuits.
`
`12.
`
`I am currently a collaborator with the Integrated Electromagnetics,
`
`Circuits, and Systems Lab at the University of Virginia. In this group we design a
`
`variety of high frequency RF integrated circuits and merged RF/Optical circuits. Of
`
`particular interest are low power wake-up receivers, clock recovery, and high
`
`efficiency power amps for battery powered RF circuits.
`
`13.
`
`I have written widely in the field of electrical engineering, including
`
`several editions of a textbook that is used across the world to teach principles of
`
`microelectronic circuit design to undergraduate and graduate students. I have
`
`authored or co-authored over 50 journal and conference papers. My textbook
`
`includes discussions of the solid-state physics needed to understand the operation of
`
`semiconductor diodes, BJT transistors, and CMOS transistors. In the course of
`
`7
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`integrated circuit design teaching and practice, particularly the low noise, high
`
`sensitivity circuits I have focused on, it has been essential to understand the device
`
`physics and how neighboring devices may interact to understand subtle effects that
`
`impact the success of both industrial and academic designs.
`
`14.
`
`I have contributed to or consulted on the design, fabrication, and/or
`
`operation of integrated circuits, including microelectronic integrated circuits, for
`
`organizations such as Hewlett-Packard, NASA Langley Research Center, Agilent
`
`Technologies, Displaytech, PocketSonics, and Analogic.
`
`15.
`
`I am a named inventor on at least 27 U.S. patents. Several of these
`
`concern analog circuitry or semiconductor design, including guard rings, charge
`
`storage devices, and photosensors.
`
`16. My qualifications and publications are set forth more fully in my
`
`curriculum vitae, attached (EX1004).
`
`II. MATERIALS AND OTHER INFORMATION CONSIDERED
`17.
`In forming the opinions expressed in this Declaration, I relied upon my
`
`education and experience in the relevant field of the art and have considered the
`
`viewpoint of a person having ordinary skill in the art (POSITA) at the time of the
`
`alleged invention.
`
`18.
`
`I have considered the materials referenced herein, including the ’502
`
`Patent (EX1001), the file history of the ’502 Patent (EX1002), the parent and related
`
`8
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`ONSEMI EXHIBIT 1003, Page 9
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`applications, the file histories of the parent and related applications, the Petition, and
`
`other documents listed in the Exhibit List of the Petition, including:
`
`Description
`U.S. Patent No. 4,684,971 to Payne
`(“Payne”) (EX1005)
`U.S. Patent No. 4,907,058 to Sakai
`(“Sakai”) (EX1006)
`
`U.S. Patent No. 6,043,114 to Kawagoe,
`et al. (“Kawagoe”) (Ex.1007)
`
`Stanley Wolf and Richard N. Tauber,
`Silicon Processing For The VLSI Era,
`Vol 1, Lattice Press (2000) (“Wolf.1”)
`(EX1008A)
`Stanley Wolf and Richard N. Tauber,
`Silicon Processing For The VLSI Era,
`Vol. 2, Lattice Press (2000) (“Wolf.2”)
`(EX1008B)
`Stanley Wolf and Richard N. Tauber,
`Silicon Processing For The VLSI Era,
`Vol. 3, Lattice Press (2000) (“Wolf.3”)
`(EX1008C)
`Stanley Wolf and Richard N. Tauber,
`Silicon Processing For The VLSI Era,
`Vol. 4, Lattice Press (2000) (“Wolf.4”)
`(EX1008D)
`U.S. Patent No. 4,160,985 to Kamins et
`al. (“Kamins”) (EX1009)
`U.S. Patent No. 4,014,522
`(“Jastrzebski”) (EX1010)
`U.S. Patent Application Publication No.
`2003/0042511 (“Rhodes”) (Ex.
`1011)
`U.S. Patent Application Publication No.
`2002/0102783 (“Fujimoto”) (EX1012)
`
`Date of Public Availability
`Filed March 13, 1981 and issued
`August 4, 1987.
`Filed July 1, 1988 (with priority to
`July 3, 1987) and issued on March 6,
`1990.
`Filed on September 22, 1997 (with
`priority to July 28, 1995) and issued
`on March 28, 2000.
`Published and publicly available no
`later than 2002.
`
`Published and publicly available no
`later than 2002.
`
`Published and publicly available no
`later than 2002.
`
`Published and publicly available no
`later than 2002.
`
`Filed November 25, 1977 and issued
`July 10, 1979.
`Filed March 24, 1982 and issued on
`November 6, 1984.
`Filed on August 30, 2001.
`
`Filed on October 24, 2001 (with
`priority to October 26, 2000).
`
`9
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`Description
`Wang and Agrawal, Single Event Upset:
`An Embedded Tutorial, 21st Intl Conf
`on VLSI Design, IEEE 2008 (“Wang”)
`(EX1013)
`U.S. Patent Application Publication No.
`2004/0063288 (“Kenney”) (EX1022)
`Jaeger, Introduction to Microelectronic
`Fabrication, Vol. V, Addison-Wesley
`Modular Series on Solid State Devices
`(1988) (“Jaeger”) (EX1023)
`U.S. Patent No. 4,435,896 (“Parrillo”)
`(EX1025)
`
`L.C. Parrillo, R.S. Payne et al., Twin-
`Tub CMOS - A Technology for VLSI
`Circuits, IEEE 1980 (“Parrillo2”)
`(EX1026)
`U.S. Patent Application Publication
`No. 2007/0045682 to Hong et al.
`(“Hong”) (EX1027)
`The Oxford American Dictionary and
`Language Guide, Oxford University
`Press (1996) (EX1028)
`U.S. Patent Application Publication No.
`2003/0183856 to Wieczorek
`(“Wieczorek”) (EX1038)
`Rabaey et al., Digital Integrated
`Circuits, A Design Perspective, Prentice
`Hall Electronics and VLSI Series (2003)
`(“Rabaey”) (EX1041)
`Sze, Semiconductor Devices Physics
`and Technology, 2d Ed., John Wiley
`& Sons (2002) (EX1042)
`Maziasz and Hayes, Layout
`Minimization of CMOS Cells, Kluwer
`Academic Publishers (1992)
`(“Maziasz”) (EX1044)
`U.S. Patent No. 5,986,924 to Yamada
`
`Date of Public Availability
`Published and publicly available in
`2008.
`
`Published and publicly available in
`2004.
`Published and publicly available in
`1988.
`
`Filed on June 29, 1983 (with priority
`to December 7, 1981) and issued on
`March 13, 1984.
`Published and publicly available in
`1980.
`
`Filed on August 31, 2005.
`
`Published and publicly available in
`1996.
`
`Filed on October 29, 2002 (with
`priority to March 28, 2002).
`
`Published and publicly available in
`2003.
`
`Published and publicly available in
`2002.
`
`Published and publicly available in
`1992.
`
`Filed June 24, 1998 (with priority to
`
`10
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`Description
`(“Yamada”) (EX1046)
`
`U.S. Patent No. 6,614,560 to
`Silverbrook (“Silverbrook”) (EX1048)
`Wong et al., “CMOS Active Pixel
`Image Sensors Fabricated Using a 1.8V,
`0.25 um CMOS Technology.”
`(EX1049)
`
`Date of Public Availability
`June 25, 1997) and issued
`November 16, 1999.
`Filed July 10, 1998 and issued
`September 2, 2003
`Published and publicly available in
`1998.
`
`19.
`
`The references listed above include prior art to the ’502 Patent which is
`
`entitled to a priority date not earlier than September 3, 2004. I am also relying on
`
`the declaration of Dr. Sylvia Hall-Ellis (EX1050) who opined that the Wolf
`
`reference was publicly available before September 3, 2004.
`
`III. UNDERSTANDING OF PATENT LAW
`20.
`I am not an attorney. For purposes of this declaration, I have been
`
`informed about certain aspects of the law that are relevant to my opinions. My
`
`understanding of the law is as listed below.
`
`A.
`21.
`
`Claim Construction
`I understand that in an IPR petition filed after November 13, 2018, a
`
`claim must be construed under the Phillips standard. Under that standard, words of
`
`a claim are given their plain and ordinary meaning as understood by a POSITA at
`
`the time of invention, in light of the specification and prosecution history, unless
`
`those sources show an intent to depart from such meaning, as well as pertinent
`
`evidence extrinsic to the patent.
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`B.
`22.
`
`Obviousness
`I have been informed and understand that a patent claim can be
`
`considered to have been obvious to a POSITA at the time the application was filed.
`
`This means that, even if all of the requirements of a claim are not found in a single
`
`prior art reference, the claim is not patentable if the differences between the subject
`
`matter in the prior art and the subject matter in the claim would have been obvious
`
`to a POSITA at the time the application was filed.
`
`23.
`
`I have been informed and understand that a determination of whether a
`
`claim would have been obvious should be based upon several factors, including,
`
`among others:
`
` the level of ordinary skill in the art at the time the application was filed;
`
` the scope and content of the prior art; and
`
` what differences, if any, existed between the claimed invention and the
`prior art.
`I have been informed and understand that the teachings of two or more
`
`24.
`
`references may be combined in the same way as disclosed in the claims, if such a
`
`combination would have been obvious to a POSITA. In determining whether a
`
`modification or combination based on either a single reference or multiple references
`
`would have been obvious, it is appropriate to consider at least the following factors:
`
` whether the teachings of the prior art references disclose known concepts
`combined in familiar ways, which, when combined, would yield
`predictable results;
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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` whether a POSITA could implement a predictable variation, and would
`see the benefit of doing so;
`
` whether the claimed elements represent one of a limited number of
`known design choices, and would have a reasonable expectation of
`success by a POSITA;
`
` whether a POSITA would have recognized a reason to combine known
`elements in the manner described in the claim;
`
` whether there is some teaching or suggestion in the prior art to make the
`modification or combination of elements claimed in the patent; and
`
` whether the innovation applies a known technique that had been used to
`improve a similar device or method in a similar way.
`I understand that a POSITA has ordinary creativity, and is not an
`
`25.
`
`automaton.
`
`26.
`
`I understand that in considering obviousness, it is important not to
`
`determine obviousness using the benefit of hindsight derived from the patent being
`
`considered.
`
`27.
`
`I understand that prior art to the ’502 Patent includes patents and printed
`
`publications in the relevant art that predate the priority date of the ’502 Patent.
`
`28.
`
`I understand
`
`that certain
`
`factors—often called “secondary
`
`considerations”—may support or rebut an assertion of obviousness of a claim. I
`
`understand that such secondary considerations include, among other things,
`
`commercial success of the alleged invention, skepticism of those having ordinary
`
`skill in the art at the time of the alleged invention, unexpected results of the alleged
`
`invention, any long-felt but unsolved need in the art that was satisfied by the alleged
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`invention, the failure of others to make the alleged invention, praise of the alleged
`
`invention by those having ordinary skill in the art, and copying of the alleged
`
`invention by others in the field.
`
`29.
`
`I further understand that there must be a nexus—a connection—
`
`between any such secondary considerations and the alleged invention. I also
`
`understand that contemporaneous and independent invention by others is a
`
`secondary consideration tending to show obviousness.
`
`C.
`30.
`
`Cumulativeness
`I understand that, under 35 U.S.C. § 325(d), the Board may exercise its
`
`discretion to deny institution of inter partes review if the IPR petition presents the
`
`same or substantially the same prior art or arguments that were previously presented
`
`to the Patent Office.
`
`31. When deciding whether to exercise its discretion to deny institution
`
`under 35 U.S.C. § 325(d), I understand the Board weighs several non-exclusive
`
`factors, including:
`
`(a)
`
`the similarities and material differences between the asserted art and
`
`the prior art involved during examination;
`
`(b)
`
`the cumulative nature of the asserted art and the prior art evaluated
`
`during examination;
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`(c)
`
`the extent to which the asserted art was evaluated during examination,
`
`including whether the prior art was the basis for rejection;
`
`(d)
`
`the extent of the overlap between the arguments made during
`
`examination and the manner in which Petitioner relies on the prior art or
`
`Patent Owner distinguishes the prior art;
`
`(e)
`
`whether Petitioner has pointed out sufficiently how the Examiner erred
`
`in its evaluation of the asserted prior art; and
`
`(f)
`
`the extent to which additional evidence and facts presented in the
`
`Petition warrant reconsideration of the prior art or arguments.
`
`IV.
`
`SUMMARY OF OPINIONS
`32.
`It is my opinion that claims 7 and 12 are disclosed or, at a minimum,
`
`rendered obvious by Payne (Ground I).
`
`33.
`
`It is my opinion that claims 7-12 are rendered obvious by Sakai in
`
`combination with Kawagoe (Ground II).
`
`34.
`
`It is my opinion that claims 9-11 are rendered obvious by Payne in
`
`combination with Wolf (Ground III).
`
`35.
`
`It is my opinion that claim 8 is rendered obvious by Payne in
`
`combination with Parrillo (Ground IV).
`
`36.
`
`It is my opinion that claim 12 is rendered obvious by Payne in
`
`combination with Silverbrook (Ground V).
`
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
`
`37.
`
`It is my opinion that claim 12 is rendered obvious by Sakai in
`
`combination with Kawagoe and Silverbrook (Ground VI).
`
`38.
`
`It is my opinion that none of the prior art references relied on in this
`
`petition are cumulative with prior art considered by the Examiner during prosecution
`
`of the ’502 Patent.
`
`39.
`
`It is my opinion that for purposes of this proceeding, the claim terms
`
`need not be construed to resolve the prior art issues presented in this Petition.
`
`V.
`
`OVERVIEW OF THE TECHNOLOGY
`40. A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a
`
`transistor that switches from an OFF state to an ON state when a voltage is applied
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`to a gate terminal. EX1008B, 402. In the ON, or active state, current flows from a
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`source to a drain through a channel region (the length of such channel region is
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`labelled “L” below). The channel region is under the gate and gate oxide, and
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`between the source and drain.
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`EX1008B, FIG. 5-1 (annotations in red);1 id., 298-301, FIGS. 5-2, 6-4. The
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`combination of the source, drain, and channel regions form the active region of a
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`transistor. EX1008B, 299-300 (“The top surface of the [substrate] body consists of
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`active or transistor regions as well as passive or (field) regions. The active regions
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`are those in which transistor action occurs; i.e., the channel and the heavily doped
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`source and drain regions.”), FIG. 5-2, 382, FIG. 6-8(c), 387, FIG. 6-10; EX1008C,
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`525, FIG. 8-1(e).
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`41. MOSFETs are characterized by the material used in the source and
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`drain. A MOSFET with source/drain regions made from “p-type” material in such
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`areas (as shown in the figure above, labelled “p+”) is known as a PMOS or p-FET,
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`while a MOSFET with source/drain regions made from “n-type” material (“n+”) in
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`1 All emphases and annotations added unless otherwise noted.
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`Declaration of Dr. Blalock for Inter Partes Review of U.S. Patent No. 9,190,502
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`such areas is known as a NMOS or n-FET. In the mid-1980s, Complementary MOS
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`(CMOS) devices became popular, which have both PMOS (p-FET) and NMOS (n-
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`FET) transistors on the same device. In such devices, the active areas (and associated
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`transistors) are generally formed in regions called “wells,” which have opposite
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`dopant type to the dopants of the source/drain, as illustrated below.
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`EX1008A, FIG. 16-28 (annotations in red).
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`42.
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`Impurities known as “dopants” are added to the active areas and wells
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`to add charge carriers and tailor the electrical properties of these regions such as their
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`conductivity. Charge carriers can be electrons or holes. EX1008C, 86. When a
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`region is doped with p-type dopants, the holes are majority carriers and the electrons
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`are minority carriers. EX1008C, 86. When a region is doped with n-type dopants,
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`the electrons are majority carriers and the holes are minority carriers. EX1008C, 86.
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`43. A “dopant profile” refers to the “map” of concentration of dopants over
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`a doped region and, in certain simplified scenarios, can be expressed as a function
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`of depth. For example, a dopant concentration that does not change with depth is a
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`uniform concentration. A non-uniform dopant concentration that varies for example
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`with depth, e.g., increases or decreases with depth, is a non-uniform dopant
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`concentration called “graded.” A graded dopant concentration that peaks at some
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`depth of the doped region(s) instead of at the top or bottom of the doped region(s) is
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`called “retrograde.” In my opinion, all such doping profiles were known in the art.
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`VI. THE ’502 PATENT
`44.
`The ’502 Patent issued on November 17, 2015 from Application No.
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`14/515,584, filed on October 16, 2014. The ’502 Patent claims priority to
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`Application No. 10/934,915, filed on September 3, 2004. EX1001, cover.
`
`A.
`45.
`
`Claims
`The ’502 Patent has 12 claims, including two independent claims
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`numbered 1 and 7. EX1001, 4:23-5:12. Claims 7-12 are the Challenged Claims.
`
`46.
`
`Exemplary Claim 7 is reproduced below:
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`7. A semiconductor device comprising:
` a surface layer;
`a substrate;
`an active region including a source and a drain, disposed
`on one surface of said surface layer;
`a single drift layer disposed between the other surface of
`said surface layer and said substrate, said drift layer
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`having a graded concentration of dopants
`generating a first static unidirectional electric drift
`field to aid the movement of minority carriers from
`said surface layer to said substrate; and
`at least one well region disposed in said single drift layer,
`said well region having a graded concentration of
`dopants generating a second static unidirectional
`electric drift field to aid the movement of minority
`carriers from said surface layer to said substrate.
`
`EX1001, 4:52-67.
`
`B.
`47.
`
`Summary of the Specification
`The ’502 Patent is directed to “grading the dopant concentration” in
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`certain region(s) of a semiconductor device. EX1001, Abstract. In particular, the
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`Challenged Claims claim that a single drift layer and a well region of a
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`semiconductor device have graded dopant concentrations to aid movement of
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`minority carriers from the surface layer to the substrate. Id., Claim 7. I understand
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`that Patent Owner has previously asserted that one or more claims of the ’502 Patent
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`were infringed by CMOS products in another district court case (Greenthread, LLC
`
`v. Intel Corporation, Dell Inc., and Dell Technologies Inc., Civil Action No. 6:22-
`
`cv-105 in the Western District of Texas, filed January 27 2022 (“Intel Litigation”).
`
`In my opinion, the references relied on in the Petition (i.e., Payne, Sakai, Kawagoe,
`
`Wolf, Parrillo, and Silverbrook) are also directed to CMOS devices and technology.
`
`48. According to the ’502 Patent, the figure below “illustrates the relative
`
`doping profiles of emitter, base and collector for the two most popular bipolar
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`junction transistors: namely, uniform base (‘A’) [(red)] and graded base (‘B’)
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`[(green)].” EX1001, 2:17-19.
`
`Id., FIG. 1 (“Prior Art”).22 The ’502 Patent states that such “uniform base” and
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`“graded base” bipolar junction transistors existed in the prior art. Id.
`
`49.
`
`The ’502 Patent alleges, without support, that “[r]etrograde wells have
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`been attempted, with little success, to help improve soft error immunity in SRAMs
`
`and visual quality in imaging circuits.” EX1001, 1:63-65. The ’502 Patent further
`
`states that “[r]etrograde and halo wells have also been attempted to improve refresh
`
`time in DRAMs (dynamic random-access memories), as well as, reducing dark
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`current (background noise) and enhance RGB (Red, Green, Blue) color resolution
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`in digital camera ICs.” Id., 2:1-6.
`
`2 All colors and colored annotations to figures added.
`
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`50.
`
`The ’502 Patent also explains that “these techniques” in the prior art
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`“either divert the minority carriers away from the active regions of critical charge
`
`storage nodes at the surface, or, increase minority carrier density locally as the
`
`particular application requires.” Id., 2:6-9.
`
`51.
`
`In my opinion, the only description of graded dopant concentrations
`
`and purported carrier movement in CMO