US009190502B2
`
`a2) United States Patent
`US 9,190,502 B2
`(10) Patent No.:
`*Nov. 17, 2015
`(45) Date of Patent:
`Rao
`
`
`(54) SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`
`(71) Applicant: G. R. Mohan Rao, Allen, TX (US)
`
`(72)
`
`Inventor: G.R. Mohan Rao, Allen, TX (US)
`:
`(73) Assignee: Greenthread, LLC,Dallas, TX (US)
`(*) Notice:
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`This patent is subject to a terminal dis-
`claimer.
`
`(21) Appl. No.: 14/515,584
`(22)
`Filed:
`Oct. 16,2014
`(65)
`Prior Publication Data
`US 2015/0035004 Al
`Feb. 5, 2015
`
`Related U.S. Application Data
`(60) Continuation of application No. 13/854,319, filed on
`Apr. 1, 2013, now abandoned, whichis a continuation
`of application No. 11/622,496, filed on Jan. 12, 2007,
`now Pat. No. 8,421,195, which is a division of
`application No. 10/934,915, filed on Sep. 3, 2004, now
`abandoned.
`
`(S51)
`
`Int. Cl.
`HOLL 21/02
`HOLL 29/739
`HOLE 27/115
`HOIL 29/36
`HOIL 27/02
`HOIL 27/108
`
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`(2006.01)
`
`(52) U.S. CL
`CPC...... HOLL 29/7395 (2013.01); HOLE 27/1152]
`(2013.01); HOIL 27/11524 (2013.01); HOIL
`29/36 (2013.01); HOLL 27/0214 (2013.01);
`HOIL 27/10844 (2013.01)
`(58) Field of Classification Search
`CPC ciccecseccseescrssenseseectessssnecnseesenseneees HO1L 29/7395
`USPC.
`cecssstssssssssssssssessssssecsesnsssensiessseeeee 438/37
`See application file for complete search history.
`References Cited
`
`(56)
`
`U.S, PATENT DOCUMENTS
`4,160,985 A *
`7/1979 Kaminsetal. ........000. 257/443
`2001/0040622 Al* 11/2001 Maruyama.........
`
`2/2003 Huetinget al. ou... 330/57
`2003/0030488 Al*
`* cited by examiner
`.
`Primary Examiner — Ajay I Arora
`(74) Attorney, Agent, or Firm — Howison & Arnott, LLP
`
`(57)
`ABSTRACT
`Most semiconductor devices manufactured today, have uni-
`form dopant concentration, either in the lateral or vertical
`device active (and isolation) regions. By grading the dopant
`concentration, the performance in various semiconductor
`devices can be significantly improved. Performance improve-
`ments can be obtained in application specific areas like
`increase in frequency of operation for digital logic, various
`power MOSFETand IGBTICS, improvementin refresh time
`for DRAM’s, decrease in programmingtime for nonvolatile
`memory, better visual quality including pixel resolution and
`colorsensitivity for imaging ICs, better sensitivity for varac-
`tors in tunablefilters, higher drive capabilities for JFET’s, and
`a host of other applications.
`
`12 Claims, 10 Drawing Sheets
`
`AccessTransistor
`
`Storage Capacitor or
`nsor element
`
`
`
`
` Ht
`
`Graded dopant region to pull minority carriers from surface
`
`
`
`Psubstrate |
`
`CMOSSubstrate for a DRAM or image sensor, with one embodiment of the invention
`
`ONSEMI EXHIBIT 1001, Page 1
`
`ONSEMI EXHIBIT 1001, Page 1
`
`

`

`U.S. Patent
`
`Nov. 17, 2015
`
`Sheet 1 of 10
`
`US 9,190,502 B2
`
`(WD 10d) uorenusou0| juedoq
`
`Distance
`
`419 sod) uoneuasuo, juedog
`
`Fioure1PriorArt
`
`ONSEMI EXHIBIT 1001, Page 2
`
`ONSEMI EXHIBIT 1001, Page 2
`
`

`

`U.S. Patent
`
`Nov. 17, 2015
`
`Sheet 2 of 10
`
`US 9,190,502 B2
`
`Slomoter
`
`SIUOWeYUSDUODJuedop-u)
`uOIseI1YupTerxeyidsu
`MeAON¢HHO
`
`IsARIJOyJNG+N
`
`tereenincenawe-ananraeTantehesreee:eerieTalentedjpeeeeeea+)
`
`
`
`
`“Caojran
`
`oyeysqns+g
`
`IOPITIOD
`
`ONSEMI EXHIBIT 1001, Page 3
`
`ONSEMI EXHIBIT 1001, Page 3
`
`
`
`
`
`

`

`U.S. Patent
`
`Nov. 17, 2015
`
`Sheet 3 of 10
`
`US 9,190,502 B2
`
`
`
`ameneeeeeeeemeemeareaeeee
`
`
`
`SOOLAOPSATIOV
`
`FT
`
`oyeysqnsd
`
`
`
`ONSEMI EXHIBIT 1001, Page 4
`
`
`
`ONSEMI EXHIBIT 1001, Page 4
`
`

`

`U.S. Patent
`
`Nov. 17, 2015
`
`Sheet 4 of 10
`
`US 9,190,502 B2
`
`jeuany
`
`10je[NsUy
`
`“okey
`
`
`
`ajeysqnsg
`
`©s0;stsuezy,
`
`SSO090Y
`
`fiesATOuIstPOUdTaSdsap-OM)&A0jjiJONG(Gegala
`
`ONSEMI EXHIBIT 1001, Page 5
`
`ONSEMI EXHIBIT 1001, Page 5
`
`
`

`

`U.S. Patent
`
`Nov. 17, 2015
`
`Sheet 5 of 10
`
`US 9,190,502 B2
`
`
`
`dojioedesaBv101sO
`
`©IO}sisuely,
`
`ssas0y
`
`ojensqnsJ
`
`
`
`ONSEMI EXHIBIT 1001, Page 6
`
`ONSEMI EXHIBIT 1001, Page 6
`
`
`

`

`U.S. Patent
`
`Nov. 17, 2015
`
`Sheet 6 of 10
`
`US 9,190,502 B2
`
`eselo1s IOJSISUBI],
`
`IO}SISUBI],
`
`js[9S/joHUCD
`
`pepes/jonu0D
`
`
`
`aSe10ISOBRIOIS
`
`
`
`jaetong(PeANNO
`[jooAiouIwYSeyGNWN&40;
`
`
`oyensqnsg
`
`
`
`
`
`[BUOTIPeH-Loye[NSUISISUISBBABYSIOJSISUBI]39S/[OQUOD:3}0N
`
`
`
`
`
`
`
`
`
`*I0]SISUR]?SOW
`
`
`
`yinATpeord.s43‘oinjonyjsoyeSpoyorjsBOARYSopouadeIOIS
`
`
`
`
`
`
`
`
`
`‘youysoy]Suisudurooayes[OQUOSpueoesSuNvoTe
`
`
`
`
`
`
`
`ONSEMI EXHIBIT 1001, Page 7
`
`ONSEMI EXHIBIT 1001, Page 7
`
`

`

`U.S. Patent
`
`Nov. 17, 2015
`
`Sheet 7 of 10
`
`US 9,190,502 B2
`
`
`
`UOIselUpjerxeydsu
`
`
`
`StUonRyUsoUOSjuedop-u)
`
`‘(papers
`
`
`
`IdAB]IOJING+N
`
`10192][0Dt
`
`
`
`
`
`
`jienaeieeeeer
`
`ONSEMI EXHIBIT 1001, Page 8
`
`ONSEMI EXHIBIT 1001, Page 8
`
`
`
`
`

`

`U.S. Patent
`
`Nov. 17, 2015
`
`Sheet 8 of 10
`
`US 9,190,502 B2
`
`
`
`SATW
`
`SOOLADP
`
`
`
`JoXey_uyuedoppoprin
`
`oyeysqnsg
`
`
`
` SOISiOWSSpus
`
`
`
`[EUDISPoxlM[E}isIp10joje1}sqngSOWV)sAMOI
`
`ONSEMI EXHIBIT 1001, Page 9
`
`ONSEMI EXHIBIT 1001, Page 9
`
`

`

`U.S. Patent
`
`
`
`JUsUIB]eIOSUASy
`
`
`
`
`
`410iopoedes9881015CT)
`
`IOJSISUBLLSSSODY
`
`Nov. 17, 2015
`
`Sheet 9 of 10
`
` TOUSAUIOW}JOJUSUMIPOquls
`
`
`
`9U0WIM“IOSHOSoseUT10JAIVug&10jeysqnsSOW()sMNO
`
`
`
`
`
`
`
`
`
`ooRpMsWoysietiesAyourw[Ind0}uorgerjuedoppaprin
`
`oyensqnsdg
`
`US 9,190,502 B2
`
`ONSEMI EXHIBIT 1001, Page 10
`
`ONSEMI EXHIBIT 1001, Page 10
`
`

`

`Nov. 17, 2015
`
`Sheet 10 of 10
`
`US 9,190,502 B2
`
`U.S. Patent
`
`IO}SISUBI
`
`pojes/fommog
`
`yoas/foyuog
`
`
`
`wooljuedop
`
`
`
`
`
`
`
`SUlAUIEAZOIdSULINPSOBLMSSPIEMO}SIOLLILDsayeIsjOD0V
`
`popein IO|stsueiy,
`
`
`
`
`
`ajensqnsg
`
`
`
`SoMSUMIMIEIS0IdJAOIGUMI0}ODiAapYStyGNWN&10joJe.1psqnsSOILD
`
`
`
`
`
`
`
`ONSEMI EXHIBIT 1001, Page 11
`
`ONSEMI EXHIBIT 1001, Page 11
`
`
`

`

`US 9,190,502 B2
`
`1
`SEMICONDUCTORDEVICES WITH
`GRADED DOPANT REGIONS
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`
`This continuation application claims priority to and the
`benefit of U.S. application Ser. No. 13/854,319, filed on Apr.
`1, 2013, which is a continuation of U.S. application Ser. No.
`11/622,496, filed Jan. 12, 2007, now U.S. Pat. No. 8,421,195,
`whichis a divisional ofU.S. application Ser. No. 10/934,915,
`filed on Sep. 3, 2004, now abandoned,all of which are incor-
`porated by reference.
`
`FIELD OF INVENTION
`
`This present invention relates to all semiconductor devices
`and systems. Particularly it applies to diffused diodes, ava-
`lanche diodes, Schottky devices, power MOStransistors,
`JFET’s, RF bipolartransistors, IGBTs (Insulated Gate Bipo-
`lar Transistors), varactors, digital VLSI, mixed signal circuits
`and sensor devices including camera ICs employing CCD
`(Charge Coupled Device) as well as CMOStechnologies.
`
`BACKGROUND OF INVENTION
`
`Bipolar Junction transistors (BJT) are minority carrier
`devices asthe principle device conduction mechanism. How-
`ever, majority carriers also a small yet finite role in modulat-
`ing the conductivity in BJTs. Consequently, both carriers
`(electrons and holes)play a role in the switching performance
`of BJTs. The maximum frequency of operation in BJTs is
`limited by the base transit time as well as the quick recombi-
`nation ofthe majority carriers when the device is switched off
`(prior to beginning the next cycle). The dominant carrier
`mechanism in BJTsis carrier diffusion. Carrier drift current
`
`componentis fairly small, especially in uniformly doped base
`BJTs. Efforts have been made in graded basetransistors to
`create an ‘aiding drift field’, to enhance the diffusing minority
`carrier’s speed from emitter to collector. However, most
`semiconductor devices, including various power MOSFETs
`(traditional, DMOS, lateral, vertical and a host of other con-
`figurations), IGBT’s (Insulated Gated Base Transistors), still
`use a uniformly dopeddrift epitaxial region in the base. FIG.
`1 showstherelative doping concentration versus distance in a
`BJT. FIG. 2 shows the ‘uniformly doped epi region’ in a
`IGBT.In contrast to BJTs, MOSdevices are majority carrier
`devices for conduction. The conduction is channel domi-
`nated. The channel can be a surface in one plane in planar
`devices. The surface can also be on the sidewalls in a vertical
`
`device. Other device architectures to combine planar and
`vertical conductions are also possible. The maximum fre-
`quency of operation is dictated primarily by source-drain
`separation distance. Most MOS devices use a uniformly
`doped substrate (or a well region). When a MOSFETis opti-
`mally integrated with a BJT ina monolithic fashion, an IGBT
`results. The IGBTinherits the advantages of both MOSFET
`and BJT. It also brings new challenges because the required
`characteristics (electron transit and hole recombination as
`fast as possible in the case of an n-channel IGBT) require
`different dopant gradients either in the samelayer atdifferent
`positions, orat the interfaces of similar or dissimilarlayers.
`‘Retrograde’ wells have been attempted, with little success,
`to help improve soft error immunity in SRAM’s andvisual
`quality in imaging circuits. FIG. 3(@) showsa typical CMOS
`VLSI device employing atwin well substrate, on which active
`devices are subsequently fabricated. FIGS. 3(5), 3(c), and
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`2
`3(d) illustrate device cross sections, as practiced today. ‘Ret-
`rograde’and‘halo’ wells have also been attempted to improve
`refresh time in DRAM’s (dynamic random access memo-
`ries), as well as, reducing dark current (background noise)
`and enhance RGB (Red, Green, Blue) color resolution in
`digital camera Ics. Most of these techniques either divert the
`minority carriers away form the active regions ofcritical
`charge storage nodes at the surface, or, increase minority
`carrier density locally as the particular application requires.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`For a more complete understanding of the present inven-
`tion, and the advantages thereof, reference is now madeto the
`following descriptions taken in conjunction with the accom-
`panying drawings, in which:
`FIG.1 illustrates the relative doping profiles of emitter,
`base, and collector, for the two most popular bipolar junction
`transistors: namely, A—uniform base, and B—gradedbase;
`FIG. 2 illustrates the cross section of a commercial IGBT
`with a uniform epitaxial drift region (base);
`FIGS. 3(a), 3(6), 3(c), 3(d) illustrate cross sections com-
`monly used CMOSsilicon substrate with two wells (one
`n-well in which p-channeltransistors are subsequently fabri-
`cated, and, one p-well in which n-channel transistors are
`subsequently fabricated)—typical IC, EEPROMusing tunnel
`insulator, DRAM and NANDflash;
`FIG.4 illustrates the cross section of a IGBT, using one
`embodiment of the invention described here, where the
`dopant is optimally graded in the eptaxial drift region; and
`FIGS. 5(a), 5(), 5(c) illustrate the cross sections of aMOS
`silicon substrate with two wells, and, an underlying layer
`using embodiments of the invention to improve performance
`in each application—VLS] logic, DRAM/imageIC, nonvola-
`tile memory IC.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`Therelative doping concentrations of emitter and collector
`regions varies from 10'* to 10?°/cm?, where as the base region
`is 10'*to 10'°/cm? dependingon the desired characteristics of
`the BJT. In graded base p-n-p transistors, the donor dopant
`concentration may be 10 to 100x at the emitter-base junction,
`relative to the base-collector junction (1x). The gradient can
`be linear, quasi linear, exponential or complimentary error
`function. The relative slope of the donor concentration
`throughout the base, creates a suitable aiding drift electric
`field, to help the holes (p-n-p transistor) transverse from emit-
`ter to collector. Since the aiding drift field helps hole conduc-
`tion, the current gain at a given frequency is enhanced,rela-
`tive to a uniformly-doped-(base) BJT. The improvement in
`cut-off frequency (or, frequency at unity gain, f,) can be as
`large as 2x-5x. Similar performance improvements are also
`applicable to n-p-ntransistors.
`Asillustrated in FIG. 4, in one embodiment according to
`the invention, a donor gradient is established from the emit-
`ter-drift epitaxial base region junction of the punch-through
`IGBT,
`to the drift epitaxial base region—n’ buffer layer
`boundary (electronsin this case are accelerated in their transit
`from emitter to collector). The ‘average’ base resistance is
`optimized, so that conductivity modulation andlifetime (for
`minority carriers) in base region are not compromised. By
`sweepingthe carriers towardsthe n' buffer region two advan-
`tages are obtained—the frequency of operation (combination
`oft,,, and t,-as is known in the IGBT commercial nomencla-
`ture) can be enhanced. More importantly, during t,», holes can
`be recombined much quicker at the n’ buffer layer, compared
`
`ONSEMI EXHIBIT 1001, Page 12
`
`ONSEMI EXHIBIT 1001, Page 12
`
`

`

`US 9,190,502 B2
`
`3
`toa uniformly doped n” epitaxial drift region by establishing
`a different dopant gradient near the n+ buffer layer. It should
`be noted that the drift region can also be a non-epitaxial
`silicon substrate. Epitaxy enhanceslifetime, but, epitaxy is
`not mandatory. Different layers ofdopan regions can be trans-
`ferred through wafer to wafer bonding(orother similar trans-
`fer mechanisms)for eventual device fabrication. The “reverse
`recovery time” for an IGBTis significantly improved due to
`the optimized graded dopantin the so called “drift region” as
`well as at the interfaces of the drift region. Graded dopants
`can also be implemented in the n+ bufferlayer as well as other
`regions adjacentto the respective layers. Two importantper-
`formance enhancements are the result of dopant gradients.
`For example, in an n-channel IGBT,electrons can be swept
`from source to drain rapidly, while at the same time holes can
`be recombinedcloserto the n+ buffer layer. This can improve
`t(on) and t(off) in the same device.
`The following paragraph, beginning on page5, line 6, and
`ending on page 11, line 28, is amendedas indicated in the
`marked up version below:
`Asillustrated in FIGS. 5(a), 5(5), 5(c), donor gradientis
`also ofbenefit to very large scale integrated circuits (WLSI)—
`VLSI logic, DRAM,nonvolatile memory like NAND flash.
`Spurious minority carriers can be generated by clock switch-
`ing in digital VLSI logic and memory IC’S. These unwanted
`carriers can discharge dynamically-held ‘actively held high’
`nodes. Statically held nodes (with V,.) can notbe affected, in
`most cases. Degradation of refresh time in DRAM’s is one of
`the results, because the capacitor holds charge dynamically.
`Similarly, degradation of CMOS digital images, in digital
`imaging IC’s is anotherresult ofthe havoc caused by minority
`carriers. Pixel and color resolution can be significantly
`enhanced in imaging IC’s with the embodiments described
`here. Creating ‘Sub Terrain’ recombination centers under-
`neath the wells (gold doping, platinum doping)as is done in
`some high-voltage diodes is not practical for VLSIcircuits.
`Hence, a novel technique has been described here by creating
`a drift field to sweep these unwanted minority carriers into the
`substrate as quickly as possible, from the active circuitry at
`the surface. In a preferred embodiment, the subterrain n-layer
`has a graded donor concentration to sweep the minority car-
`riers deep into the substrate. One or more of such layers can
`also be implemented through wafer to wafer bondingor simi-
`lar “transfer” mechanisms. This n-layer can be a deeply-
`implanted layer. It can also be an epitaxial layer. The n-well
`and p-well also can be graded or retrograded in dopants, as
`desired, to sweep those carriers away from the surface as well.
`The graded dopantcan also be implemented in surface chan-
`nel MOSdevices to accelerate majority carriers towards the
`drain. In nonvolatile memory devices, to decrease program-
`mingtime, carriers should be accelerated towards the surface
`when programming of memory cells is executed. The graded
`dopant can also be used to fabricate superior Junction field-
`effect transistors where the “channel pinchoff”is controlled
`by a graded channelinstead of a uniformly doped channel (as
`practicedin priorart).
`Oneof ordinary skill and familiarity in the art will recog-
`nize that the concepts taught herein can be customized and
`tailored to a particular application in many advantageous
`ways. For instance, minority carriers can be channeled to the
`surface, to aid programming in nonvolatile memory devices
`(NOR, NAND, multivalued-cell). Moreover, single well, as
`well triple-well CMOS fabrication techniques can also be
`optimized to incorporate these embodiments, individually
`and collectively. Any modifications of such embodiments
`
`4
`(described here) fall within the spirit and scope of the inven-
`tion. Hence,they fall within the scope ofthe claims described
`below
`
`Although the invention has been described with reference
`to specific embodiments, these descriptions are not meant to
`be construed in a limiting sense. Various modifications of the
`disclosed embodiments, as well as alternative embodiments
`ofthe invention will become apparentto personsskilled in the
`art upon reference to the description of the invention. It
`should be appreciated by those skilled in the art that the
`conception and the specific embodiment disclosed may be
`readily utilized as a basis for modifying or designing other
`structures for carrying out the same purposesofthe present
`invention.It should also be realized by those skilled in the art
`that such equivalent constructions do not depart from the
`spirit and scope of the invention as set forth in the appended
`claims.
`
`It is therefore, contemplated that the claims will cover any
`such modifications or embodiments that fall within the true
`
`20
`
`scope ofthe invention.
`
`Whatis claimedis:
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`1. A semiconductor device comprising:
`a surface layer;
`a substrate;
`an active region including a source anda drain, disposed on
`one surface of said surface layer;
`a single drift layer disposed between the other surface of
`said surface layer and said substrate, said drift layer
`having a graded concentration of dopants generating a
`first static unidirectional electric drift field to aid the
`movement of minority carriers from said substrate to
`said surface layer; and
`at least one well region disposed in said single drift layer,
`said well region having a graded concentration of
`dopants generating a second static unidirectional elec-
`tric drift field to aid the movementof minority carriers
`from said substrate to said surface layer.
`2. The semiconductor device of claim 1 wherein saidfirst
`
`and secondstatic unidirectionalelectric fields are adapted to
`respective grading of dopants to aid movementsof carriers in
`respective active regions.
`3. The semiconductor device of claim 1 wherein the semi-
`conductor device is a central processing unit (CPU).
`4. The semiconductor device of claim 1 wherein the semi-
`conductor device is a DRAM device.
`5. The semiconductor device of claim 1 wherein the semi-
`conductor device is a flash memory device.
`6. The semiconductor device of claim 1 wherein the semi-
`
`conductor device is an image sensor device.
`7. A semiconductor device comprising:
`a surface layer;
`a substrate;
`an active region including a source anda drain, disposed on
`one surface of said surface layer;
`a single drift layer disposed between the other surface of
`said surface layer and said substrate, said drift layer
`having a graded concentration of dopants generating a
`first static unidirectional electric drift field to aid the
`movement ofminority carriers from said surface layer to
`said substrate; and
`at least one well region disposed in said single drift layer,
`said well region having a graded concentration of
`dopants generating a second static unidirectional elec-
`tric drift field to aid the movementof minority carriers
`from said surface layer to said substrate.
`
`ONSEMI EXHIBIT 1001, Page 13
`
`ONSEMI EXHIBIT 1001, Page 13
`
`

`

`US 9,190,502 B2
`
`5
`8. The semiconductor device of claim 7 wherein saidfirst
`and secondstatic unidirectional electric fields are adapted to
`respective grading of dopants to aid movementsof carriers in
`respective active regions.
`9. The semiconductor device of claim 7 wherein the semi-
`
`conductor device is a central processing unit (CPU).
`10. The semiconductor device of claim 7 wherein the semi-
`conductor device is a DRAM device.
`11. The semiconductor device of claim 7 wherein the semi-
`
`conductor device is a flash memory device.
`12. The semiconductor device of claim 7 wherein the semi-
`conductor device is an image sensor device.
`*
`*
`*
`*
`*
`
`5
`
`10
`
`ONSEMI EXHIBIT 1001, Page 14
`
`ONSEMI EXHIBIT 1001, Page 14
`
`