United States Patent (19)
`Schiltz et al.
`
`(54) HIGHSPEEDSAMPLE AND HOLD CIRCUIT
`AND RADIO CONSTRUCTED THEREWITH
`(75) Inventors: Thomas E. Schiltz, Chandler; Carl R.
`Nuckolls, Fountain Hills, both of
`Ariz.
`73) Assignee: Motorola, Inc., Schaumburg, Ill.
`(21) Appl. No.: 985,477
`22 Filed:
`Dec. 3, 1992
`51) Int. Cl......................... H04B 1/28; H03K 5/159
`152 U.S. Cl. .................................... 455/333; 455/313;
`455/318; 307/353
`58 Field of Search ............... 455/313, 318, 323, 319,
`455/343,333,334, 316; 307/352, 353; 328/151
`References Cited
`U.S. PATENT DOCUMENTS
`Re. 32,314 12/1986 Gittins et al. ....................... 455/263
`
`(56)
`
`3,602,825 8/1971. Senior ..............
`
`-
`
`-
`
`- - -
`
`- -
`
`-
`
`- - - - - - 307/352
`
`4,066,919 1/1978 Huntington ......................... 307/353
`4,370,572
`/1983 Cosand et al. .......
`... 307/353
`4.389,579 6/1983 Stein .....................
`... 307/353
`4,612,464 9/1986 Ishikawa et al. .
`... 307/352
`4,801,823 1/1989 Yokoyama ...........
`... 307/353
`4,806,790 2/1989 Sone .....................
`... 307/353
`4,910,752 3/1990 Yester, Jr. et al. .
`... 455/343
`4,922,452 5/1990 Larsen et al. ........
`... 367/138
`4,970,703 11/1990 Hariharan et al. ...
`5,017,924 5/1991 Guiberteau et al. ................ 342/195
`OTHER PUBLICATIONS
`An article entitled "Accurately Model Unbiased FETs
`for Monolithic Switches', by C. Kermarrec et al. of
`Tachonics Corp., from Microwaves & RF Jun. 1989.
`An article entitled “Waveform Sampling with Schottky
`Diodes' Hewlett Packard Components Application Bulle
`tin 16, 5952-9818 (Nov. 1976).
`An article entitled "A 1-GHz 6-bit ADC System” by
`Ken Poulton et al., IEEE Journal of Solid-State Circuits,
`vol. SC-22, No. 6, Dec. 1987, pp. 962-969.
`An article entitled "Characterization of Microwave
`Integrated Circuits. Using an Optical Phase-Locking
`and Sampling System', by H-L. A. Hung et al. of
`COMSAT Laboratories, Clarksburg, Md., IEEE
`MTT-S Digest, 1991, pp. 507–510.
`
`- - - - - 365/45
`
`
`
`US005339459A
`Patent Number:
`11
`45) Date of Patent:
`
`5,339,459
`Aug. 16, 1994
`
`An article entitled "Computer-Aided Noise analysis of
`MESFET and HEMT Mixers', by V. Rizzoli et al.,
`IEEE Transactions on Microwave Theory and Techniques,
`vol. 37, No. 9, Sep. 1989, pp. 1401-1410.
`An article entitled "Novel GaAs FET Phase Detector
`Operable to Ka Band'T. Takano et al. Fujitsu Labora
`tories Ltd., Kawasaki, Japan, IEEE MTTS Digest,
`1984, pp. 381-383.
`An article entitled "130 GHz GaAs Monolithic Inte
`grated Circuit Sampling Head', by R. A. Marsland et
`al. of Edward L. Ginzton Laboratory, Stanford Univer
`sity, Stanford, Calif., 1989 American Institute of Physics,
`Appl. Phy. Lett. 55(6), 7 Aug. 1989, pp. 592–594.
`An article entitled "RF Sampling Gates: a brief re
`view', by N. P. Akers et al., IEEProceedings, vol. 133,
`Pt. A. No. 1, Jan. 1986, pp. 45-49.
`(List continued on next page.)
`Primary Examiner-Reinhard J. Eisenzopf
`Assistant Examiner-Nguyen Vo
`Attorney, Agent, or Firm-Frederick M. Fliegel; Robert
`M. Handy
`ABSTRACT
`57)
`A sample and hold circuit is formed within an inte
`grated circuit and has a small, substantially linear hold
`capacitance. The circuit includes a sampling switch, a
`hold capacitor, and a buffer amplifier. The buffer ampli
`fier includes a common drain FET and a constant cur
`rent source FET. The common drain FET provides an
`input which couples to the hold capacitor. The constant
`current FET isolates the source of the common drain
`FET from ground. The sample and hold circuit may be
`used as a wide bandwidth mixer. In a radio application,
`a pulse generator provides a stream of pulses in which
`the sampling rate times an integer number equals the RF
`frequency minus the IF frequency. The width of the
`sampling pulse is less than the period of an RF signal. In
`an oscillator application, the sample and hold circuit
`operates as a mixer in a frequency multiplying phase
`locked loop.
`
`17 Claims, 3 Drawing Sheets
`
`MEDIATEK EX. 1005
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`

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`5,339,459
`Page 2
`
`OTHER PUBLICATIONS
`An article entitled "Sampling for Oscilloscopes and
`Other RF Systems: Dc through X-Band”, by W. M.
`Grove, IEEE Transactions on Microwave Theory and
`Techniques, vol. MTT-14, No. 12, Dec. 1966, pp.
`629–635.
`An article entitled "Sampling Loops Lock Sources to
`23 GHz", Microwaves & RF, Sep.1990.
`An article entitled "Subharmonic Sampling for the
`Measurement of Short-Term Stability of Microwave
`
`Oscillators' by N. D. Faulkner et al., IEEE Transac
`tions on Instrumentation and Measurement, vol. IM-32,
`No. 1, Mar. 1983, pp. 208-213.
`An article entitled "Sub-Nanosecond Single-Shot Dig
`itizing Using the HP 54111D', Hewlett Packard Product
`Note HP54111D-1, Mar. 1988.
`An article entitled “2.4 GHz MESFET Sampler', by H.
`Hafdallah et al., Institut d'Electronique Fondamentale,
`Universite Paris, France, 10th Dec. 1987.
`An article entitled "Readout', Electronic Engineering,
`Mar. 1987, pp. 77-79.
`
`MEDIATEK EX. 1005
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`

`

`U.S. Patent
`
`Aug. 16, 1994
`
`Sheet 1 of 3
`
`5,339,459
`
`
`
`
`
`
`
`
`
`
`
`38
`
`
`
`
`
`
`
`HIGH SPEED
`SAMPLE AND
`HOLD CIRCUIT
`
`
`
`28
`
`30
`
`32
`
`Gefior
`
`Af7G 7
`
`Af7G 2
`
`40
`
`44
`HIGH SPEED
`SAMPLE AND
`HOLD CIRCUIT
`
`LOOP
`FILTER
`
`
`
`
`
`50 DIELECTRIC
`RESONATOR
`OSCILLATOR
`
`f
`36
`
`
`
`RE
`
`
`
`52
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`MEDIATEK EX. 1005
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`

`

`U.S. Patent
`
`Aug. 16, 1994
`
`Sheet 2 of 3
`
`5,339,459
`
`777G 4
`
`
`
`DC
`
`64 62 62
`
`MEDIATEK EX. 1005
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`

`

`U.S. Patent
`
`Aug. 16, 1994
`
`Sheet 3 of 3
`
`5,339,459
`
`
`
`# II
`
`NOISSIWSNW8||
`
`ENIT
`
`ff/
`
`Gº ~ º) Z, AZ
`
`MEDIATEK EX. 1005
`Page 5 of 12
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`

`

`1
`
`5,339,459
`
`HIGH SPEED SAMPLE AND HOLD CIRCUIT AND
`RADIO CONSTRUCTED THEREWITH
`
`s
`
`TECHNICAL FIELD OF THE INVENTION
`The present invention relates generally to high speed
`electronic circuits. More specifically, the present inven
`tion relates to a high speed sample and hold circuit and
`to radios which use such a circuit as a mixer.
`BACKGROUND OF THE INVENTION
`Conventional radios which detect high frequency RF
`signals, above 300 MHz for example, or otherwise gen
`erate high frequency signals often consume great
`15
`amounts of power, require a large amount of space,
`require excessive amounts of individual alignment, are
`excessively expensive, and suffer from reduced reliabil
`ity. These problems result, at least in part, from the
`generation of local oscillator or other oscillation signals
`20
`at high frequencies.
`For example, frequencies of signals used in these
`applications must often be multiplied by factors in the
`range of 25-200. One conventional technique for ac
`complishing the multiplication is through the use of a
`25
`cascade of step recovery diode multipliers, each of
`which multiply by a factor of around 2-15. Such multi
`pliers can require up to 16 cubic inches in volume and
`consume an excess of 2 Watt of power. Another con
`ventional technique for accomplishing the multiplica
`30
`tion is through the use of a phase locked loop which
`requires less space but still requires high power, high
`speed frequency dividers.
`Both of these techniques produce narrow band out
`put signals. With a cascade of step recovery diodes,
`35
`each cascaded stage must be carefully aligned for opera
`tion at a single output frequency, and filters in each
`stage must be individually tuned to reject undesired
`harmonics. With a phase locked loop, the tuning range
`of a voltage controlled oscillator limits the frequency
`range producible, and this tuning range is typically
`minimized to reduce phase noise. The need for individ
`ual alignment in devices which operate at high frequen
`cies drives up costs by introducing costly manufactur
`45
`ing steps and by introducing opportunities for mistakes
`and errors in workmanship.
`As discussed below, sample and hold circuits may be
`used in solving at least some of the problems posed by
`radios which operate at high frequency. An extensive
`50
`body of technology has developed around utilizing
`sample and hold circuits in the digital reconstruction of
`analog signals. Since the majority of this technology
`requires sampling to occur at a rate which is typically
`greater than twice the frequency of the signal being
`sampled, a need has always existed for higher speed
`sample and hold circuits.
`Nevertheless, the performance of conventional sam
`ple and hold circuits operating at high frequency micro
`wave RF rates has remained poor. For example, acqui
`sition time and acquisition accuracy have often been too
`poor to permit the use of sample and hold circuits at
`higher RF frequencies in any application other than
`those requiring only very narrow output bandwidths,
`such as phase detector applications. Moreover, non
`65
`linearities in critical parameters, such as hold capaci
`tance, become severe handicaps at higher RF frequen
`cies.
`
`2
`SUMMARY OF THE INVENTION
`Accordingly, it is an advantage of the present inven
`tion that an improved radio is provided.
`Another advantage is that the present invention pro
`vides a radio which uses a sample and hold circuit as a
`mixer, which does not require the generation of a LO
`signal near an RF frequency, and which uses only a few
`low-power components.
`Another advantage is that the present invention pro
`vides an oscillating signal generation circuit which pro
`duces a relatively high frequency output signal locked
`to a relatively low frequency reference signal using only
`a few low-power components.
`Another advantage of the present invention is that an
`improved sample and hold circuit is provided.
`Another advantage is that the present invention pro
`vides a sample and hold circuit which exhibits a rela
`tively linear hold capacitance when operated at high
`RF frequencies.
`Another advantage is that the present invention pro
`vides a single sample and hold circuit which may be
`used as either a phase detector or a mixer.
`The above and other advantages of the present inven
`tion are carried out in one form by an improved radio
`having a receiver capable of receiving a wideband RF
`signal. The radio includes an antenna that supplies an
`RF signal exhibiting an RF frequency. A sample and
`hold circuit has a sample input that couples to the an
`tenna. A hold output of the sample and hold circuit
`supplies an IF signal. A pulse generator has an output
`which couples to a control input of the sample and hold
`circuit. The pulse generator is configured to produce a
`stream of pulses at a sampling rate less than the RF
`frequency. Moreover, the pulse generator is configured
`so that each of the pulses has a pulse width substantially
`less than a period for the RF signal.
`The above and other advantages of the present inven
`tion are carried out in another form by an improved
`high speed sample and hold circuit. The sample and
`hold circuit includes a sampling switch that has an input
`for receiving a signal to be sampled. A hold capacitor
`couples to an output of the sampling switch. A first
`transistor is configured in a common drain circuit ar
`rangement and has a gate that couples to the sampling
`switch output. A second transistor is configured as a
`substantially constant current source. The second tran
`sistor couples to a source of the first transistor.
`BRIEF DESCRIPTION OF THE DRAWINGS
`A more complete understanding of the present inven
`tion may be derived by referring to the detailed descrip
`tion and claims when considered in connection with the
`Figures, wherein like reference numbers refer to similar
`items throughout the Figures, and:
`FIG. 1 shows a block diagram of a radio constructed
`in accordance with the teaching of the present inven
`tion;
`FIG. 2 shows a block diagram of an oscillating signal
`generation circuit constructed in accordance with the
`teaching of the present invention;
`FIG. 3 shows an exemplary spectral diagram depict
`ing a sample pulse spectrum and an RF spectrum;
`FIG. 4 shows an exemplary spectral diagram depict
`ing the convolution of the sample pulse and RF spectra
`of FIG. 3; and
`FIG. 5 shows a schematic diagram of a sample and
`hold circuit.
`
`MEDIATEK EX. 1005
`Page 6 of 12
`
`

`

`10
`
`15
`
`3
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`FIG. 1 shows a block diagram of a radio 10 which
`converts one or more RF signals into an IF signal and
`then into a baseband signal. Radio 10 includes an an
`tenna 12, which provides a first RF signal and an op
`tional antenna 14 which provides a second RF signal. In
`the preferred embodiment, these RF signals exhibit
`frequencies in excess of 300 MHz, and quite possibly in
`excess of 1-7 GHz. The present invention may be
`adapted to operate at lower frequencies, but the numer
`ous advantages of the present invention are pronounced
`at higher RF frequencies.
`An example embodiment is described herein in which
`the first RF signal exhibits a frequency around 7.49
`GHz and the second RF signal exhibits a frequency
`around 2.21 GHz. Radio 10 downconverts both of these
`RF signals to an IF signal that exhibits a frequency
`around 50 MHz. However, those skilled in the art will
`20
`appreciate that this example embodiment is presented to
`illustrate and clarify the concepts embodied by the pres
`ent invention and that the present invention is in no way
`limited to this example embodiment.
`Antenna 12 couples to an input of a low noise ampli
`25
`fier 16, and an output of amplifier 16 couples to an input
`of an image filter 18. Antenna 14 couples to an input of
`a low noise amplifier 20, and an output of amplifier 20
`couples to an input of an image filter 22. Of course,
`those skilled in the art will appreciate that an alternate
`30
`embodiment may be constructed in which a single an
`tenna and RF amplifier drive separate image filters (not
`shown). As is conventional, image filters 18 and 22 are
`preferably configured as bandpass filters having center
`frequencies near the their respective RF frequencies
`35
`and a bandwidths approximately twice the IF fre
`quency. For the example embodiment, filter 18 has a
`center frequency at around 7.49 GHz and a bandwidth
`of around 100 MHz, and filter 22 has a center frequency
`at around 2.21 GHz and a bandwidth of around 100
`MHz. Such filters may be constructed using microwave
`comb filtering techniques or high dielectric-constant
`ceramic materials, depending upon the frequencies in
`volved.
`The outputs of image filters 18 and 22 couple to a
`45
`combiner 24, where they are added together. An output
`from combiner 24 couples to a sample input of a high
`speed sample and hold circuit 26. Details related to
`sample and hold circuit 26 are discussed below in con
`nection with FIG. 5. Sample and hold circuit 26 succes
`50
`sively samples the filtered RF signals supplied through
`amplifier 16 and filter 18 and through amplifier 20 and
`filter 22 to determine an amplitude of the resulting RF
`signal during the samples. In addition, sample and hold
`circuit 26 holds sampled amplitudes between successive
`55
`samples. Sample and hold circuit 26 provides the IF
`signal at a hold output. In other words, held samples of
`the RF signal represent the IF signal. The hold output
`of sample and hold circuit 26 couples to an input of a
`detector 28. Detector 28 decodes a baseband signal
`from the IF signal in a manner consistent with an appli
`cation in which radio 10 is being used. Detector 28 may,
`for example, decode digital data from the IF signal
`supplied by the hold output of sample and hold circuit
`26.
`65
`The IF frequency is determined by characteristics of
`a pulse stream supplied by a pulse generator 30 to a
`control input of sample and hold circuit 26. Pulse gener
`
`5,339,459
`4
`ator 30 includes an oscillation signal source, such as a
`voltage controlled crystal oscillator (VCXO) 32. The
`frequency of oscillator 32 (f) may be controlled exter
`nally (not shown) within a frequency range that is eas
`ily, reliably, and inexpensively achievable. In the exam
`ple embodiment of the present invention, oscillator 32
`generates an oscillation signal exhibiting frequencies
`around 240 MHz. Oscillator 32 couples to an input of an
`impulse generator 34. Impulse generator 34 generates a
`pulse having a width (t) that is less than the period (Tf)
`of the highest RF signal presented to the sample input of
`sample and hold circuit 26. A stream of sampling pulses
`at a pulse rate off results. Those skilled in the art will
`appreciate that impulse generator 34 may be imple
`mented using many different techniques. For example,
`step recovery diodes and inductor-capacitor (LC) tank
`circuits may be used, or digital flip-flop circuits with
`feedback may be used (not shown).
`The duration between successive sampling pulses is
`Ts, which equals 1/f, and is approximately 4.167 nano
`seconds seconds (ns) in the example embodiment. The
`duration T of the sampling pulse is not a critical parame
`ter in the present invention so long as it remains signifi
`cantly less than the period of the RF signals being sam
`pled, but is preferably as brief as is reasonably practical.
`Moreover, the rise and fall times of the sampling pulse
`are not critical parameters, but are preferably as brief as
`is reasonably practical.
`Sample and hold circuit 26 operates as a downcon
`verter in radio 10. Sample and hold circuit 26 converts
`a high frequency RF signal into an IF signal in a single
`operation. Moreover, no local oscillator signal at a fre
`quency near the RF is generated. Rather, local oscilla
`tor signals may remain at frequencies less than 3, and
`preferably significantly less than , of the RF. By re
`fraining from generating local oscillator signals at fre
`quencies near the RF signal, power consumption and
`circuit volume requirements are reduced, and compo
`nents which otherwise require individual alignment are
`not needed.
`The inclusion of two RF input sources in radio 10
`illustrates the wide RF bandwidth nature of radio 10
`and of the downconverter provided by sample and hold
`circuit 26. If radio 10 loses a signal source at one fre
`quency, the input circuitry may be switched so that an
`entirely different input frequency band is received. A
`single sample and hold circuit 26 may successfully
`downconvert from either frequency band.
`While FIG. 1 shows a radio 10 in which a local oscil
`lator signal need not operate at or near the RF fre
`quency, FIG. 2 shows an improved oscillation signal
`generation circuit 36 which generates a high frequency
`oscillation signal using only a few low power compo
`nents. Oscillation circuit 36 may, for example, provide a
`high frequency local oscillation signal which a radio
`may use in a conventional manner. The oscillation sig
`nal provided by the circuit shown in FIG. 2 is locked to
`an externally supplied relatively low frequency refer
`ence signal.
`With reference to FIG. 2, the low frequency refer
`ence signal is applied to a terminal 38. Terminal 38
`couples to an input of an impulse generator 40 and to an
`input of a frequency divider circuit 42. An output of
`impulse generator 40 couples to a control input of a
`high speed sample and hold circuit 44. A hold output of
`sample and hold circuit 44 couples to a first input of a
`phase comparator 46, and an output of frequency di
`vider 42 couples to a second input of phase comparator
`
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`5,339,459
`5
`6
`46. An output of phase comparator 46 couples to an
`adopt this teaching to the mixing application shown in
`input of a loop filter 48, and an output of loop filter 48
`FIG. 2 as well.
`couples to an input of an oscillator 50. An output of
`Sample and hold circuit 26 (see FIG. 1) samples the
`oscillator 50 couples to an input of a power divider 52.
`RF signal while the pulses supplied by pulse generator
`A first output of power divider 52 couples to a sample
`30 (see FIG. 1) are active and holds the samples while
`input of sample and hold circuit 44, and a second output
`the pulses are inactive. In other words, sample and hold
`of power divider 52 provides the oscillation signal gen
`circuit 26 successively samples the RF signal for a dura
`erated by oscillation circuit 36.
`tion of T (the pulse width) and holds the sample for the
`In general, circuit 36 represents a fractional-fre
`remainder of the duration TS (the sampling period).
`quency synthesizing phase locked loop. Frequency
`Ignoring the hold effect, in the time domain this sam
`pling process is equivalent to a multiplication of the
`divider 42 provides a fractional multiplication capabil
`ity which allows the output frequency to differ from an
`local oscillator pulse stream with the RF signal. In the
`integral multiple of the reference frequency. Impulse
`frequency domain, it is equivalent to the convolution of
`generator 40 and sample and hold circuit 44 represent
`the RF spectrum with the spectrum of the local oscilla
`tor pulse stream. FIGS. 3-4 graphically show this con
`substantially the same structures as are described above
`volution. The frequency content of the pulse stream
`in connection with FIG. 1 with reference to impulse
`consists of a series of impulses 54 at integral multiples of
`generator 34 and sample and hold circuit 26, respec
`the sampling frequency f. An amplitude envelope 56 of
`tively. Sample and hold circuit 44 also serves as a mixer.
`the pulse stream spectrum follows a sin(x)/x, or sinc(x),
`In circuit 36, sample and hold circuit 44 multiplies the
`shape, with nulls occurring at integral multiples of 1/t.
`20
`signal harmonics present in the pulse stream output by
`In general, the IF output frequency spectrum from
`impulse generator 40 with the output signal to generate
`sampling an RF signal is governed by the general equa
`a "product” signal. Oscillator 50 is tuned to oscillate at
`or near a desired output frequency.
`tion:
`As an example embodiment, oscillator 50 may repre
`25
`sent a dielectric resonator oscillator which is configured
`to resonate at around 8.86 GHz, a reference signal may
`oscillate at around 120 MHz, and frequency divider 42
`may be configured to divide frequency by a factor of 6.
`The harmonics of the reference signal, as presented in
`the pulse stream provided by impulse generator 40, are
`multiplied by the fed-back 8.86 GHz output signal in
`sample and hold circuit 44. The 74th harmonic of the
`120 MHz reference signal has a frequency of 8.88 GHz.
`Of course, numerous other harmonics are present in the
`35
`output from impulse generator 40 as well. The 74th
`harmonic causes sample and hold circuit 44 to produce
`a 20 MHz product signal. The other harmonics from the
`pulse stream cause the product signal to additionally
`include higher frequency components. With frequency
`divider 42 dividing frequency by a factor of six, a 20
`MHz signal is produced. Phase comparator 46 produces
`a DC output from the 20 MHz components of the sig
`nals produced by frequency divider 42 and sample and
`hold circuit 44. The higher frequency components are
`45
`filtered off by loop filter 48. A feedback loop forms
`wherein the output of phase comparator 46 operates
`around DC to keep the output signal oscillating at 8.86
`GHz, locked to the 120 MHz reference signal. Of
`course, those skilled in the art will appreciate that this
`50
`example is presented herein for the purposes of explana
`tion and that the present invention is in no way limited
`to the particular parameters presented in this example.
`As will be discussed below, sample and hold circuit
`44 has little conversion loss in multiplying the signals
`presented at its sample and control inputs. Accordingly,
`even the 74th harmonic of the reference signal causes
`the output to have significant power. Those skilled in
`the art will appreciate that filtering and amplification
`stages may be minimized and even omitted between
`sample and hold circuit 44 and phase comparator 46,
`and that only a few low power components are needed.
`FIGS. 3-4 graphically illustrate sampling effects in
`multiplying the signals presented at control and sample
`inputs of sample and hold circuits 26 (see FIG. 1) and 44
`65
`(see FIG. 2). FIGS. 3-4 are presented from the perspec
`tive of down converting an RF signal to an IF signal, as
`shown in FIG. 1. However, those skilled in the art can
`
`With a sample frequency f. of 240 MHz, the ninth
`harmonic (n=9) of the pulse stream spectrum occurs at
`2.16 GHz. This ninth harmonic is adjacent to the 2.21
`GHz. RF input signal discussed above in connection
`with FIG.1. Likewise, the thirty-first harmonic (n=31)
`of the pulse stream spectrum occurs at 7.44 GHz and is
`adjacent to the 7.49 GHz. RF input signal discussed
`above in connection with FIG. 1. FIG. 3 illustrates the
`2.21 GHz. RF spectrum at component 58 and the ninth
`harmonic at impulse 60. Those skilled in the art will
`understand that numerous harmonics 54 for this exam
`ple have been omitted from FIG.3 for clarity of illustra
`tion. As shown in FIG. 4, the convolution produces a
`series of spectral IF components 62, with one IF com
`ponent 64 occurring near DC and components 62 sepa
`rated from one another by fs. Those skilled in the art
`will appreciate that FIG. 4 applies to downconversion
`of the 7.49 GHz. RF signal as well.
`Conversion loss describes the signal loss which re
`sults from converting an RF signal into an IF signal. To
`minimize conversion loss of the lowest frequency IF,
`the Sinc function weighing factor in Eq. 1, presented
`above, must be as close to unity as possible. In order to
`keep fs at frequencies far less than frF, the n and fs
`parameters are set by other design considerations. Thus,
`
`fiF(j2af) = 1f. - 8 Fj2nfrf) -- Š (sincentrfs) }.
`
`Eq. 1
`
`where:
`f=sampling rate,
`frF=RF frequency,
`t=sampling pulse duration,
`n = an integer harmonic number, and
`F ()=Fourier transform.
`Thus, for an IF output near DC, which is usually de
`sired, the pulse stream frequency components that are
`adjacent to the input RF spectrum will convolve with
`the RF signal to produce an IF output (fiF) centered at:
`fiF= frFEnf
`Eq. 2
`
`5
`
`O
`
`15
`
`55
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`15
`
`5,339,459
`7
`8
`the sampling pulse width T is desirably as brief as possi
`tion of fifty ohm transmission lines, which are com
`ble.
`monly used to transmit high frequency RF signals.
`For the example embodiment, conversion loss is
`A gate of FET 76 couples through a DC blocking
`around -37.3 dB. However, the holding process per
`capacitor 82 to a contact 84 of IC 66. Contact 84 serves
`formed by sample and hold circuit 26 compensates for
`as the control input for sample and hold circuit 26. In
`this loss while simultaneously attenuating higher fre
`other words, the stream of sampling pulses is applied to
`quency components 54. Conversion loss is compensated
`sample and hold circuit 26 at contact 84. The gate of
`for because the information obtained during a brief
`FET 76 also couples to a first node of a matching resis
`sample is held without substantial attenuation for the
`tor 86, which preferably exhibits around fifty ohms for
`remainder of the sampling period Ts. Thus, the relative
`10
`termination of fifty ohm transmission lines. An AC
`proportion of this information is amplified, roughly by
`shorting capacitor 88 and a biasing resistor 90 each
`the factor TS/t, when compared to other information
`couple between a second node of matching resistor 86
`ignored during the hold period. Higher frequencies are
`and ground terminal 80. A biasing resistor 92 couples
`attenuated due to a zero-order hold created by a hold
`between the second node of matching resistor 86 and a
`capacitor (discussed below) within sample and hold
`contact 94 of IC 66. When a negative potential, around
`circuit 26.
`-4 Vdc for example, is applied at contact 94 biasing
`Thus, the spectral content of a stream of pulses in
`resistors 90 and 92, bias the gate of FET 76 through
`cludes a large number of harmonics. These harmonics
`matching resistor 86. Capacitor 88 provides an AC
`mix with the RF signal. Radio 10 (see FIG. 1) uses
`ground to the second node of matching resistor 86.
`20
`higher order harmonics from the stream of pulses in lieu
`A drain of FET 76 serves as the output of sample
`of a continuous wave local oscillator signal at or near
`switch 68. The schematic diagram of FIG. 5 shows a
`the RF frequency. One of the higher order harmonics
`transmission line 96, which couples sample switch 68 to
`convolves with the RF signal to produce a near DCIF
`a first node of hold capacitor 70. The schematic dia
`signal. Conversion loss at the desired low frequency IF
`gram of FIG. 5 also shows a transmission line 97, which
`25
`is compensated for by holding samples, and higher fre
`couples the first node of hold capacitor 70 and sample
`quency IF spectra produced by convolution with other
`switch 68 to an input of buffer amplifier 72. A second
`harmonics from the stream of pulses are attenuated by a
`node of hold capacitor 70 couples to ground terminal
`zero-order hold.
`80.
`Sample and hold circuits 26 (see FIG. 1) and 44 (see
`In the preferred embodiment, hold capacitor 70 ex
`30
`FIG. 2) have a bandwidth sufficiently wide to accom
`hibits a capacitance of around 1 picoFarad. In general,
`modate the required IF (see FIG. 1) or product signal
`this capacitance needs to be as small as possible so that
`(see FIG. 2), that they respectively generate. Unfortu
`acquisition time may be as fast as possible and band
`nately, conventional sample and hold circuits fail to
`width extended as far as possible. On the other hand,
`achieve the bandwidth needed for mixing when IF
`hold capacitance preferably exhibits a capacitance
`35
`signals output from sample and hold circuits 26 and 44
`which is significantly larger than the parasitic capaci
`occupy a frequency range of many MHz, as in the ex
`tances present at the output of FET 76 and the input of
`ample embodiments presented above in connection with
`buffer amplifier 72. Such parasitic capacitances associ
`FIGS. 1 and 2. FIG. 5 shows a schematic diagram of
`ated with active devices are nonlinear. In other words,
`one embodiment of sample and hold circuit 26 that
`the capacitance changes depending upon the instanta
`40
`neous voltages present. Such non-linear capacitances
`achieves a wide bandwidth and is suitable for use in
`radio 10. Although, the discussion of FIG. 5 is pres
`tend to harm the accuracy of samples and decrease the
`ented from a perspective of sample and hold circuit 26,
`dynamic range of RF signals receivable by radio 10 (see
`the same structure applies to sample and hold circuit 44
`FIG. 1). By forming hold capacitor 70, which exhibits a
`as well.
`substantially linear capacitance, to have a capacitance
`45
`significantly larger than the parasitic capacitances at
`In order to achieve a wide bandwidth, sample and
`hold circuit 26 is preferably implemented as an inte
`this node, acquisition accuracy is improved and dy
`grated circuit. In other words, substantially all compo
`namic range is extended.
`nents needed by sample and hold circuit 26 reside
`Those skilled in the art will appreciate that at the high
`within a single integrated circuit (IC) 66. In the pre
`RF frequencies at which sample and hold circuit 26
`50
`ferred embodiment, IC 66 is constructed from a gallium
`may operate, the transmission line characteristics of
`arsenide (GaAs) die within an area that is approximately
`every connection between components may be signifi
`70 mils by 70 mils, or an area less than 0.005 in 2. This
`cant. However, transmission lines 96 and 97 are shown
`small area causes transmission lines which carry signals
`because their characteristics particularly affect the per
`between components within sample and hold circuit 26
`formance factors controlled by hold capacitor 70. The
`55
`to be very short. Consequently, stray capacitances,
`resistive and inductive characteristics of transmission
`resistances, and inductances are reduced.
`lines 96 and 97 are reduced by forming sample switch
`IC 66 includes a sampling switch 68, a hold capacitor
`68, hold capacitor 70, and buffer amplifier 72 in a small
`70, and a buffer amplifier 72. Sampling switch 68 in
`area within a common integrated circuit.
`cludes a contact 74 of IC 66, which serves as the sam
`The time required for hold capacitor 70 to acquire a
`pling input. In other words, an RF signal is applied to
`sample is determined in large part by the R-C time
`sample and hold circuit 26 at contact 74. Contact 74
`constant formed by hold capacitor 70 and the "on'
`couples to a source of a field effect transistor (FET) 76.
`resistance of FET 76 in series with transmiss