I El El I I Burr-Brown Products
`• - - - - - • from Texas Instruments
`
`ADS7822
`
`SBAS062C - JANUARY 1996-REVISED AUGUST 2007
`
`12-Bit, 200kHz, microPower Sampling
`ANALOG-TO-DIGITAL CONVERTER
`
`FEATURES
`• 200kHz Sampling Rate
`• microPower:
`1.6mW at 200kHz
`0.54mW at 75kHz
`0.06mW at 7.SkHz
`• Power Down: 3µA max
`• Mini-DIP-8, S0-8, and MSOP-8 Packages
`• Pseudo-Differential Input
`• Serial Interface
`
`APPLICATIONS
`• Battery-Operated Systems
`• Remote Data Acquisition
`Isolated Data Acquisition
`•
`• Simultaneous Sampling, Multichannel Systems
`
`DESCRIPTION
`The ADS7822 is a 12-bit sampling analog-to-digital
`(AID) converter with ensured specifications over a
`2.7V to 5.25V supply range. It requires very little
`power even when operating at the full 200kHz rate. At
`lower conversion rates, the high speed of the device
`enables
`it
`to spend most of its
`time
`in
`the
`power-down mode-the power dissipation is less
`than 60µW at 7.SkHz.
`The ADS7822 also features operation from 2.0V to
`SV, a synchronous serial
`interface, and a
`pseudo-differential input. The reference voltage can
`be set to any level within the range of S0mV to Vee•
`Ultra low power and small size make the ADS7822
`ideal for battery-operated systems. It is also a perfect
`fit for remote data-acquisition modules, simultaneous
`multichannel systems, and isolated data acquisition.
`The ADS7822 is available in a plastic mini-DIP-8, an
`SO-8, or an MSOP-8 package.
`
`SAR
`
`Control
`
`CDAC
`
`Serial
`- - . ,, Interface
`
`Comparator
`
`Dour
`
`DCLOCK
`
`CS/SHON
`
`A
`Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
`~ Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
`All trademarks are the property of their respective owners.
`
`PRODUCTION DATA information is current as of publication date.
`Products conform to specifications per the terms of tile Texas
`Instruments standard warranty. Production processing does not
`necessarily include testing of all parameters.
`
`Copyright © 1996--2007, Texas Instruments Incorporated
`
`Petitioner Samsung Ex-1042, 0001
`
`

`

`ADS7822
`
`SBAS062C - JANUARY 1996-REVISED AUGUST 2007
`
`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
`appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
`
`ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
`suscept ble to damage because very small parametric changes could cause the device not to meet its published specifications.
`
`ORDERING INFORMATIONl11
`
`PRODUCT
`
`MAXIMUM
`INTEGRAL
`LINEARITY
`ERROR
`(LSB)
`
`MAXIMUM
`DIFFERENTIAL PACKAGE·
`LINEARITY
`LEAD
`ERROR
`(LSB)
`
`SPECIFIED
`PACKAGE
`PACKAGE
`DESIGNATOR TEMPERATURE MARKINGl2l
`RANGE
`
`ORDERING
`NUMBER
`
`ADS7822E
`
`±2
`
`±2
`
`MSOP-8
`
`DGK
`
`-4o•c to +85°C
`
`A22
`
`ADS7822EB
`
`±1
`
`±1
`
`MSOP-8
`
`DGK
`
`-4o•c to +85°C
`
`A22
`
`ADS7822EC
`
`±0.75
`
`±0.75
`
`MSOP-8
`
`DGK
`
`-4o•c to +85°C
`
`A22
`
`ADS7822E/250
`
`ADS7822E/2K5
`
`ADS7822EB/250
`
`ADS7822EB/2K5
`
`ADS7822EC/250
`
`ADS7822EC/2K5
`
`TRANSPORT
`MEDIA,
`QUANTITY
`
`Tape and Reel,
`250
`
`Tape and Reel,
`2500
`
`Tape and Reel,
`250
`
`Tape and Reel,
`2500
`
`Tape and Reel,
`250
`
`Tape and Reel,
`2500
`
`A0S7822P
`
`±2
`
`±2
`
`ADS7822PB
`
`Plastic
`DIP-8
`
`p
`
`p
`
`-4o•c to +85°C
`
`A0S7822P
`
`A0S7822P
`
`Rails, 50
`
`Rails, 50
`
`±1
`
`±1
`
`A0S7822PC
`
`±0.75
`
`±0.75
`
`ADS7822U
`
`±2
`
`ADS7822UB
`
`±1
`
`±2
`
`±1
`
`Plastic
`DIP-8
`Plastic
`DIP-8
`
`S0-8
`
`S0-8
`
`ADS7822UC
`
`±0.75
`
`±0.75
`
`S0-8
`
`p
`
`D
`
`D
`
`D
`
`-4o•c to +85°C
`
`ADS7822PB
`
`ADS7822PB
`
`-4o•c to +85°C
`
`A0S7822PC
`
`A0S7822PC
`
`Rails, 50
`
`-4o•c to +85°C
`
`ADS7822U
`
`-4o•c to +85°C
`
`ADS7822UB
`
`-4o•c to +85°C
`
`ADS7822UC
`
`ADS7822U
`
`Rails. 100
`
`ADS7822U/2K5
`
`Tape and Reel,
`2500
`
`ADS7822UB
`
`Rails. 100
`
`ADS7822UB/2K5
`
`Tape and Reel,
`2500
`
`ADS7822UC
`
`Rails. 100
`
`ADS7822UC/2K5
`
`Tape and Reel,
`2500
`
`(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
`the Tl website at www.ti.com.
`(2) Performance grade information is marked on the reel.
`
`ABSOLUTE MAXIMUM RATINGSl11
`over operating free-air temperature range (unless otherwise noted)
`
`Vee
`Analog input
`Logic input
`Case temperature
`Junction temperature
`Storage temperature
`External reference voltage
`
`ADS7822
`+6
`-0.3 to Vee+ 0.3
`-0.3 to 6
`+100
`+150
`+125
`+5.5
`
`UNIT
`V
`V
`V
`•c
`•c
`•c
`V
`
`(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
`only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
`Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
`
`2
`
`Submit Documentation Feedback
`
`Copyright © 1996-2007, Texas Instruments Incorporated
`
`Product Folder Link(s): ADS7822
`
`Petitioner Samsung Ex-1042, 0002
`
`

`

`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`ADS7822
`
`SBAS062C - JANUARY 1996-REVISED AUGUST 2007
`
`ELECTRICAL CHARACTERISTICS: +Vee = +2.7V
`A t -40 ° C to +85° C , + Vee = +2.7 V, VREF = +2.5V , fsAMPLE = 75kH z , and fcU< = 16 x fsAMPLE• unless o therwise n o t e d .
`
`PARAMETER
`
`TEST CONDITIONS
`
`ADS7822
`
`ADS7822B
`
`ADS7822C
`
`MIN
`
`TYP
`
`MAX
`
`MIN
`
`TYP
`
`MAX
`
`MIN
`
`TYP
`
`MAX
`
`+ln - (- ln)
`
`+ln - GND
`
`--ln - GND
`
`ANALOG INPUT
`Ful~scale input span
`
`Absolute input range
`
`Capacitance
`
`Leakage current
`SYSTEM PERFORMANCE
`Resolution
`
`No missing codes
`
`Integral linearity error
`
`0
`
`--0.2
`
`--0.2
`
`11
`
`- 2
`
`25
`:!:1
`
`12
`
`v • .,
`
`Vee + 02
`+1 0
`
`0
`
`--0.2
`
`--0.2
`
`v -
`Vee+ 0.2
`+1 0
`
`0
`
`--0.2
`
`--0.2
`
`v..,
`
`Vee+ 0.2
`+1.0
`
`25
`
`:!:1
`
`12
`
`25
`
`:!:1
`
`12
`
`12
`
`- 1
`
`+2
`
`11
`
`+1
`
`+0.75
`
`UNIT
`
`V
`
`V
`
`V
`
`pF
`
`µA
`
`Bits
`
`Bits
`LSB11l
`
`Differential linearity error
`
`Offset error
`
`Gain error
`
`Noise
`
`Power-supply rejection
`SAMPLING DYNAMICS
`Conversion time
`
`ACQuisition time
`Throughput rate
`
`DYNAMIC CHARACTERISTICS
`Total harmonic distortion
`v., = 2.5V.., at 1kHz
`
`- 2
`
`- 3
`
`- 3
`
`1 5
`
`:!:0.5
`
`:!:0.5
`
`33
`
`82
`
`-82
`
`71
`
`86
`
`- 1
`
`- 3
`
`- 3
`
`1.5
`
`+2
`
`+3
`
`+3
`
`12
`
`75
`
`:!:0.5
`
`:!:0.5
`
`33
`
`82
`
`-82
`
`71
`
`86
`
`--0.75
`
`--0.75
`
`- 1
`
`- 1
`
`1.5
`
`+1
`
`+3
`
`+3
`
`12
`
`75
`
`:!:0.25
`
`:!:0.25
`
`33
`
`82
`
`-82
`
`71
`
`86
`
`+0.75
`
`+1
`
`+1
`
`LSB
`
`LSB
`
`LSB
`µVrms
`
`dB
`
`12
`
`Clk Cycles
`
`Clk Cycles
`
`75
`
`kHz
`
`dB
`
`dB
`
`SINAD
`v., = 2.5V.., at 1 kHz
`Spurious-free dynamic range v., = 2.5V.., at 1 kHz
`REFERENCE OUTPUT
`
`Voltage range
`
`Resistance
`
`Current drain
`
`cs = GND, fSAMPlE = OHz
`
`~= Vee
`
`At code 710h
`
`!SAMPLE = 7 .5kHz
`
`~= Vee
`
`DIGITAL INPUT/OUTPUT
`
`Logic family
`
`v.,
`
`v ..
`
`1,H = +5!JA
`ltl = +-SµA
`
`Logic levels
`
`0.05
`
`Vee
`
`0.05
`
`Vee
`
`0.05
`
`5
`
`5
`8
`0.8
`
`0.001
`
`CMOS
`
`5
`
`5
`
`8
`
`0.8
`
`0.001
`
`CMOS
`
`40
`
`3
`
`55
`
`08
`
`2.0
`
`--0.3
`
`2.1
`
`5
`
`5
`8
`08
`
`0.001
`
`CMOS
`
`40
`
`3
`
`55
`
`08
`
`2.0
`
`--0.3
`
`2.1
`
`20
`
`--0.3
`
`2.1
`
`dB
`
`V
`
`GO
`
`GO
`µA
`
`µA
`
`µA
`
`V
`
`V
`
`V
`
`Vee
`
`40
`
`3
`
`5.5
`
`0.8
`
`Yott
`
`Va.
`
`lo" = - 250µA
`10, = 250!JA
`
`Data format
`
`Straight Binary
`
`0.4
`
`36
`
`2.7
`
`36
`
`325
`
`3
`
`Straight Binary
`
`2.7
`
`2.0
`
`2.7
`
`20
`
`200
`
`0.4
`
`36
`
`2.7
`
`36
`
`325
`
`3
`
`Straight Binary
`
`2.7
`
`2.0
`2.7
`
`20
`
`200
`
`0.4
`
`V
`
`3.6
`
`2.7
`
`3.6
`
`325
`
`3
`
`V
`
`V
`
`V
`
`µA
`
`µA
`
`µA
`
`2.7
`
`20
`
`2.7
`
`20
`
`200
`
`POWER-SUPPLY REQUIREMENTS
`Specified performance
`
`Vee
`
`Quienscent current
`
`Power doWn
`
`TEMPERATURE RANGE
`Specified performance
`
`See Notes 12> and <3>
`See Note 13>
`
`!SAMPLE = 7.5kHzl•>I•>
`!SAMPLE = 75kHz1' >
`CS-= Vee
`
`-40
`
`+85
`
`-40
`
`+85
`
`-40
`
`+85
`
`•c
`
`( 1 ) LSB m eans least s ignificant bit. With VREF e qual to +2.5V, one LS B is 0.61mV.
`(2) The maxim um cloc k rate of the ADS7 822 is less than 1.2M H z in this power- supp l y range .
`(3) See the Typical Characteristics for m ore inf o nmation.
`fcLK = 1.2 M H z , CS = Vee for 145 clo c k cycles o ut o f every 160.
`(4 )
`(5) See the Power Dissipation s e ctio n for m ore inf onmatio n regard ing lower sample rates.
`
`Copyright© 1996-2007, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`3
`
`P roduct Fold er L ink(s): ADS7822
`
`Petitioner Samsung Ex-1042, 0003
`
`

`

`ADS7822
`
`SBAS062C - JANUARY 1996-REVISED AUGUST 2007
`
`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`ELECTRICAL CHARACTERISTICS: +Vee = +5V
`At -4O° C to +85° C , +Vee = +5V, VREF = +5V, fsAMPLE = 200kHz, and fcU< = 16 x fsAMPLE• un less o t herwi se n o t e d .
`
`PARAMETER
`
`TEST CONDmONS
`
`ADS7822
`
`ADS78228
`
`MIN
`
`TYP
`
`MAX
`
`MIN
`
`TYP
`
`MAX
`
`v.~
`Vee+ 0.2
`+1.0
`
`0
`
`--0.2
`
`--0.2
`
`v.~
`Vee+ 0.2
`+1.0
`
`+In - (-In)
`
`+ln - GND
`
`-ln -GND
`
`ANALOG INPUT
`Ful~scale input span
`
`Absolute input range
`
`Capacitance
`
`Leakage current
`SYSTEM PERFORMANCE
`Resolution
`
`No missing codes
`
`Integral linearity error
`
`Differential linearity error
`
`Offset error
`
`Gain error
`
`Noise
`
`Power-supply rejection
`SAMPLING DYNAMICS
`Conversion time
`
`ACQuisition time
`Throughput rate
`
`DYNAMIC CHARACTERISTICS
`Total harmonic distortion
`
`SINAD
`
`Spurious-free dynamic range
`
`v,. = 5Vpp at 10kHz
`v,. = sv .. at 10kHz
`v,. = sv .. at 10kHz
`
`0
`
`--0.2
`
`--0.2
`
`11
`
`- 2
`
`- 3
`
`-4
`
`1.5
`
`25
`
`~1
`
`12
`
`~.8
`
`33
`
`70
`
`-78
`
`71
`
`UNIT
`
`V
`
`V
`
`V
`
`pF
`µA
`
`Bits
`
`Bits
`LSB11l
`
`LSB
`
`LSB
`
`LSB
`µVrms
`
`dB
`
`12
`
`- 1
`
`- 1
`
`- 3
`
`- 3
`
`1.5
`
`+2
`
`+3
`
`+4
`
`12
`
`200
`
`25
`
`~1
`
`12
`
`~ .5
`
`33
`
`70
`
`- 78
`
`71
`
`79
`
`+1
`
`+1
`
`+3
`
`+3
`
`12
`
`Clk Cycles
`
`Clk Cycles
`
`200
`
`kHz
`
`dB
`
`dB
`
`REFERENCE OUTPUT
`
`Voltage range
`
`Resistance
`
`Current drain
`
`DIGITAL INPUT/OUTPUT
`
`Logic family
`
`CS = GND, t,,.... .... = 0Hz
`
`~
`
`= Vee
`
`At code 710h
`
`t.,,...LE = 12.5kHz
`
`~
`
`= Vee
`
`V1H
`
`VIL
`
`VOH
`
`VOL
`
`1., = +5µA
`
`I._ = +5µA
`
`Iott = - 250µA
`
`IOI. = 250µA
`
`Logic levels
`
`Data format
`
`POWER-SUPPLY REQUIREMENTS
`Specified performance
`
`Vee
`Quienscent current
`
`PowerdoWn
`
`TEMPERATURE RANGE
`Specified performance
`
`f.,,...LE = 200kHz
`
`i'.:S = Vee
`
`79
`
`5
`
`5
`
`40
`
`2.5
`
`0001
`
`CMOS
`
`Straight Binary
`
`320
`
`005
`
`3.0
`
`--0.3
`
`3.5
`
`4.75
`
`-40
`
`Vee
`
`0.05
`
`5
`
`5
`40
`
`2.5
`
`0.001
`
`CMOS
`
`3.0
`
`--0.3
`
`3.5
`
`4.75
`
`-40
`
`Straight Binary
`
`320
`
`100
`
`3
`
`5.5
`
`0.8
`
`0.4
`
`525
`
`550
`
`3
`
`+85
`
`dB
`
`V
`
`GO
`
`GO
`µA
`µA
`
`µA
`
`V
`
`V
`
`V
`
`V
`
`V
`
`µA
`
`µA
`
`Vee
`
`100
`
`3
`
`5.5
`
`0.8
`
`0.4
`
`5.25
`
`550
`
`3
`
`+85
`
`•c
`
`(1) L SB means least sign ificant bit W ith VREF equal to +5V, o n e LSB is 1 .22mV.
`
`4
`
`Submit Documentation Feedback
`
`Copyright © 1996-2007, Texas Instruments Incorporated
`
`P rod uct F o ld er L in k (s): ADS7822
`
`Petitioner Samsung Ex-1042, 0004
`
`

`

`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`ADS7822
`
`SBAS062C - JANUARY 1996-REVISED AUGUST 2007
`
`PIN CONFIGURATION
`
`D, DGK, OR P PACKAGE
`SO, MSOP, or DIP
`(TOP VIEW)
`
`ADS7822
`
`+In
`
`In
`
`GND
`
`2
`
`3
`
`4
`
`8
`
`+Vee
`
`7 DCLOCK
`
`6 Dour
`
`5 CS/SHON
`
`PIN ASSIGNMENTS
`
`DESCRIPTION
`
`Reference input
`
`Noninverting input
`
`Inverting input. Connect to ground or to remote ground sense point.
`
`Ground
`Chip select when low; Shutdown mode when high.
`
`The serial output data word is comprised of 12 bits of data. In operation, the data are valid on he falling edge of DCLOCK. The
`second dock pulse after the falling edge of 'CS' enables he serial output. After one null bit, the data are valid for the next edges.
`
`Data clock synchroniZes the serial data transfer and determines conversion speed.
`
`Power supply
`
`PIN
`
`NAME
`
`VREF
`+In
`
`- In
`
`GND
`
`'CS'/SHDN
`
`DotJT
`
`DCLOCK
`
`+Vee
`
`NO.
`1
`
`2
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`Copyright© 1996-2007, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`5
`
`Product Folder Link(s): ADS7822
`
`Petitioner Samsung Ex-1042, 0005
`
`

`

`ADS7822
`
`SBAS062C - JANUARY 1996-REVISED AUGUST 2007
`
`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`TYPICAL CHARACTERISTICS
`At TA = +25°C, Vee = +2.7V, VREF = +2.5V, fsAMPLE = 75kHz, fcLI< = 16 x fsAMPLE• unless otherwise specified.
`
`INTEGRAL LINEARITY ERROR
`VS CODE
`
`DIFFERENTIAL LINEARITY ERROR
`VS CODE
`
`.oJ.,ll
`..,
`I f' ·· 1 ..
`
`,.
`
`~
`
`~
`
`" "
`
`. .... &
`
`,.,,,,,.,,,.,, n• .. • TI .. ~, "
`
`11" " n·•·
`
`..
`
`y
`
`...... i. ,J.111
`... ,,. ,. ,,.
`
`0
`
`2048
`Code
`Figure 1.
`
`SUPPLY CURRENT
`vs TEMPERATURE
`
`4095
`
`1.00 '-------''-------'-----'----'-----'-----'
`4095
`0
`2048
`Code
`Figure 2.
`
`POWER-DOWN SUPPLY CURRENT
`vs TEMPERATURE
`
`cir
`
`uJ
`~
`
`rn d. e
`si C :.:;
`e en
`
`.Sl
`C
`
`1.00
`
`0.75
`
`0.50
`
`0.25
`
`0.00
`
`0.25
`
`0.50
`
`0.75
`
`1.00
`
`350
`
`300
`
`100
`
`50
`
`-
`
`----
`
`----
`
`-
`
`<' .s
`c
`Q)
`t:
`:::,
`C)
`2-
`a.
`a.
`:::,
`rn
`
`120
`
`100
`
`80
`
`60
`
`40
`
`20
`
`0
`
`50
`
`25
`
`0
`
`50
`25
`Temperature ("C)
`Figure 3.
`
`QUIESCENT CURRENT
`vs Vee
`
`75
`
`100
`
`50
`
`25
`
`i
`i :i
`C)
`c
`~ Q) ·s
`
`0
`
`400
`
`350
`
`300
`
`250
`
`200
`
`150
`
`100
`
`1000
`
`'N'
`100
`:I:
`~
`Q)
`to
`a::
`Q) a.
`~
`rn
`
`10
`
`--------
`~~
`
`L--""""
`
`2
`
`3
`Voc M
`Figure 5.
`
`4
`
`5
`
`----
`
`0
`
`50
`25
`Temperature (°C)
`Figure 4.
`
`75
`
`100
`
`MAXIMUM SAMPLE RATE
`vs Vee
`
`/
`
`I
`I
`I
`
`I
`
`2
`
`4
`
`5
`
`3
`Voc M
`Figure 6.
`
`6
`
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`INSTRUMENTS
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`
`ADS7822
`
`SBAS062C- JANUARY 1996-REVISED AUGUST 2007
`
`TYPICAL CHARACTERISTICS (continued)
`At TA = +25°C, Vee = +2.7V, VREF = +2.SV, fsAMPLE = 75kHz, feLK = 16 x fsAMPLE• unless otherwise specified.
`
`CHANGE IN OFFSET
`vs REFERENCE VOLTAGE
`
`CHANGE IN OFFSET
`vs TEMPERATURE
`
`12
`
`1.0
`
`- Vee= SI/
`
`0.8
`ffi'
`rn
`d. 0.6
`~ 0.4
`,jg
`02
`0
`.S
`~
`"' J::
`C
`
`0.0
`02
`0.4
`
`C)
`
`0.6
`
`0.8
`
`2.5
`
`2.0
`
`- V ee= 5V
`
`1.5
`
`1.0
`
`0.5
`
`0.0
`
`ffi'
`~
`C
`·.;
`(!)
`.S
`Q)
`en
`f;j
`J::
`C)
`
`.........___
`
`. /
`
`---
`
`0.6
`
`0.4
`
`ffi'
`rn
`,d. 02
`C)
`i(i
`E
`,g
`~ 02
`c?l
`
`0
`
`0.4
`
`----
`
`-
`
`-
`
`-------
`
`4
`
`5
`
`50
`
`25
`
`0.6
`
`2
`
`3
`Reference Voltage (V)
`Figure 7.
`
`CHANGE IN GAIN
`vs REFERENCE VOLTAGE
`
`75
`
`100
`
`50
`25
`0
`Temperature (°C)
`Figure 8.
`
`CHANGE IN GAIN
`vs TEMPERATURE
`
`0.15
`
`0.10
`
`0
`
`0.05
`
`~
`
`-
`
`---,,.,.,..,--
`
`----
`
`ffi'
`rn
`,d. 0.05
`~
`"' E
`Ill
`,g
`~
`c?l
`
`0.10
`
`0.15
`
`------
`
`2
`
`3
`Reference Voltage (V)
`Figure 9.
`
`4
`
`5
`
`50
`
`25
`
`0
`
`50
`25
`Temperature {°C)
`Figure 10.
`
`75
`
`100
`
`EFFECTIVE NUMBER OF BITS
`vs REFERENCE VOLTAGE
`
`PEAK-TO-PEAK NOISE
`vs REFERENCE VOLTAGE
`
`0.5
`
`1.0
`
`1.5
`
`12.00
`
`= V ee= 5V
`
`\
`\
`
`' '\
`' ' "
`
`10
`
`9
`ffi' 8
`~ 7
`Q) ·i!l 6
`z
`i
`5
`~ 4
`~
`"' c'f 2
`"' 3
`
`10
`
`0
`0.1
`
`11 .25
`
`11 .00
`
`11 .75
`cii"
`.§. 11 .50
`~
`0
`cii
`.0
`E
`::, 10.75
`z
`.2: 10.50
`ti
`~ 10.25
`10.00
`
`Q)
`
`V ee= 5V
`
`I,' ..
`
`,
`
`J
`
`I
`I
`
`J
`
`I
`
`I
`
`0.1
`
`Reference Voltage (V)
`Figure 11.
`
`....
`
`"'-
`
`r--.
`
`-
`
`Reference Voltage (V)
`Figure 12.
`
`10
`
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`
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`

`ADS7822
`
`SBAS062C - JANUARY 1996-REVISED AUGUST 2007
`
`TYPICAL CHARACTERISTICS (continued)
`At TA = +25°C, Vee = +2.7V, VREF = +2.SV, fsAMPLE = 75kHz, feLK = 16 x fsAMPLE• unless otherwise specified.
`
`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`SPURIOUS FREE DYNAMIC RANGE AND
`SIGNAL-TO-NOISE RATIO vs FREQUENCY
`
`TOTAL HARMONIC DISTORTION
`vs FREQUENCY
`0 _____ .,....,........,.,.... ______ ,........,..
`
`, Spurious Free Dynamic Range
`
`- .....
`
`'
`I
`Signal to Noise Ratio
`
`-
`
`~
`
`100
`
`90
`
`80
`ffi' 70
`~
`a: 60
`z fJ)
`'C
`5j
`a:
`C
`LL
`fJ)
`
`50
`40
`
`30
`
`20
`10
`
`0
`
`10
`Frequency (kHz)
`Figure 13.
`
`100
`
`10 l----+-+-+-1-+++++---+--+-+-+-++++-1
`ffi'
`~ 20 1-----+--+-+-1--+-+-+++---+---+---+--+-+-+++1
`
`30 l----+-+-+-1-+++++---+--+-+-+-++++-1
`
`40 l----+-+-+-1-+++++---+--+-+-+-++++-1
`50 ::=====t==t=+=:=++++t:::====t==t=+:J~:;;;:::::::;
`60 ~==~~=t~=EE81:~2~~~=E~~~SlE
`70 1----+-+--+-:::i.-+-"Fl-++---+---+-+-+-++++I
`80 t::::;;~~::t::'.+--=t=ttttt====t==t=t~~ttt~
`90 l----+-+-+-1-+++++---+--+-+-+-++++-1
`100 ..__ _ _.__ ........................ ______ .......................
`10
`100
`Frequency {kHz)
`Figure 14.
`
`SIGNAL-TO-(NOISE+DISTORTION)
`vs FREQUENCY
`
`SIGNAL-TO-(NOISE+DISTORTION)
`vs INPUT LEVEL
`
`100 - - - - - - - - - - - - - - - - - (cid:173)
`ffi' 00 1-----+--+-+-1--+-++++---+---+---+--+-+-+-++1
`~ ro i---+-+-+-1-+++++---+--+-+-+-++++-1
`* 00 ~====t==t=t=t=t+++~~~~:t~=t=t~~t++~
`'2
`1---+--+-+-+-+++++----+-+-+--11-++++-1
`~ ro p - "'"+"-+-+-i-!:±+++---+--+-+-+-++++-1
`~ ~ ~ .. ====t==t=t=tt1ttt====t~~t=f~ttiiE
`m
`·o 40 1-----+--+-+-1--+-++++---+---+---+--+-+-+-++1
`z
`ro 1-----+--+-+-1--+-++++---+---+---+--+-+-+-++1
`y
`!?
`~ ~ ---+-+-+-1-+++++---+--+-+-+-++++-1
`~ 10 1-----+--+-+-1--+-++++---+---+---+--+-+-+-++1
`0 __ ....__ ........................ ______ .......................
`
`ffi' 80
`'C
`:::: 70
`8
`
`~ 60 * i:5 50
`
`+
`0 'a 40
`a:
`m 30
`·o
`z
`-
`~
`~ 10
`C>
`en o
`
`20
`
`_.....
`l...---'
`
`l...---' --
`
`----V""
`
`_.....
`l,_......---'
`
`10
`Frequency {kHz)
`Figure 15.
`
`REFERENCE CURRENT
`vs SAMPLE RATE
`
`100
`
`40
`
`35
`
`30
`
`15
`25
`20
`Input Level (dB)
`Figure 16.
`
`10
`
`5
`
`0
`
`REFERENCE CURRENT vs TEMPERATURE
`(Code= 710h)
`
`14
`
`12
`
`6
`
`i 10
`c
`~ 8
`:::,
`C)
`2l
`C
`~
`.,
`,l!!
`a:
`
`,,,,.,..
`~
`0 ~
`
`~
`
`------
`
`14
`
`12
`
`g:
`c 10
`~
`:i
`C)
`~
`~ 6
`i a:
`
`8
`
`4
`
`2
`
`60
`
`75
`
`~
`
`25
`
`0
`
`25
`~
`Temperature (°C)
`Figure 18.
`
`75
`
`100
`
`ro
`45
`Sample Rate {kHz)
`Figure 17.
`
`4
`
`2
`
`0
`
`15
`
`8
`
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`
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`
`

`

`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`ADS7822
`
`SBAS062C- JANUARY 1996-REVISED AUGUST 2007
`
`TYPICAL CHARACTERISTICS (continued)
`At TA = +25°C, Vee = +2.7V, VREF = +2.SV, fsAMPLE = 75kHz, feLK = 16 x fsAMPLE• unless otherwise specified.
`
`POWER-SUPPLY REJECTION
`vs RIPPLE FREQUENCY
`
`POWER-SUPPLY REJECTION
`vs RIPPLE FREQUENCY
`
`Vcc= 2.7V
`Ripple = 500mV pp
`v ,N = 1.25VDC
`VREF = 2.SI/
`
`v -
`
`0
`
`10
`
`20
`
`30
`ar 40
`:s
`a: 50
`rn
`a.
`
`60
`
`70
`
`80
`
`90
`
`...
`
`v v
`
`,,,
`
`/
`
`..
`
`PSR (dB) = 20Iog(500mV/,W 0 )
`where tN 0 = change in digital result
`
`0
`
`10
`
`20
`
`30
`ar 40
`:s
`a:
`50
`rn
`a.
`
`60
`
`70
`
`80
`
`90
`
`1k
`
`10k
`
`100k
`Ripple Frequency (Hz)
`Figure 19.
`
`1M
`
`10M
`
`10
`
`CHANGE IN INTEGRAL LINEARITY
`AND DIFFERENTIAL LINEARITY
`vs REFERENCE VOLTAGE
`
`020
`
`Vee= SI/
`Ripple = 500mV pp
`v ,N= 2.5VDC
`VREF = 5V
`
`;I
`
`,,.,.,,
`
`;I
`
`,,.,.,,
`
`;I
`
`I v
`
`I--'
`PSR (dB) = 20Iog(500mV/,W 0 )
`where tN 0 = change in digital result
`
`100k
`10k
`1k
`Ripple Frequency (Hz)
`Figure 20.
`
`1M
`
`10M
`
`0.15
`
`~
`
`ar rn
`::::!.
`8 0.10
`JII .,
`a:
`?;
`"' +
`E
`,g
`~ 0.05
`c?l
`
`0.05
`
`0.00
`
`0.10
`
`Change in Differential
`U nearity (LSB)
`
`2
`
`3
`Reference Voltage (V)
`Figure 21 .
`
`4
`
`5
`
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`
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`

`ADS7822
`
`SBAS062C- JANUARY 1996-REVISED AUGUST 2007
`
`THEORY OF OPERATION
`
`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`The range of the -In input is limited to -0.2V to +1 V.
`Because of this, the differential input can be used to
`reject only small signals that are common to both
`inputs. Thus, the -In input is best used to sense a
`remote signal ground that may move slightly with
`respect to the local ground potential.
`The input current on the analog inputs depends on a
`number of factors: sample rate, input voltage, source
`impedance, and power-down mode. Essentially, the
`current
`into
`the ADS7822 charges
`the
`internal
`capacitor array during the sample period. After this
`capacitance has been fully charged, there is no
`further input current. The source of the analog input
`voltage must be able to charge the input capacitance
`(25pF) to a 12-bit settling level within 1.5 clock
`cycles. When the converter goes into the hold mode
`or while it is in the power-down mode, the input
`impedance is greater than 1 GO.
`Care must be taken regarding the absolute analog
`input voltage. To maintain
`the
`linearity of the
`converter, the -In input should not drop below GND -
`200mV or exceed GND + 1V. The +In input should
`always remain within the range of GND - 200mV to
`Vee + 200mV. Outside of these ranges, the converter
`linearity may not meet specifications.
`
`REFERENCE INPUT
`The external reference sets the analog input range.
`The ADS7822 operates with a reference in the range
`to Vee• There are several
`important
`of 50mV
`implications of this.
`As the reference voltage is reduced, the analog
`voltage weight of each digital output code is reduced.
`This is often referred to as the LSB (least significant
`bit) size and is equal to the reference voltage divided
`by 4096. This means that any offset or gain error
`inherent in the AID converter will appear to increase,
`in terms of LSB size, as the reference voltage is
`reduced.
`
`The ADS7822 is a classic successive approximation
`register (SAR) AID converter. The architecture is
`based on capacitive redistribution
`that inherently
`includes a sample/hold function. The converter is
`fabricated on a 0.6µ CMOS process. The architecture
`and process allow the ADS7822 to acquire and
`convert an analog signal at up
`to 200,000
`conversions per second while consuming very little
`power.
`The ADS7822 requires an external reference, an
`external clock, and a single power source (V cc). The
`external reference can be any voltage between 50mV
`and V cc• The value of the reference voltage directly
`sets the range of the analog input. The reference
`input current depends on the conversion rate of the
`ADS7822.
`The external clock can vary between 1 0kHz (625Hz
`throughput) and 3.2MHz (200kHz throughput). The
`duty cycle of the clock is essentially unimportant as
`long as the minimum high and low times are at least
`400ns for a supply range between 2.7V to 3.6V, or
`125ns for a supply range between 4.75V to 5.25V.
`The minimum clock frequency is set by the leakage
`on the capacitors internal to the ADS7822.
`The analog input is provided to two input pins: +In
`and -In. When a conversion
`is
`initiated,
`the
`differential input on these pins is sampled on the
`internal capacitor array. While a conversion is in
`progress, both inputs are disconnected from any
`internal function.
`The digital result of the conversion is clocked out by
`the DCLOCK input and is provided serially, most
`significant bit first, on the DouT pin. The digital data
`that is provided on the DouT pin is for the conversion
`currently in progress-there is no pipeline delay. It is
`possible to continue to clock the ADS7822 after the
`conversion is complete and to obtain the serial data
`least significant bit first. See the Digital Interface
`section for more information.
`
`ANALOG INPUT
`for a
`input pins allow
`The +In and
`-In
`some
`signal. Unlike
`pseudo-differential
`input
`converters of this type, the -In input is not resampled
`later in the conversion cycle. When the converter
`goes into the hold mode, the voltage difference
`between +In and -In is captured on the internal
`capacitor array.
`
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`INSTRUMENTS
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`
`The noise inherent in the converter will also appear to
`increase with lower LSB size. With a 2.SV reference,
`the internal noise of the converter typically contributes
`only 0.32 LSB peak-to-peak of potential error to the
`output code. When the external reference is S0mV,
`the potential error contribution from the internal noise
`will be 50 times larger- 16 LSBs. The errors due to
`the internal noise are gaussian in nature and can be
`reduced by averaging consecutive conversion results.
`For more information regarding noise, consult the
`typical characteristic curves Effective Number of Bits
`vs Reference Voltage and Peak-to-Peak Noise vs
`Reference Voltage. Note that the effective number of
`bits (ENOS) figure
`is calculated based on
`the
`converter signal-to-(noise + distortion) ratio with a
`1 kHz, 0dB input signal. SINAD is related to ENOS as
`follows:
`SINAD = 6.02 • ENOS + 1.76
`With lower reference voltages, extra care should be
`taken to provide a clean layout including adequate
`bypassing, a clean power supply, a
`low-noise
`reference, and a low-noise input signal. Because the
`LSB size is lower, the converter will also be more
`sensitive to external sources of error such as nearby
`digital signals and electromagnetic interference.
`
`ADS7822
`
`SBAS062C-JANUARY 1996-REVISED AUGUST 2007
`
`DIGITAL INTERFACE
`
`Signal Levels
`
`The digital inputs of the ADS7822 can accommodate
`logic levels up to 6V regardless of the value of V cc•
`Thus, the ADS7822 can be powered at 3V and still
`accept inputs from logic powered at SV.
`The CMOS digital output (DouT) will swing 0V to Vee•
`If V cc is 3V and this output is connected to a SV
`CMOS logic input, then that IC may require more
`supply current than normal and may have a slightly
`longer propagation delay.
`
`Serial Interface
`The ADS7822 communicates with microprocessors
`and other digital systems via a synchronous 3-wire
`serial interface, as shown in Figure 22 and Table 1.
`The DCLOCK signal synchronizes the data transfer
`with each bit being transmitted on the falling edge of
`DCLOCK. Most receiving systems will capture the
`bitstream on the rising edge of DCLOCK. However, if
`the minimum hold time for DouT is acceptable, the
`system can use the falling edge of DCLOCK to
`capture each bit.
`
`l- - - - - - - - ~c - - - - - - --
`
`CS/SHON 7
`- I 1-
`
`tsucs
`
`1
`
`n._ _______ _
`f - j ::~'
`
`DCLOCK
`
`Note: (1) After completing the data transfer, if further clocks are applied with CS LOW,
`the AID w ill output LSB Fl rst data then followed with zeroes indefinitely.
`
`l - - - - - - - - ~c - - - - - - - - - - - - - - - - - - - -1
`
`r-i...
`
`CS/SHON 7
`-1 l-
`
`tsucs
`
`DCLOCK
`
`~
`
`1- - - - - -lcONv - - - - - -- - - - - - - - tDATA - - - - - -- 1
`
`B1 I BO B1
`
`Hi-2
`
`Note: (1) After completing the data transfer, if further clocks are applied with CS LOW,
`the AID w ill output zeroes I ndefinltely.
`
`tDATA: During this time, the bias current and the comparator power down and the reference input
`becomes a high impedance node, leaving the CLK running to clock out LSB first data or zeroes.
`
`Figure 22. Basic Timing Diagrams
`
`Copyright© 1996--2007. Texas Instruments Incorporated
`
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`

`ADS7822
`
`SBAS062C - JANUARY 1996-REVISED AUGUST 2007
`
`Table 1. Timing Specifications (-40°C to +85°C)
`
`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`SYMBOL
`
`DESCRIPTION
`
`tsMPL
`
`b v
`
`lcvc
`
`lcso
`
`tsucs
`
`li.oo
`
`Analog input sample time
`
`Conversion time
`
`Cycle time
`
`CS falling to DCLOCK low
`
`~ falling to DCLOCK rising
`
`DCLOCK falling to current DoUT not valid
`
`DCLOCK falling to next DouT valid
`
`MIN
`1.5
`
`16
`
`0.03
`15
`
`Vee = 2.7V
`TYP
`
`12
`
`130
`
`40
`
`MAX
`
`2.0
`
`0
`
`1000
`
`200
`
`80
`
`MIN
`1.5
`
`16
`
`0.03
`15
`
`Vee = SV
`TYP
`
`12
`
`85
`
`25
`
`MAX
`
`2.0
`
`0
`
`1000
`
`150
`
`50
`
`UNITS
`
`Clk Cydes
`
`Clk Cydes
`
`Clk Cydes
`
`ns
`
`1,.15
`ns
`
`ns
`
`ns
`
`t.oo
`t.,;.
`fen
`
`" t,
`
`~ rising to DotJT tri-state
`
`DCLOCK falling to DouT enabled
`
`DoUTfall time
`
`DoUT rise time
`
`75
`
`90
`110
`
`175
`
`200
`
`200
`
`50
`70
`
`60
`
`100
`
`100
`
`100
`
`ns
`
`ns
`
`ns
`
`1.4V
`
`3kO
`
`OoUT 1 - - - - - - - -<1Test Point
`
`100pF
`ICLDAD
`
`load Circuit for tdOO, t,, and t,
`
`OCLOCK
`
`tdOO -
`-
`---~--~- ---------------~H
`----4-----=,r- - - - - - - - - - - - - - - - - VOL
`l,,oo -
`
`Voltage Waveforms for 0 0 UT Delay T imes, 1000
`
`CS/SHON
`
`OOUT
`Waveform 1!1>
`
`OOUT
`Waveform 212>
`
`--------VoH
`
`------VoL
`
`Voltage Waveforms for 0 0 UT Rise and Fall Times, t,, \
`
`Test Point
`
`OoUT 1--
`
`3kO
`- ~ ,111,,t'-- a
`
`100pF
`
`ICLDAD
`
`load Circuit for Ids and t..,
`
`\,;s Waveform 2, t..,
`
`\,;s Waveform 1
`
`CS/SHON
`
`OCLOCK
`
`Voltage Waveforms for lo;s
`
`Voltage Waveforms fort..,
`
`NOTES: (1) Waveform 1 is for an output with internal oondltions such that the output
`is HIGH unless disabled by the output oontrol.
`
`(2) Waveform 2 is for an output with internal conditions such that the output
`is LOW unless disabled by the output control .
`
`Figure 23. Timing Diagrams and Test Circuits for the Parameters in Table 1
`
`12
`
`Submit Documentation Feedback
`
`Copyright © 1996-2007, Texas Instruments Incorporated
`
`Product Folder Link(s): ADS7822
`
`Petitioner Samsung Ex-1042, 0012
`
`

`

`'!!1TEXAS
`INSTRUMENTS
`www.ti.com
`
`A falling ~ signal initiates the conversion and data
`transfer. The first 1.5 to 2.0 clock periods of the
`conversion cycle are used to sample the input signal.
`After the second falling DCLOCK edge, DouT is
`enabled and outputs a low value for one clock period.
`For the next 12 DCLOCK periods, DouT outputs the
`conversion result, most significant bit first.
`After the least significant bit (BO) has been output,
`subsequent clocks repeat the output data, but in a
`format. After the most
`least significant bit first
`significant bit (B 11 ) has been repeated, DOUT will
`tri-state. Subsequent clocks have no effect on the
`converter. A new conversion is initiated only when 'C'S
`is taken high and returned low.
`
`Data Format
`The output data from the ADS7822 is in straight
`binary format, as shown in Table 2. This table
`represents the ideal output code for the given input
`voltage and does not include the effects of offset,
`gain error, or noise.
`
`Table 2. Ideal Input Voltages and Output Codes
`
`DESCRIPTION
`
`ANALOG VALU E
`
`DIGITAL OUTPUT
`STRAIGHT BINARY
`
`Full-Scale range
`
`Least significant
`bit (LSB)
`
`Full-Scale
`
`Midscale
`
`Midscale - 1 LSB
`Zero
`
`VREF
`
`VREF/4096
`
`VREF- 1 LSB
`
`VREF/2
`VREF/2 - 1 LSB
`OV
`
`BINARY CODE
`111 111 1111 11
`
`HEX CODE
`FFF
`
`1000 0000 0000
`
`011 1 11 11 11 11
`
`0000 0000 0000
`
`800
`
`7FF
`
`000
`
`POWER DISSIPATION
`The architecture of the converter, the semiconductor
`fabrication process, and a careful design allow the
`ADS7822 to convert at up to a 75kHz rate while
`requiring very little power. Still, for the absolute
`lowest power dissipation, there are several things to
`keep in mind.
`The power dissipation of the ADS7822 scales directly
`with conversion rate. So, the first step to achieving
`the lowest power dissipation is to find the lowest
`conversion rate that will satisfy the requirements of
`the system.
`In addition, the ADS7822 goes into power-down
`mode under two conditions: when the conversion is
`complete and whenever ~ is high (see Figure 22).
`Ideally, each conversion should occur as quickly as
`possible; preferably, at a 1.2MHz clock rate. This
`way, the converter spends the longest possible time
`in the power-down mode. This is very important since
`the converter not only uses power on each DCLOCK
`
`ADS7822
`
`SBAS062C-JANUARY 1996-REVISED AUGUST 2007
`
`transition (as is typical for digital CMOS components),
`but also uses some current for the analog circuitry,
`such as
`the comparator. The analog section
`dissipates power continuously, until the power-down
`mode is entered.
`Figure 24 shows the current consumption of the
`ADS7822 versus sample rate. For this graph, the
`converter is clocked at 1.2MHz regardless of the
`sample rate-~ is high for the remaining sample
`period. Figure 25 also shows current consumption
`versus sample rate. However, in this case, the
`DCLOCK period is 1116th of the sample period- 'C'S
`is high for one DCLOCK cycle out of every 16.
`
`1000
`
`1 100
`c
`~
`:i
`(.)
`2-
`8:
`::,
`rn
`
`10
`
`1
`0.1
`
`STA= 2s• c
`~ feLK = 1.2MHz
`
`i..- .,/
`
`- Yee= 2.7V
`
`VREF = 2.5V
`
`10
`
`100
`
`Vee= 5.0V
`VREF = 5.0V
`/
`
`i..-,,,,.
`
`~
`
`-
`
`1
`
`Sample Rate (kHz)
`
`Figure 24. Maintaining f cLK at the Highest
`Possible Rate Allows the Supply Current to Drop
`Linearly with the Sample Rate
`
`1000
`
`1 100
`c
`~
`:i
`(.)
`2-
`8:
`::,
`rn
`
`10
`
`1
`0.1
`
`TA= 2s• c
`Vcc= 2.7V
`VREF = 2.5V
`fcLK = 16 • fSAMPLE
`
`1
`
`10
`
`100
`
`Sample Rate (kHz)
`
`Figure 25. Scaling f cLK Reduces the Supply
`Current Only Slightly with the Sample Rate
`
`Copyright© 1996-2007, Texas Instruments Incorporated
`
`Submit Documentation Feedback
`
`13
`
`Product Folder Link(s): ADS7822
`
`Petitioner Samsung Ex-1042, 0013
`
`

`

`ADS7822
`
`SBAS062C - JANUARY 1996- REVISED AUGUST 2007
`
`the
`important distinction between
`is an
`There
`power-down mode that is entered after a conversion
`is complete and the full power-down mode