`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`CIRRUS LOGIC, INC.;
`OMNIVISION TECHNOLOGIES, INC.; AND
`AMS SENSORS USA INC.,
`Petitioner,
`
`
`v.
`
`
`GREENTHREAD, LLC,
`Patent Owner.
`
`
`Case No. IPR2024-00020
`Patent No. 11,121,222
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO.
`11,121,222
`UNDER 35 U.S.C. §§ 312 AND 37 C.F.R. § 42.104
`
`
`
`
`
`

`

`
`
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES ............................................................................ 1
`A.
`Real Party-In-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Counsel Service Information ................................................................ 3
`D.
`37 C.F.R. §42.8(b)(4): Service Information ......................................... 5
`PAYMENT OF FEES UNDER 37 C.F.R. §42.103 ....................................... 5
`III.
`IV. CERTIFICATION OF GROUNDS FOR STANDING ................................. 5
`V. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED ................... 6
`A.
`Prior Art Printed Publications .............................................................. 6
`B.
`Relief Requested ................................................................................... 7
`VI. PERSON OF ORDINARY SKILL IN THE ART ......................................... 7
`VII. CLAIM CONSTRUCTION ........................................................................... 8
`VIII. SPECIFIC GROUNDS FOR PETITION ....................................................... 9
`A. Ground I: .............................................................................................. 9
`1.
`Claims 1/21/39/41/42 ................................................................. 9
`2.
`Claims 2/23: ............................................................................. 33
`3.
`Claims 3/24: ............................................................................. 33
`4.
`Claims 4/25: ............................................................................. 33
`5.
`Claims 5/26: ............................................................................. 34
`6.
`Claims 6/27: ............................................................................. 35
`7.
`Claims 7/32: ............................................................................. 36
`
`ii
`
`

`

`
`
`B.
`
`8.
`Claim 8: .................................................................................... 36
`Claims 9/28: ............................................................................. 37
`9.
`10. Claims 12/31: ........................................................................... 38
`11. Claim 13: .................................................................................. 38
`12. Claim 14: .................................................................................. 39
`13. Claims 16/34: ........................................................................... 40
`14. Claim 17: .................................................................................. 41
`15. Claims 18/36: ........................................................................... 41
`16. Claims 19/37: ........................................................................... 41
`17. Claims 20/38: ........................................................................... 42
`18. Claim 33: .................................................................................. 43
`19. Claim 35: .................................................................................. 43
`20. Claim 40: .................................................................................. 47
`Ground II: ........................................................................................... 47
`1.
`Claim 1/21/39/41/42 ................................................................ 49
`2.
`Claims 2/23: ............................................................................. 66
`3.
`Claims 4/25: ............................................................................. 66
`4.
`Claims 5/26: ............................................................................. 67
`5.
`Claims 6/27: ............................................................................. 68
`6.
`Claims 7/32: ............................................................................. 69
`7.
`Claim 8: .................................................................................... 69
`8.
`Claims 9/28: ............................................................................. 70
`9.
`Claims 12/31: ........................................................................... 71
`
`iii
`
`

`

`
`
`10. Claim 13: .................................................................................. 71
`11. Claim 14: .................................................................................. 72
`12. Claim 15: .................................................................................. 74
`13. Claims 16/34: ........................................................................... 74
`14. Claim 17: .................................................................................. 75
`15. Claims 18/36: ........................................................................... 75
`16. Claims 19/37: ........................................................................... 77
`17. Claims 20/38: ........................................................................... 78
`18. Claim 22: .................................................................................. 79
`19. Claim 33: .................................................................................. 80
`20. Claim 35: .................................................................................. 80
`21. Claim 40: .................................................................................. 82
`GROUNDS III/IV .............................................................................. 82
`C.
`D. GROUNDS V/VI ............................................................................... 88
`IX. THE BOARD SHOULD INSTITUTE IPR ................................................. 90
`A.
`35 U.S.C. § 314(a) .............................................................................. 90
`B.
`35 U.S.C. § 325(d).............................................................................. 92
`C.
`Prior Terminated Petitions Do Not Warrant Denying Institution ...... 95
`CERTIFICATION OF WORD COUNT ........................................................ 1
`
`
`
`
`
`
`iv
`
`

`

`
`
`Exhibit
`No.
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008A
`
`1008B
`
`1008C
`
`1008D
`
`1009
`
`1010
`
`1011
`
`TABLE OF EXHIBIT
`
`Description
`
`U.S. Patent No. 11,121,222 to Rao (the “’222 Patent”)
`
`Prosecution History of the ’222 Patent
`
`Declaration of Sanjay Banerjee, PhD
`
`Curriculum Vitae of Sanjay Banerjee, PhD
`
`Publication Declaration of Sean O’Bryan for Maziasz (“O’Bryan
`Decl.”)
`
`U.S. Patent Application Publication No. 2003/0183856 to
`Wieczorek (“Wieczorek”)
`
`U.S. Patent No. 6,043,114 to Kawagoe, et al. (“Kawagoe”)
`
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol 1,
`Lattice Press (2000) (“Wolf.1”)
`
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 2,
`Lattice Press (2000) (“Wolf.2”)
`
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 3,
`Lattice Press (2000) (“Wolf.3”)
`
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 4,
`Lattice Press (2000) (“Wolf.4”)
`
`Wang and Agrawal, Single Event Upset: An Embedded Tutorial,
`21st Intl Conf on VLSI Design, IEEE 2008 (“Wang”)
`
`U.S. Patent No. 4,481,522 (“Jastrzebski”)
`
`Publication Declaration of Martin L. Knott for Rabaey (“Knott-
`Rabaey Decl.”)
`
`v
`
`

`

`
`
`Exhibit
`No.
`
`Description
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`Publication Declaration of Alyssa G. Resnick for Wolf.1 and
`Wolf.2 (“Resnick Decl.”)
`
`Publication Declaration of Rachel J. Watters for Wolf.3 and Wolf.4
`(“Watters Decl.”)
`
`U.S. Patent No. 6,163,877 (“Gupta”)
`
`U.S. Patent No. 6,534,805 (“Jin”)
`
`Excerpts from the Prosecution History of U.S. Patent No.
`8,421,195 (the “’195 Patent”)
`
`Patent Owner’s Proposed Constructions
`
`Blank
`
`Blank
`
`Patent Owner’s Responsive Claim Construction Brief
`
`Blank
`
`Sze, Semiconductor Devices Physics and Technology, 2d Ed., John
`Wiley & Sons (2002)
`
`Maziasz and Hayes, Layout Minimization of CMOS Cells, Kluwer
`Academic Publishers (1992) (“Maziasz”)
`
`U.S. District Courts – Case Statistics, obtained at
`https://www.uscourts.gov/statistics-reports/analysis- reports/
`federal-court-management-statistics, dated June 30, 2023
`Rabaey et al., Digital Integrated Circuits, A Design Perspective,
`Prentice Hall Electronics and VLSI Series (2003) (“Rabaey”)
`
`Gregory and Shafer, “Latch-Up In CMOS Integrated Circuits,”
`IEEE Transactions on Nuclear Science, Volume 20, Issue 6 (1973)
`
`vi
`
`

`

`
`
`Exhibit
`No.
`
`Description
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`1036
`
`1037
`
`1038
`
`1039
`
`1040
`
`U.S. Patent Application Publication No. 2007/0045682 to Hong et
`al. (“Hong”)
`
`Excerpts from the Prosecution History of U.S. Patent Application
`Publication No. 10/934,915 (the “’915 App.”)
`
`Excerpts from the Prosecution History of U.S. Patent No.
`9,190,502 (the “’502 Patent”)
`
`Excerpts from the Prosecution History of U.S. Patent Application
`Publication No. 13/854,319 (the “’319 App.”)
`
`U.S. Patent No. 4,160,985 to Kamins et al. (“Kamins”)
`
`McGraw-Hill Dictionary of Scientific and Technical Terms (2003)
`
`U.S. Patent No. 9,647,070 to Rao (the “’070 Patent”)
`
`U.S. Patent Application Publication No. 2003/0030488 to Hueting
`et al. (“Hueting”)
`
`Blank
`
`Proposed Claim Constructions in the District Court Case
`
`Howe and Sodini, Microelectronics, An Integrated Approach,
`Prentice Hall Electronics and VLSI Series (1997) (“Howe”)
`
`Hodges et al., Analysis and Design of Digital Integrated Circuits
`In Deep Submicron Technology, 3rd Ed., McGraw-Hill (2004)
`(“Hodges”)
`
`Publication Declaration of Martin L. Knott for Hodges (“Knott-
`Hodges Decl.”)
`
`Jaeger, Microelectronic Circuit Design, McGraw-Hill (1997)
`(“Jaeger”)
`
`vii
`
`

`

`
`
`
`
`Exhibit
`No.
`
`Description
`
`1041
`
`1042
`
`1043
`
`1044
`
`1045
`
`1046
`
`1047
`
`Kang and Leblebici, CMOS Digital Integrated Circuits Analysis
`and Design, McGraw-Hill (2003) (“Kang”)
`
`Redacted District Court Case Transfer Order
`
`Publication Declaration of Sylvia Hall-Ellis for Wolf
`
`Dec. 21, 2022 Preliminary Claim Constructions in 6:22-CV-00105
`
`Oct. 31, 2022 Giapis Declaration, 6:22-CV-00105
`
`U.S. Patent No. 6,614,560 to Silverbrook (“Silverbrook”)
`
`Wong et al., “CMOS Active Pixel Image Sensors Fabricated Using
`a 1.8V, 0.25 um CMOS Technology.”
`
`viii
`
`

`

`
`
`Cirrus Logic, Inc., OmniVision Technologies, Inc., and ams Sensors USA,
`
`Inc. (collectively, “Petitioner”) requests inter partes review (“IPR”) of claims 1-9,
`
`12-28, and 31-42 (the “Challenged Claims”) of U.S. Patent No. 11,121,222
`
`(Ex.1001, “the ’222 Patent”).
`
`I.
`
`INTRODUCTION
`The ’222 Patent is directed to a VLSI semiconductor device having a graded
`
`dopant concentration in its active/well region(s) to aid carrier movement. Ex.1001,
`
`Claim 1. This Petition demonstrates that the Challenged Claims are unpatentable.
`
`II. MANDATORY NOTICES
`A. Real Party-In-Interest
`Cirrus Logic, Inc., OmniVision Technologies, Inc., ams Sensors USA, Inc.,
`
`OSRAM GmbH, ams-OSRAM AG, and GlobalFoundries U.S., Inc. are the real
`
`parties-in-interest.
`
`B. Related Matters
`The ’222 Patent is the subject of the following active proceedings:
`
`• Cirrus Logic, Inc., OmniVision Technologies, Inc., and ams Sensors
`
`USA, Inc., v. Greenthread, LLC, IPR2024-00021 (challenging claim 44),
`
`before the Patent Trial and Appeal Board, filed October 27, 2023;
`
`• Greenthread, LLC v. Cirrus Logic, Inc., Civil Action No. 1:23-cv-00369
`
`in the Western District of Texas, filed March 31, 2023 (“Cirrus District
`
`Court Case”);
`
`1
`
`

`

`
`
`• Greenthread, LLC v. OmniVision Technologies, Inc., Civil Action No.
`
`2:23-cv-00212 in the Eastern District of Texas, filed May 10, 2023
`
`(“OmniVision District Court Case”);
`
`• Greenthread, LLC v. OSRAM GmbH et al., Civil Action No. 2:23-cv-
`
`00179 in the Eastern District of Texas, filed April 19, 2023 (“ams-
`
`OSRAM District Court Case”);
`
`• Greenthread, LLC v Texas Instruments Incorporated, Civil Action No.
`
`2:23-cv-00157 in the Eastern District of Texas, filed April 6, 2023;
`
`• Greenthread, LLC v. On Semiconductor Corporation et al., 1:23-cv-
`
`00443 in the District of Deleware, filed April 21, 2023;
`
`• Greenthread, LLC v. Monolithic Power Systems, Inc., Civil Action No.
`
`1:23-cv-00579 in the District of Delaware, filed May 26, 2023;
`
`• Semiconductor Components Industries, LLC v. Greenthread, LLC,
`
`IPR2023-01242, before the Patent Trial and Appeal Board, filed July 27,
`
`2023; and
`
`• Semiconductor Components Industries, LLC v. Greenthread, LLC,
`
`IPR2023-01244, before the Patent Trial and Appeal Board, filed July 27,
`
`2023;
`
`The ’222 Patent was previously subject to the following proceedings, which
`
`are no longer pending:
`
`2
`
`

`

`
`
`
`
`• Greenthread, LLC v. Intel Corporation, Dell Inc., and Dell Technologies
`
`Inc., Civil Action No. 6:22-cv-105 in the Western District of Texas
`
`(“Intel Litigation”), filed January 27, 2022;
`
`• Greenthread, LLC v. Intel Corporation, Civil Action No. 6:22-cv-01293
`
`in the Western District of Texas, severed December 21, 2022, and
`
`transferred to District of Oregon as 3:22-cv-02001;
`
`• Greenthread, LLC v. Micron Technology, Inc. et al., Civil Action No.
`
`1:23-cv-00333 in the District of Delaware, filed March 24, 2023;
`
`• Greenthread, LLC v. Western Digital Corporation et al, Civil Action No.
`
`1:23-cv-00326 in the District of Delaware, filed March 24, 2023;
`
`• Intel Corporation v. Greenthread, LLC, IPR2023-00420, before the
`
`Patent Trial and Appeal Board, filed December 28, 2022;
`
`• Intel Corporation v. Greenthread, LLC, IPR2023-00552, before the
`
`Patent Trial and Appeal Board, filed February 1, 2023;
`
`• Dell Technologies Inc. et al v. Greenthread, LLC, IPR2023-00509,
`
`before the Patent Trial and Appeal Board, filed January 27, 2023; and
`
`• Sony Group Corporation v. Greenthread, LLC, IPR2023-00324, before
`
`the Patent Trial and Appeal Board, filed December 12, 2022.
`
`C. Counsel Service Information
`
`3
`
`

`

`
`
`Lead Counsel
`Scott Weidenfeller (No. 54,531)
`sweidenfeller@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5923
`Facsimile: (202) 778-5923
`
`Backup Counsel
`Anupam Sharma (No. 55,609)
`asharma@cov.com
`Covington & Burling LLP
`3000 El Camino Real,
`5 Palo Alto Square,
`Palo Alto, CA 94306
`Telephone: (650) 632-4720
`Facsimile: (650) 632-4800
`
`Raj Paul (No. 64,492)
`rpaul@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5740
`Facsimile: (202) 778-5740
`
`Bert Greene (No. 48,366)
`bgreene@duanemorris.com
`Andrew Liddell (No. 65,693)
`waliddell@duanemorris.com
`DUANE MORRIS LLP
`Las Cimas IV
`900 S. Capital of Texas Hwy., Suite
`300, Austin, TX 78746
`Telephone: (512) 277-2246
`Facsimile: (512)277-2301
`
`Daniel G. Nguyen (No. 42,933)
`dnguyen@lockelord.com
`Emma A. Bennett (No. 80,631)
`emma.bennett@lockelord.com
`LOCKE LORD LLP
`600 Travis St., Suite 2800
`Houston, Texas 77002
`Telephone: (713) 226-1200
`Facsimile: (214) 223-3717
`
`4
`
`

`

`
`
`
`
`
`
`David H. Bluestone (No. 44,542)
`david.bluestone@bfkn.com
`Barack Ferrazzano Kirschbaum &
`Nagelberg LLP
`200 West Madison St., Suite 3900
`Chicago, Illinois 60606
`Telephone: (312) 984-3106
`Facsimile: (312) 984-3150
`
`
`37 C.F.R. §42.8(b)(4): Service Information
`D.
`Service information is provided in the designation of counsel above. Petitioner
`
`consents to electronic service by email to GT-Cirrus-IPR@cov.com, osram-
`
`greenthread@lockelord.com,
`
`david.bluestone@bfkn.com,
`
`and
`
`BGreene@duanemorris.com.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. §42.103
`The Office is authorized to charge the fee set forth in 37 C.F.R. §42.15(a)(1)
`
`for this Petition to Deposit Account No. 60-3160. Review of 38 claims is requested.
`
`The undersigned further authorizes payment for any additional fees that may be due
`
`in connection with this Petition.
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies under Rule 42.104(a) that the ’222 Patent is available for
`
`IPR and Petitioner is not barred or estopped from requesting IPR of the Challenged
`
`Claims on the grounds identified in this Petition.
`
`5
`
`

`

`
`
`V. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Prior Art Printed Publications
`A.
`The ’222 Patent claims priority to September 3, 2004. Petitioner’s challenge
`
`is based on the following prior-art references, none of which were discussed by the
`
`Patent Office during prosecution of the ’222 Patent:
`
`• U.S. Patent No. 6,043,114 to Kawagoe et al. (“Kawagoe”) (Ex.1007) issued
`
`March 28, 2000 and is prior art under §102(b).1
`
`• U.S. Patent Application Publication 2003/0183856 to Wieczorek et al.
`
`(“Wieczorek”) (Ex.1006) was filed October 29, 2002 and published October 2,
`
`2003. Wieczorek is prior art under §§102(a), (e).
`
`• Wolf and Tauber, Silicon Processing for the VLSI Era, Lattice Press (2000)
`
`(“Wolf”) (Exs.1008A-D), was published and publicly available no later than
`
`2002, and is prior art under §102(b). See Exs.1012-1013.
`
`• U.S. Patent No. 6,163,877 to Gupta (Ex.1014) issued December 19, 2000 and is
`
`prior art under §102(b).
`
`• U.S. Patent No. 6,614,560 to Silverbrook (Ex.1046) issued September 2, 2003
`
`and is prior art under §102(b).
`
`
`1 Cites to §§102/103 are to the pre-America Invents Act (pre-AIA).
`
`6
`
`

`

`
`
`B. Relief Requested
`Petitioner requests cancellation of the Challenged Claims as unpatentable
`
`under 35 U.S.C. §103. The specific grounds of the challenge are set forth below and
`
`are supported by the declaration of Dr. Banerjee (Ex.1003).
`
`Ground Basis
`
`Challenged Claims
`
`Reference(s)
`
`I
`
`II
`
`III
`
`IV
`
`V
`
`VI
`
`§103
`
`1-9, 12-14, 16-21, 23-28, and 31-42 Kawagoe
`
`§103
`
`1-2, 4-9, 12-23, 25-28, and 31-42 Wieczorek, Wolf
`
`§103
`
`1-9, 12-14, 16-21, 23-28, and 31-42 Kawagoe, Gupta
`
`§103
`
`§103
`
`§103
`
`1-2, 4-9, 12-23, 25-28, and 31-42 Wieczorek, Wolf,
`Gupta
`
`19 and 37
`
`19 and 37
`
`Kawagoe,
`Silverbrook
`
`Wieczorek, Wolf,
`Silverbrook
`
`
`VI. PERSON OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (“POSITA”) of the subject matter of the
`
`’222 Patent would have had a Bachelor’s degree in electrical engineering, material
`
`science, applied physics, or a related field, and four years of experience in
`
`semiconductor design and manufacturing or equivalent work experience. Ex.1003,
`
`¶¶48-49. Additional education might compensate for a deficiency in experience, and
`
`7
`
`

`

`
`
`vice-versa. Id. In the Intel Litigation, Patent Owner (“PO”) agreed with this POSITA
`
`characterization. Ex.1045, ¶13.
`
`VII. CLAIM CONSTRUCTION
`Claims in an IPR are construed under Phillips v. AWH Corp., 415 F.3d 1303
`
`(Fed. Cir. 2005) (en banc). 37 C.F.R. §42.100(b). Petitioner is aware that PO took
`
`positions on the meaning of certain claim terms, listed below. See Exs. 1017, 1020.25
`
`Claim Term
`“substrate”
`
`“active region”
`
`Patent Owner’s Proposed Construction
`Plain and ordinary meaning
`(“an underlying layer”)
`
`Plain and ordinary meaning (“a doped
`silicon region at the surface of a
`semiconductor device
`where a transistor can be formed”)
`
`“to aid carrier movement from …
`[to/towards] …”
`
`Plain and ordinary meaning
`
`“well region”
`
`“active region … within which
`transistors can be formed
`
`Plain and ordinary meaning (“a doped
`region that surrounds the active region of a
`semiconductor device”)
`
`Plain and ordinary meaning (“a doped
`silicon region at the surface of a
`semiconductor device where a transistor
`can be formed”)
`
`
`
`2
`
`
`For the “active region” and “well region” terms, PO’s position is reflected in
`
`its claim construction briefing. See Ex. 1020, 28, 39-40.
`
`8
`
`

`

`
`
`Petitioner is further aware that, in the Intel Litigation, the Court provided its
`
`“preliminary constructions” in advance of the claim construction hearing, in which
`
`the Court offered a “preliminary construction” of plain and ordinary meaning as to
`
`each of the above-listed terms. See Ex.1044. Petitioner does not believe any terms
`
`need be construed to resolve this Petition, and Petitioner takes no position regarding
`
`claim construction at this time. The Challenged Claims are unpatentable under either
`
`their plain and ordinary meaning, or under PO’s proposed constructions (except for
`
`the term “active region ... within which transistors can be formed,” addressed further
`
`below). Ex.1003 ¶54. Petitioner reserves the right to respond to any purported claim
`
`constructions that PO raises.
`
`
`VIII. SPECIFIC GROUNDS FOR PETITION
`A. Ground I:
`Kawagoe renders claims 1-9, 12-14, 16-21, 23-28, and 31-42 obvious.
`
`Ex.1003, ¶¶66-135.
`
`1.
`
`Claims 1/21/39/41/42
`Preambles:3
`a.
`
`
`3 Bracketed language shows the difference between the claims addressed together
`
`in the same section. Appendix A lists the elements and corresponding language for
`
`all Challenged Claims.
`
`9
`
`

`

`
`
`To the extent the preamble is limiting, Kawagoe is directed to a
`
`“semiconductor integrated circuit device.” Ex.1007, Title, 1:13-23, 14:46-67, FIGS.
`
`16-17/23; Ex.1003, ¶67. Ground I focuses on the CMOS device of Figure 23
`
`(Embodiment 4), fabricated on a uniformly-doped epitaxial substrate taught in
`
`Embodiment 1.4 See §VIII.A.1.b.
`
`Ex.1007, FIG. 23.5
`
`
`
`
`4 Figures 16-17 and 23 are directed to Kawagoe’s Embodiment 4. Ex.1007, 14:46-
`
`60. Figure 23 shows the same twin-well CMOS structures of Figure 16 without the
`
`metal layers (not recited in the Challenged Claims). Ex.1007, 17:10-18:38;
`
`Ex.1003, ¶67.
`
`5 All colors and colored annotations to figures added.
`
`10
`
`

`

`
`
`Kawagoe’s teachings apply to “VLSI” DRAM, flash memory, and
`
`microcomputer devices. Id., 1:24-30; §§VIII.A.1.h, VIII.A.12/13/15. Notably,
`
`Kawagoe’s teachings apply to multi-Megabit DRAM devices with at least one
`
`transistor per memory cell, totaling millions of transistors. Ex.1007, 19:15-18, 20:1-
`
`15; Ex.1003, ¶68; Ex.1016, 73 (VLSI refers to “at least one million active
`
`elements”). Wolf, which applies to “the VLSI Era,” also confirms that such devices
`
`at the time were understood to have at least one million active elements. Ex.1008A,
`
`cover, xxxiii, FIG. 1 (microprocessor with at least one million transistors);
`
`Ex.1008B, 596-597 (1-Megabit CMOS DRAM with one transistor per memory cell),
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`633-635 (1-Megabit CMOS flash EEPROM with one floating gate per memory cell
`
`and other transistors, totaling at least one million active elements); Ex.1003 ¶68.
`
`Elements[1.1]/[21.1]/[39.1]/[41.1]/[42.1]:
`b.
`Kawagoe discloses “semiconductor substrate 2” of a first doping type (p-type)
`
`having a silicon “epitaxial layer 2E [] doped with a p-type impurity such as boron”
`
`formed over non-epitaxial “semiconductor substrate body 2S [also] doped with a p-
`
`type impurity such as boron....” 6 Ex.1007, 14:61-15:12, 6:50-7:3. The substrate
`
`(orange) has a surface, as indicated below. Ex.1003, ¶69.
`
`
`6 All emphases added unless otherwise noted.
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`11
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`

`
`
`Ex.1007, FIG. 23.
`
`Kawagoe satisfies elements [1.1]/[21.1]/[39.1]/[41.1]/[42.1] under PO’s plain
`
`meaning construction. §VII; Ex.1007, 6:51-56, 14:61-67, 17:10-18:38; Ex.1003,
`
`
`
`¶70.
`
`
`Ex.1007, FIG. 20. Ground I relies on a uniformly-doped epitaxial substrate in which
`
`silicon epitaxial layer 2E of the substrate is doped at the same level as silicon
`
`substrate body 2S, so that the entire substrate in Figure 20 is “at a first doping level.”
`
`Ex.1007, 6:60-7:3; Ex.1003, ¶71.
`
`12
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`

`
`
`“at a first doping level” - Kawagoe teaches an epitaxial substrate (2S+2E),
`
`illustrated in Figure 20, in which the non-epitaxial silicon substrate body (2S) is
`
`either doped at the same or higher level compared to the epitaxial silicon layer (2E).
`
`For example, Embodiment 1 describes a uniformly-doped epitaxial substrate in
`
`which the “epitaxial layer 2E is doped ... in a concentration equal to the
`
`[concentration] of the semiconductor substrate body 2S, e.g., 1.3x1015 atoms/cm3.”
`
`Ex.1007, 6:60-7:3; id., Abstract (describing “an epitaxial layer which contains an
`
`impurity of the same conduction type [and at] .. the same concentration” as the bulk
`
`substrate), 2:57-3:9 (same). This uniformly-doped epitaxial substrate is Kawagoe’s
`
`benchmark substrate discussed in other embodiments, including Embodiment 4.
`
`Ex.1007, 12:64-65, 13:12-15, 13:66-67, 14:18-20, 15:725. Embodiment 4 introduces
`
`the option of a latchup-resistant substrate in which “the impurity concentration of
`
`the semiconductor substrate body 2S is made higher than that of the epitaxial layer
`
`2E ... to improve the resistance to the latchup.” Ex.1007, 15:13-17; see also id., 3:60-
`
`63 (there is a high “degree of freedom for setting the impurity concentration” in the
`
`disclosed semiconductor substrate so “as to facilitate the control of the formation”).
`
`Kawagoe teaches that the “substrate body 2S is doped with a p-type impurity such
`
`as boron at a concentration of about 1.5 x 1015 atoms/cm3.” Id., 14:64-67; Ex.1003,
`
`¶¶72-73.
`
`13
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`

`
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`“[A] POSITA would have understood that Kawagoe teaches forming Figure
`
`23’s twin-well CMOS device (Embodiment 4) on either Embodiment 1’s uniformly-
`
`doped epitaxial substrate or Embodiment 4’s optional latchup-resistant substrate.”
`
`Ex.1003, ¶74. Specifically, a POSITA would have appreciated that Kawagoe teaches
`
`a tradeoff between improving latchup resistance and minimizing manufacturing cost.
`
`This understanding is consistent with the teachings of Wolf. See Ex.1008C, 524
`
`(“There are many trade-offs involved in the optimization of a CMOS process”
`
`including “fabrication cost[] and susceptibility to latchup.”); Ex.1003, ¶75. Kawagoe
`
`emphasizes the benefits of Embodiment 1’s uniformly-doped epitaxial substrate and
`
`explains that the substrate used in Embodiment 4 is formed “as in the foregoing
`
`embodiment 1 so that... the cost of the semiconductor substrate 2 is lowered to about
`
`one half.” Ex.1007, 15:7-25.
`
`Accordingly, a POSITA would have been motivated to use a uniformly-doped
`
`epitaxial substrate to form Figure 23’s twin-well CMOS device because this
`
`substrate provides “excellent film quality” that “drastically reduce[s] the defect
`
`densities of the gate insulating films” and “improve[s] the [device’s] performance,
`
`reliability and production yield.” Ex.1003, ¶75; Ex.1007, 12:8-40; id., 15:7-25. This
`
`substrate is also easier to manufacture, helping “lower the cost” of the substrate and
`
`chip. Ex.1007, 12:8-40. As a POSITA would have appreciated, Kawagoe teaches
`
`that a semiconductor substrate having an “impurity high in concentration[] is
`
`14
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`

`
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`[undesirably] expensive.” Id., 2:15-18. To avoid this, Kawagoe repeatedly teaches
`
`that using a less heavily-doped substrate body (as in Embodiment 1) can result in
`
`lower cost, relative to a more heavily-doped substrate body. See id., 3:38-45; 7:13-
`
`18; 12:19-24. While Embodiment 4 is disclosed as having an improved latchup
`
`resistance, this requires that the substrate body is doped at a higher concentration
`
`(1.5 x 1015 atoms/cm3) compared to the substrate body of Embodiment 1 (1.3 x 1015
`
`atoms/cm3). See id., 6:62-64, 14:64-67.
`
`Thus, a POSITA, opting to maximize cost savings over latch-up resistance,
`
`would have been motivated to instead use the uniformly-doped epitaxial substrate
`
`(i.e., doped at both 1.3 x 1015 atoms/cm3 for the substrate body and epitaxial layer,
`
`as disclosed for Embodiment 1) as the starting material in lieu of Embodiment 4’s
`
`latchup-resistant substrate to form the twin-well CMOS device of Figure 23. The use
`
`of uniformly-doped epitaxial substrate as the starting material in lieu of Embodiment
`
`4’s latchup-resistant substrate to form Figure 23’s twin-well CMOS devices is a
`
`simple substitution of one known element with another known, closely-related
`
`element, both of which are described in Kawagoe. Additionally, this substitution
`
`would have been obvious to try because it merely involves choosing one of two ways
`
`of doping an epitaxial substrate, both described in Kawagoe, and both options have
`
`15
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`

`

`
`
`predictable effects on the devices formed using those substrates.7 Ex.1003, ¶76.
`
`Twin-well CMOS devices (illustrated in Figure 23) fabricated on a uniformly-doped
`
`epitaxial substrate would have worked for their intended purpose. Id., ¶77. As
`
`discussed in Wolf, twin-well CMOS devices were commonly formed over a
`
`“uniform, lightly doped p- or n-type substrate” that provides no improved latchup
`
`resistance. Ex.1008C, 523; id., 530 (“With the twin-tub [(twin-well)] approach, two
`
`separate wells are formed for n- and p-channel transistors on a lightly doped
`
`substrate ...”); Ex.1008B, 387-389; Ex.1007, 2:57-65 (discussing a uniform, “lightly
`
`doped” epitaxial substrate).
`
`There would have been a reasonable expectation of success because Kawagoe
`
`details the use of both uniformly-doped epitaxial substrates and latchup-resistant
`
`substrates in forming CMOS devices, and repeatedly emphasizes their similarity.
`
`Ex.1007, 8:40-52; 12:8-40, 14:58-60, 15:7-12 (substrate), 15:18-25 (epitaxial layer),
`
`15:26-40 (transistors); Ex.1003, ¶78. A uniformly-doped epitaxial substrate is also
`
`better than the bulk (non-epitaxial) substrate commonly used to fabricate twin-well
`
`CMOS devices. Ex.1007, 1:33-40 (“The epitaxial wafer is advantageous [compared
`
`
`7 Bos. Sci. Scimed, Inc. v. Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009)
`
`(“Combining two embodiments disclosed adjacent to each other in a prior art
`
`patent does not require a leap of inventiveness.”).
`
`16
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`

`

`
`
`to bulk wafer/substrate] in that ... the gate insulating film to be formed over the
`
`epitaxial layer can have excellent breakdown characteristics to drastically reduce the
`
`defect density of the gate insulating film.”); id., 12:8-40; Ex.1008B, 387-88
`
`(discussing twin-well CMOS devices fabricated over bulk substrate); Ex.1003, ¶78.
`
`Kawagoe characterizes
`
`the
`
`improved
`
`latchup
`
`tolerance provided by
`
`Embodiment 4’s optional latchup-tolerant substrate as just another “effect[] [that]
`
`can be achieved in addition to those of the foregoing embodiment 1,” Ex.1007,
`
`19:49-63, as opposed to being vital to its operation. Consistent with Kawagoe’s
`
`teachings, a POSITA would have understood that a uniformly-doped epitaxial
`
`substrate is a suitable substrate because, among other benefits, it “drastically
`
`reduce[s] the defect densities of the gate insulating films” of CMOS transistors.
`
`Ex.1007, 12:8-40 Ex.1003, ¶79. Moreover, a POSITA would have understood that
`
`susceptibility to latchup (a “short-circuit” failure condition in poorly designed
`
`circuits) may not be a concern for all CMOS chips—see Ex.1008B, 406 (“four
`
`conditions must exist in a CMOS circuit in order for latchup to occur.”); Ex.1026, 1
`
`(“several conditions must be met” to cause latchup)—in which case it is unnecessary
`
`to improve latchup resistance. Ex.1003, ¶79. Indeed, both single-well and twin-well
`
`CMOS devices were commonly fabricated on uniformly-doped bulk substrates that
`
`provide no improved latchup resistance. See, e.g., Ex.1008B, 387-388 (“With the
`
`[twin-well] approach, ... [t]he substrate may be [] a lightly doped wafer ...”), 652
`
`17
`
`

`

`
`
`(example 6.7). Even if latchup were to remain a concern, a POSITA would have
`
`understood that improved latchup resistance can be achieved by other means
`
`unrelated to the choice of substrate, such as careful circuit layout. Ex.1003, ¶80;
`
`Ex.1008B, 381 (“Latchup tolerance can [] be improved by spacing n- and p-channel
`
`transistors farther apart”), 419 (“Increasing the number of well contacts to VDD
`
`reduces latchup susceptibility” and thus “can serve as an alternative approach to
`
`improving latchup immunity.”).
`
`Elements[1.2]/[21.2]/[39.2]/[41.2]/[42.2]:
`c.
`Kawagoe discloses “semiconductor regions 4Na and 4Nb ... for forming the
`
`source-drain regions of the nMOS [n-channel transistor] 4N.” Ex.1007, 8:66-67;
`
`id., 3:35-38, 8