`
`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`CIRRUS LOGIC, INC.;
`OMNIVISION TECHNOLOGIES, INC.; AND
`AMS SENSORS USA INC.,
`Petitioner,
`
`
`v.
`
`
`GREENTHREAD, LLC,
`Patent Owner.
`
`
`Case No. IPR2024-00019
`Patent No. 11,316,014
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO.
`11,316,014
`UNDER 35 U.S.C. §§ 312 AND 37 C.F.R. § 42.104
`
`
`
`
`
`

`

`
`
`TABLE OF CONTENTS
`
`
`INTRODUCTION ........................................................................................ 1
`I.
`II. MANDATORY NOTICES .......................................................................... 1
`A.
`Real Party-In-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Counsel Service Information ................................................................ 3
`D.
`37 C.F.R. §42.8(b)(4): Service Information ......................................... 4
`III. PAYMENT OF FEES UNDER 37 C.F.R. §42.103 .................................... 5
`IV. CERTIFICATION OF GROUNDS FOR STANDING ............................ 5
`V. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED ............. 5
`A.
`Prior Art Printed Publications .............................................................. 5
`B.
`Relief Requested ................................................................................... 6
`VI. THE ’014 PATENT ...................................................................................... 7
`VII. PERSON OF ORDINARY SKILL IN THE ART ..................................... 7
`VIII. CLAIM CONSTRUCTION ......................................................................... 7
`IX. SPECIFIC GROUNDS FOR PETITION .................................................. 9
`A. Ground I: .............................................................................................. 9
`1.
`Claims 1/21 ................................................................................ 9
`2.
`Claims 2/23: “The system of claim [1/21], wherein the
`substrate of the at least one semiconductor device is a p-
`type substrate.” ......................................................................... 35
`Claims 3/24: “The system of claim [1/21], wherein the
`substrate of the at least one semiconductor device has
`epitaxial silicon on top of a nonepitaxial substrate.” ............... 35
`
`3.
`
`i
`
`

`

`
`
`4.
`
`6.
`
`7.
`
`8.
`
`5.
`
`Claims 4/25: “The system of claim [1/21], wherein the
`first active region and second active region of the at least
`one semiconductor device contain [digital logic formed
`by/at least] one of either p-channel and n-channel
`devices.” ................................................................................... 35
`Claims 5/26: “The system of claim [1/21], wherein the
`first active region and second active region of the at least
`one semiconductor device contain either p-channel or n-
`channel devices in n-wells or p-wells, respectively, and
`each well has at least one graded dopant.” .............................. 36
`Claims 6/27: “The system of claim [1/21], wherein the
`first active region and second active region of the at least
`one semiconductor device are each separated by at least
`one isolation region.” ............................................................... 37
`Claim 7: “The system of claim 1, wherein the graded
`dopant is fabricated with an ion implantation process.” .......... 38
`Claim 8: “The system of claim 1, wherein the first and
`second active regions of the at least one semiconductor
`device are formed adjacent the first surface of the
`substrate of the at least one semiconductor device.” ............... 38
`Claims 9/28: “The system of claim [1/21], wherein
`dopants of the graded dopant concentration in the first
`active region or the second active region of the at least
`one semiconductor device are either p-type or n-type.” .......... 39
`10. Claim 12: “The system of claim 1, wherein dopants of
`the graded dopant region in the well region are both p-
`type and n-type.” ...................................................................... 40
`11. Claim 13: “The system of claim 1, wherein the transistors
`which can be formed in the first and second active
`regions of the at least one semiconductor device are
`CMOS digital logic transistors requiring at least a source,
`a drain, a gate and a channel.” ................................................. 41
`
`9.
`
`ii
`
`

`

`
`
`B.
`
`12. Claim 14: “The system of claim 1, wherein the at least
`one semiconductor device is a dynamic random access
`memory (DRAM).” .................................................................. 42
`13. Claim 16: “The system of claim 1, wherein the at least
`one semiconductor device is a flash memory.” ....................... 42
`14. Claim 17: “The system of claim 1, wherein the at least
`one semiconductor device comprises digital logic and
`capacitors.” ............................................................................... 43
`15. Claim 18: “The system of claim 1, wherein the at least
`one semiconductor device is a central processing unit.” ......... 44
`16. Claim 19: “The system of claim 1, wherein the device is
`an image sensor.” ..................................................................... 44
`17. Claim 20: “The system of claim 1, wherein each of the
`first and second active regions of the at least one
`semiconductor device are in the lateral or vertical
`direction.” ................................................................................. 45
`Ground II: ........................................................................................... 46
`1.
`Claims 1/21 .............................................................................. 47
`2.
`Claims 2/23: ............................................................................. 64
`3.
`Claims 4/25: ............................................................................. 64
`4.
`Claims 5/26: ............................................................................. 65
`5.
`Claims 6/27: ............................................................................. 66
`6.
`Claim 7: .................................................................................... 66
`7.
`Claim 8: .................................................................................... 67
`8.
`Claims 9/28: ............................................................................. 67
`9.
`Claim 12: .................................................................................. 68
`10. Claim 13: .................................................................................. 68
`
`iii
`
`

`

`
`
`11. Claim 14: .................................................................................. 69
`12. Claim 15: .................................................................................. 71
`13. Claim 16: .................................................................................. 71
`14. Claim 17: .................................................................................. 72
`15. Claim 18: .................................................................................. 72
`16. Claim 19: .................................................................................. 74
`17. Claim 20: .................................................................................. 75
`18. Claim 22: “The system of claim 21, wherein the substrate
`of the at least one semiconductor device is an n-type
`substrate.” ................................................................................. 76
`GROUNDS III/IV .............................................................................. 77
`C.
`D. GROUNDS V/VI ............................................................................... 83
`THE BOARD SHOULD INSTITUTE IPR .............................................. 84
`A.
`35 U.S.C. § 314(a) .............................................................................. 84
`B.
`35 U.S.C. § 325(d).............................................................................. 87
`C.
`Prior Terminated Petitions Do Not Warrant Denying Institution ...... 90
`CERTIFICATION OF WORD COUNT .............................................................. 1
`
`
`
`X.
`
`
`
`iv
`
`

`

`
`
`
`
`Exhibit No.
`1001
`1002
`1003
`1004
`1005
`
`1006
`
`1007
`1008A
`
`1008B
`
`1008C
`
`1008D
`
`1009
`
`1010
`1011
`
`1012
`
`1013
`
`1014
`1015
`1016
`
`1017
`1018
`1019
`1020
`1021
`
`TABLE OF EXHIBITS
`
`Description
`U.S. Patent No. 11,316,014 to Rao (the “’014 Patent”)
`Prosecution History of the ’014 Patent
`Declaration of Sanjay Banerjee, PhD
`Curriculum Vitae of Sanjay Banerjee, PhD
`Publication Declaration of Sean O’Bryan for Maziasz (“O’Bryan
`Decl.”)
`U.S. Patent Application Publication No. 2003/0183856 to
`Wieczorek (“Wieczorek”)
`U.S. Patent No. 6,043,114 to Kawagoe, et al. (“Kawagoe”)
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol 1,
`Lattice Press (2000) (“Wolf.1”)
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 2,
`Lattice Press (2000) (“Wolf.2”)
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 3,
`Lattice Press (2000) (“Wolf.3”)
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 4,
`Lattice Press (2000) (“Wolf.4”)
`Wang and Agrawal, Single Event Upset: An Embedded Tutorial,
`21st Intl Conf on VLSI Design, IEEE 2008 (“Wang”)
`U.S. Patent No. 4,481,522 (“Jastrzebski”)
`Publication Declaration of Martin L. Knott for Rabaey (“Knott-
`Rabaey Decl.”)
`Publication Declaration of Alyssa G. Resnick for Wolf.1 and
`Wolf.2 (“Resnick Decl.”)
`Publication Declaration of Rachel J. Watters for Wolf.3 and
`Wolf.4 (“Watters Decl.”)
`U.S. Patent No. 6,163,877 (“Gupta”)
`U.S. Patent No. 6,534,805 (“Jin”)
`Excerpts from the Prosecution History of U.S. Patent No.
`8,421,195 (the “’195 Patent”)
`Patent Owner’s Proposed Constructions
`Blank
`Blank
`Patent Owner’s Responsive Claim Construction Brief
`Blank
`
`v
`
`

`

`
`
`Exhibit No.
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`1032
`1033
`1034
`
`1035
`1036
`1037
`
`1038
`
`1039
`
`1040
`
`1041
`1042
`
`Description
`Sze, Semiconductor Devices Physics and Technology, 2d Ed., John
`Wiley & Sons (2002)
`Maziasz and Hayes, Layout Minimization of CMOS Cells, Kluwer
`Academic Publishers (1992) (“Maziasz”)
`U.S. District Courts – Case Statistics, obtained at
`https://www.uscourts.gov/statistics-reports/analysis- reports/
`federal-court-management-statistics, dated June 30, 2023
`Rabaey et al., Digital Integrated Circuits, A Design Perspective,
`Prentice Hall Electronics and VLSI Series (2003) (“Rabaey”)
`Gregory and Shafer, “Latch-Up In CMOS Integrated Circuits,”
`IEEE Transactions on Nuclear Science, Volume 20, Issue 6 (1973)
`U.S. Patent Application Publication No. 2007/0045682 to Hong et
`al. (“Hong”)
`Excerpts from the Prosecution History of U.S. Patent Application
`Publication No. 10/934,915 (the “’915 App.”)
`Excerpts from the Prosecution History of U.S. Patent No.
`9,190,502 (the “’502 Patent”)
`Excerpts from the Prosecution History of U.S. Patent Application
`Publication No. 13/854,319 (the “’319 App.”)
`U.S. Patent No. 4,160,985 to Kamins et al. (“Kamins”)
`McGraw-Hill Dictionary of Scientific and Technical Terms (2003)
`U.S. Patent No. 9,647,070 to Rao (the “’070 Patent”)
`U.S. Patent Application Publication No. 2003/0030488 to Hueting
`et al. (“Hueting”)
`Blank
`Proposed Claim Constructions in the District Court Case
`Howe and Sodini, Microelectronics, An Integrated Approach,
`Prentice Hall Electronics and VLSI Series (1997) (“Howe”)
`Hodges et al., Analysis and Design of Digital Integrated Circuits
`In Deep Submicron Technology, 3rd Ed., McGraw-Hill (2004)
`(“Hodges”)
`Publication Declaration of Martin L. Knott for Hodges (“Knott-
`Hodges Decl.”)
`Jaeger, Microelectronic Circuit Design, McGraw-Hill (1997)
`(“Jaeger”)
`Kang and Leblebici, CMOS Digital Integrated Circuits Analysis
`and Design, McGraw-Hill (2003) (“Kang”)
`Redacted District Court Case Transfer Order
`
`vi
`
`

`

`
`
`
`
`Exhibit No.
`1043
`1044
`1045
`1046
`1047
`
`Description
`Publication Declaration of Sylvia Hall-Ellis for Wolf
`Dec. 21, 2022 Preliminary Claim Constructions in 6:22-CV-00105
`Oct. 31, 2022 Giapis Declaration, 6:22-CV-00105
`U.S. Patent No. 6,614,560 to Silverbrook (“Silverbrook”)
`Wong et al., “CMOS Active Pixel Image Sensors Fabricated Using
`a 1.8V, 0.25 um CMOS Technology.”
`
`vii
`
`

`

`
`
`Cirrus Logic, Inc., OmniVision Technologies, Inc., and ams Sensors USA,
`
`Inc. (collectively, “Petitioner”) requests inter partes review (“IPR”) of claims 1-9
`
`and 12-28 (the “Challenged Claims”) of U.S. Patent No. 11,316,014 (Ex.1001, “the
`
`’014 Patent”).
`
`I.
`
`INTRODUCTION
`The ’014 Patent is directed to an electronic system comprising a
`
`semiconductor device having graded dopant concentrations in its active and well
`
`regions to aid carrier movement. Ex.1001, 4:49-5:7 (Claim 1), 6:4-33 (Claim 21).
`
`This Petition demonstrates that the Challenged Claims are unpatentable.
`
`II. MANDATORY NOTICES
`A. Real Party-In-Interest
`Cirrus Logic, Inc., OmniVision Technologies, Inc., ams Sensors USA, Inc.,
`
`OSRAM GmbH, ams-OSRAM AG, and GlobalFoundries U.S., Inc. are the real
`
`parties-in-interest.
`
`B. Related Matters
`The ’014 Patent is the subject of the following active proceedings:
`
`• Greenthread, LLC v. Cirrus Logic, Inc., Civil Action No. 1:23-cv-00369
`
`in the Western District of Texas, filed March 31, 2023 (“Cirrus District
`
`Court Case”);
`
`
`
`

`

`
`
`• Greenthread, LLC v. OmniVision Technologies, Inc., Civil Action No.
`
`2:23-cv-00212 in the Eastern District of Texas, filed May 10, 2023
`
`(“OmniVision District Court Case”);
`
`• Greenthread, LLC v. OSRAM GmbH et al., Civil Action No. 2:23-cv-
`
`00179 in the Eastern District of Texas, filed April 19, 2023 (“ams-
`
`OSRAM District Court Case”);
`
`• Greenthread, LLC v Texas Instruments Incorporated, Civil Action No.
`
`2:23-cv-00157 in the Eastern District of Texas, filed April 6, 2023;
`
`• Greenthread, LLC v. Monolithic Power Systems, Inc., Civil Action No.
`
`1:23-cv-00579 in the District of Delaware, filed May 26, 2023;
`
`The ’014 Patent was previously subject to the following proceedings, which
`
`are no longer pending:
`
`• Greenthread, LLC v. Intel Corporation, Dell Inc., and Dell Technologies
`
`Inc., Civil Action No. 6:22-cv-105 in the Western District of Texas
`
`(“Intel Litigation”), filed January 27, 2022;
`
`• Greenthread, LLC v. Intel Corporation, Civil Action No. 6:22-cv-01293
`
`in the Western District of Texas, severed December 21, 2022, and
`
`transferred to District of Oregon as 3:22-cv-02001;
`
`• Greenthread, LLC v. Micron Technology, Inc. et al., Civil Action No.
`
`1:23-cv-00333 in the District of Delaware, filed March 24, 2023;
`
`2
`
`

`

`
`
`• Greenthread, LLC v. Western Digital Corporation et al, Civil Action No.
`
`1:23-cv-00326 in the District of Delaware, filed March 24, 2023;
`
`• Intel Corporation v. Greenthread, LLC, IPR2023-00386, before the
`
`Patent Trial and Appeal Board, filed December 19, 2022;
`
`• Dell Technologies Inc. et al v. Greenthread, LLC, IPR2023-00510,
`
`before the Patent Trial and Appeal Board, filed January 27, 2023; and
`
`• Sony Group Corporation v. Greenthread, LLC, IPR2023-00325, before
`
`the Patent Trial and Appeal Board, filed December 12, 2022.
`
`C. Counsel Service Information
`Lead Counsel
`Scott Weidenfeller (No. 54,531)
`sweidenfeller@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5923
`Facsimile: (202) 778-5923
`
`Backup Counsel
`Anupam Sharma (No. 55,609)
`asharma@cov.com
`Covington & Burling LLP
`3000 El Camino Real,
`5 Palo Alto Square,
`Palo Alto, CA 94306
`Telephone: (650) 632-4720
`Facsimile: (650) 632-4800
`
`Raj Paul (No. 64,492)
`rpaul@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5740
`Facsimile: (202) 778-5740
`
`Bert Greene (No. 48,366)
`bgreene@duanemorris.com
`
`3
`
`

`

`
`
`
`
`
`Andrew Liddell (No. 65,693)
`waliddell@duanemorris.com
`DUANE MORRIS LLP
`Las Cimas IV
`900 S. Capital of Texas Hwy., Suite
`300, Austin, TX 78746
`Telephone: (512) 277-2246
`Facsimile: (512)277-2301
`
`Daniel G. Nguyen (No. 42,933)
`dnguyen@lockelord.com
`Emma A. Bennett (No. 80,631)
`emma.bennett@lockelord.com
`LOCKE LORD LLP
`600 Travis St., Suite 2800
`Houston, Texas 77002
`Telephone: (713) 226-1200
`Facsimile: (214) 223-3717
`
`David H. Bluestone (No. 44,542)
`david.bluestone@bfkn.com
`Barack Ferrazzano Kirschbaum &
`Nagelberg LLP
`200 West Madison St., Suite 3900
`Chicago, Illinois 60606
`Telephone: (312) 984-3106
`Facsimile: (312) 984-3150
`
`
`37 C.F.R. §42.8(b)(4): Service Information
`D.
`Service information is provided in the designation of counsel above. Petitioner
`
`consents to electronic service by email to GT-Cirrus-IPR@cov.com, osram-
`
`greenthread@lockelord.com,
`
`david.bluestone@bfkn.com,
`
`and
`
`BGreene@duanemorris.com.
`
`4
`
`

`

`
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. §42.103
`The Office is authorized to charge the fee set forth in 37 C.F.R. §42.15(a)(1)
`
`for this Petition to Deposit Account No. 60-3160. Review of 26 claims is requested.
`
`The undersigned further authorizes payment for any additional fees that may be due
`
`in connection with this Petition.
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies under Rule 42.104(a) that the ’014 Patent is available for
`
`IPR and Petitioner is not barred or estopped from requesting IPR of the Challenged
`
`Claims on the grounds identified in this Petition.
`
`V. OVERVIEW OF CHALLENGE AND RELIEF REQUESTED
`Prior Art Printed Publications
`A.
`The ’014 Patent claims priority to September 3, 2004. Petitioner’s challenge
`
`is based on the following prior-art references, none of which were discussed by the
`
`Patent Office during prosecution:
`
`• U.S. Patent No. 6,043,114 to Kawagoe et al. (“Kawagoe”) (Ex.1007) issued on
`
`March 28, 2000 and is prior art under §102(b).1
`
`
`1 Cites to 35 U.S.C. §§102/103 are to the pre-America Invents Act (pre-AIA).
`
`5
`
`

`

`
`
`• U.S. Patent Application Publication 2003/0183856 to Wieczorek et al.
`
`(“Wieczorek”) (Ex.1006) was filed on October 29, 2002 and published on
`
`October 2, 2003. Wieczorek is prior art under §§102(a), (e).
`
`• Wolf and Tauber, Silicon Processing for the VLSI Era, Lattice Press (2000)
`
`(“Wolf”) (Exs. 1008A-D), was published and publicly available no later than
`
`2002, and is prior art under §102(b). See Exs. 1012-1013.
`
`• U.S. Patent No. 6,163,877 to Gupta (Ex.1014) issued on December 19, 2000
`
`and is prior art under §102(b).
`
`• U.S. Patent No. 6,614,560 to Silverbrook (Ex.1046) issued September 2, 2003
`
`and is prior art under §102(b).
`
`B. Relief Requested
`Petitioner requests cancellation of the Challenged Claims as unpatentable
`
`under 35 U.S.C. §103. The specific grounds of the challenge are set forth below and
`
`are supported by the declaration of Dr. Banerjee (Ex.1003).
`
`Ground Basis
`I
`§103
`
`Claims
`1-9, 12-14, 16-21, and 23-28
`
`II
`
`III
`
`IV
`
`§103
`
`§103
`
`§103
`
`1-2, 4-9, 12-23, and 25-28
`
`1-9, 12-14, 16-21, and 23-28
`
`1-2, 4-9, 12-23, and 25-28
`
`Reference(s)
`Kawagoe
`
`Wieczorek, Wolf
`
`Kawagoe, Gupta
`
`Wieczorek, Wolf,
`Gupta
`
`6
`
`

`

`
`
`V
`
`VI
`
`§103
`
`§103
`
`19
`
`19
`
`Kawagoe,
`Silverbrook
`
`Wieczorek, Wolf,
`Silverbrook
`
`
`VI. THE ’014 PATENT
`The ’014 Patent is directed to “grading the dopant concentration” in certain
`
`regions of a semiconductor device. Ex.1001, Abstract. The Challenged Claims claim
`
`that an active and a well region of a semiconductor device have graded dopant
`
`concentrations to aid carrier movement. Id., Cl. 1.
`
`VII. PERSON OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (“POSITA”) of the subject matter of the
`
`’014 Patent would have had a Bachelor’s degree in electrical engineering, material
`
`science, applied physics, or a related field, and four years of experience in
`
`semiconductor design and manufacturing or equivalent work experience. Ex.1003,
`
`¶45. Additional education might compensate for a deficiency in experience, and
`
`vice-versa. Id. In the Intel Litigation, Patent Owner (“PO”) agreed with this POSITA
`
`characterization. Ex.1045, ¶13.
`
`VIII. CLAIM CONSTRUCTION
`Claims in an IPR are construed under the principles set forth in Phillips v.
`
`AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). 37 C.F.R. §42.100(b).
`
`7
`
`

`

`
`
`Petitioner is aware that PO took positions on the meaning of certain claim terms,
`
`listed below. See Exs. 1017, 1020.2
`
`Claim Term
`“substrate”
`
`“active region”
`
`Patent Owner’s Proposed Construction
`Plain and ordinary meaning
`(“an underlying layer”)
`
`Plain and ordinary meaning (“a doped
`silicon region at the surface of a
`semiconductor device
`where a transistor can be formed”)
`
`“to aid carrier movement from …
`[to/towards] …”
`
`Plain and ordinary meaning
`
`“well region”
`
`“active region … within which
`transistors can be formed
`
`Plain and ordinary meaning (“a doped
`region that surrounds the active region of a
`semiconductor device”)
`
`Plain and ordinary meaning (“a doped
`silicon region at the surface of a
`semiconductor device where a transistor
`can be formed”)
`
`
`
`Petitioner is further aware that, in the Intel Litigation, the Court provided its
`
`“preliminary constructions” in advance of the claim construction hearing, in which
`
`the Court offered a “preliminary construction” of plain and ordinary meaning as to
`
`each of the above-listed terms. See Ex.1044. Petitioner does not believe any terms
`
`
`For the “active region” and “well region” terms, PO’s position is reflected in
`
`2
`
`its claim construction briefing. See Ex. 1020, 28, 39-40.
`
`8
`
`

`

`
`
`need be construed to resolve the issues presented in this Petition, as the Challenged
`
`Claims are unpatentable under either party’s proposed constructions (except for the
`
`term “active region ... within which transistors can be formed,” addressed under
`
`PO’s proposed construction). Ex.1003 ¶51. Petitioner reserves the right to respond
`
`to any purported claim constructions that PO raises.
`
`IX.
`
`SPECIFIC GROUNDS FOR PETITION
`A. Ground I:
`Kawagoe renders claims 1-9, 12-14, 16-21, and 23-28 obvious. Ex.1003,
`
`¶¶63-126.
`
`1.
`
`Claims 1/21
`Preambles: “An electronic system, [the system]
`a.
`comprising:” 3
`To the extent the preamble is limiting, Kawagoe is directed to a
`
`“semiconductor integrated circuit device,” such as a microcomputer and memories
`
`that each constitute an electronic system. Ex.1007, Title, 1:13-23, 14:46-67,
`
`24:28¬31, 19:15-16, 20:1-33, 22:10-23:14, FIGS. 16-17, 23, 26(A), 28; Ex.1003,
`
`¶64; Sections IX.A.12-15.
`
`
`3 Bracketed language in headings show the difference between pairs of claims
`
`addressed together in the same section. Appendix A lists the elements and
`
`corresponding language for all Challenged Claims.
`
`9
`
`

`

`
`
`Ground I focuses on the CMOS device of Figure 23 (Embodiment 4),
`
`fabricated on a uniformly-doped epitaxial substrate taught in Embodiment 1.4 See
`
`IX.A.1.c.
`
`
`
`
`Ex.1007, FIG. 23. 5
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`4 Figures 16-17 and 23 are directed to Kawagoe’s Embodiment 4. Ex.1007,
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`14:46¬60. Figure 23 shows the same twin-well CMOS structures of Figure 16
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`without the metal layers (not recited in the Challenged Claims). Ex.1007, 17:10-
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`18:38; Ex.1003, ¶65.
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`5 All colors and colored annotations to figures added.
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`10
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`§IX.A.1.a.
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`b.
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`Elements [1.1]/[21.1]: “at least one semiconductor
`device, the at least one semiconductor device
`including:”
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`c.
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`Elements [1.2]/[21.2]: “a substrate of a first doping
`type at a first doping level having a surface;”
`Kawagoe discloses “semiconductor substrate 2” of a first doping type (p-type)
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`having a silicon “epitaxial layer 2E [] doped with a p-type impurity such as boron”
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`formed over non-epitaxial “semiconductor substrate body 2S [also] doped with a p-
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`type impurity such as boron....” Ex.1007, 14:61-15:12, 6:50-7:3. The substrate
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`(orange) has a surface, as indicated below. Ex.1003, ¶67.
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`Ex.1007, FIG. 23.
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`Kawagoe satisfies elements [1.2]/[21.2] under PO’s plain meaning
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`construction. Ex.1036; Ex.1007, 6:51-56, 14:61-67, 17:10-18:38; Ex.1003, ¶68.
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`Ex.1007, FIG. 20. As detailed below, Ground I relies on a uniformly-doped epitaxial
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`substrate in which silicon epitaxial layer 2E of the substrate is doped at the same
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`level as silicon substrate body 2S, so that the entire substrate in Figure 20 is “at a
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`first doping level.” Ex.1007, 6:60-7:3; Ex.1003, ¶69.
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`“at a first doping level” - Kawagoe teaches an epitaxial substrate (2S+2E),
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`illustrated in Figure 20, in which the non-epitaxial silicon substrate body (2S) is
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`either doped at the same or higher level compared to the epitaxial silicon layer (2E).
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`For example, Embodiment 1 describes a uniformly-doped epitaxial substrate in
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`which the “epitaxial layer 2E is doped ... in a concentration equal to the
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`[concentration] of the semiconductor substrate body 2S, e.g., 1.3x1015 atoms/cm3.”
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`Ex.1007, 6:60-7:3; id., Abstract (describing “an epitaxial layer which contains an
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`impurity of the same conduction type [and at] ... the same concentration” as the
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`bulk substrate), 2:57-3:9 (same). This uniformly-doped epitaxial substrate is
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`Kawagoe’s benchmark substrate discussed in other embodiments, including
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`Embodiment 4. Ex.1007, 12:64-65, 13:12-15, 13:66-67, 14:18-20, 15:7¬25.
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`Embodiment 4 introduces the option of a latchup-resistant substrate in which “the
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`impurity concentration of the semiconductor substrate body 2S is made higher than
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`that of the epitaxial layer 2E ... to improve the resistance to the latchup.” Ex.1007,
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`15:13-17; see also id., 3:60-63 (there is a high “degree of freedom for setting the
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`impurity concentration” in the disclosed semiconductor substrate so “as to facilitate
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`the control of the formation”). Kawagoe teaches that the “substrate body 2S is doped
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`with a p-type impurity such as boron at a concentration of about 1.5 x 1015
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`atoms/cm3.” Id., 14:64-67; Ex.1003, ¶¶70-71.
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`A POSITA would have understood that Kawagoe teaches forming Figure 23’s
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`twin-well CMOS device (Embodiment 4) on either Embodiment 1’s uniformly-
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`doped epitaxial substrate or Embodiment 4’s optional latchup-resistant substrate.
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`Ex.1003, ¶72. Specifically, a POSITA would have appreciated that Kawagoe teaches
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`a tradeoff between improving latchup resistance and minimizing manufacturing cost.
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`This understanding is consistent with the teachings of Wolf. See Ex.1008C, 524
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`(“There are many trade-offs involved in the optimization of a CMOS process”
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`including “fabrication cost[] and susceptibility to latchup.”); Ex.1003, ¶73. Indeed,
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`Kawagoe emphasizes the benefits of Embodiment 1’s uniformly-doped epitaxial
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`substrate and explains that the substrate used in Embodiment 4 is formed “as in the
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`foregoing embodiment 1 so that... the cost of the semiconductor substrate 2 is
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`lowered to about one half.” Ex.1007, 15:7-25.
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`Accordingly, a POSITA would have been motivated to use a uniformly-doped
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`epitaxial substrate to form Figure 23’s twin-well CMOS device because this
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`substrate provides “excellent film quality” that “drastically reduce[s] the defect
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`densities of the gate insulating films” and “improve[s] the [device’s] performance,
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`reliability and production yield.” Ex.1007, 12:8-40; id., 15:7-25. This substrate is
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`also easier to manufacture, helping “lower the cost” of the substrate and chip.
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`Ex.1003, ¶75; Ex.1007, 12:8-40. As a POSITA would have appreciated, Kawagoe
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`teaches that a semiconductor substrate having an “impurity high in concentration[]
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`is [undesirably] expensive.” Id., 2:15-18. To avoid this, Kawagoe repeatedly teaches
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`that using a less heavily-doped substrate body (as in Embodiment 1) can result in
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`lower cost, relative to a more heavily-doped substrate body. See id., 3:38-45; 7:13-
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`18; 12:19-24. While Embodiment 4 is disclosed as having an improved latchup
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`resistance, this requires that the substrate body is doped at a higher concentration
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`(1.5 x 1015 atoms/cm3) compared to the substrate body of Embodiment 1 (1.3 x 1015
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`atoms/cm3). See id., 6:62-64, 14:64-67.
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`Thus, a POSITA, opting to maximize cost savings over latch-up resistance,
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`would have been motivated to instead use the uniformly-doped epitaxial substrate
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`(i.e., doped at both 1.3 x 1015 atoms/cm3 for the substrate body and epitaxial layer,
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`as disclosed for Embodiment 1) as the starting material in lieu of Embodiment 4’s
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`latchup-resistant substrate to form the twin-well CMOS device of Figure 23. The use
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`of uniformly-doped epitaxial substrate as the starting material in lieu of Embodiment
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`4’s latchup-resistant substrate to form Figure 23’s twin-well CMOS devices is a
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`simple substitution of one known element with another known, closely-related
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`element, both of which are described in Kawagoe. Additionally, this substitution
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`would have been obvious to try because it involves nothing more than choosing one
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`of two ways of doping an epitaxial substrate, both described in Kawagoe, and both
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`options have predictable effects on the devices formed using those substrates. 6
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`Ex.1003, ¶74. Twin-well CMOS devices (illustrated in Figure 23) fabricated on a
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`uniformly-doped epitaxial substrate would have worked for their intended purpose.
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`Id., ¶75. As discussed in Wolf, twin-well CMOS devices were commonly formed
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`over a “uniform, lightly doped p- or n-type substrate” that provides no improved
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`latchup resistance. Ex.1008C, 523; id., 530 (“With the twin-tub [(twin-well)]
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`approach, two separate wells are formed for n- and p-channel transistors on a lightly
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`doped substrate ...”); Ex.1008B, 387-389; Ex.1007, 2:57-65 (discussing a uniform,
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`“lightly doped” epitaxial substrate).
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`6 Bos. Sci. Scimed, Inc. v. Cordis Corp., 554 F.3d 982, 991 (Fed. Cir. 2009)
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`(“Combining two embodiments disclosed adjacent to each other in a prior art
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`patent does not require a leap of inventiveness.”).
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`There would have been a reasonable expectation of success because Kawagoe
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`describes in detail the use of both uniformly-doped epitaxial substrates and latchup-
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`resistant substrates in forming CMOS devices, and repeatedly emphasizes their
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`similarity. Ex.1007, 8:40-52; 12:8-40, 14:58-60, 15:7-12 (substrate), 15:18-25
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`(epitaxial layer), 15:26-40 (transistors); Ex.1003, ¶76. A uniformly-doped epitaxial
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`substrate is also better than the bulk (non-epitaxial) substrate commonly used to
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`fabricate twin-well CMOS devices. Ex.1007, 1:33-40 (“The epitaxial wafer is
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`advantageous [compared to bulk wafer/substrate] in that ... the gate insulating film
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`to be formed over the epitaxial layer can have excellent breakdown characteristics
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`to drastically reduce the defect density of the gate insulating film.”); id., 12:8-40;
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`Ex.1008B, 387-88 (discussing twin-well CMOS devices fabricated over bulk
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`substrate); Ex.1003, ¶76.
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`Kawagoe characterizes
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`the
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`improved
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`latchup
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`tolerance provided by
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`Embodiment 4’s optional latchup-tolerant substrate as just another “effect[] [that]
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`can be achieved in addition to those of the foregoing embodiment 1,” Ex.1007,
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`19:49-63, as opposed to being vital to its operation. Consistent with Kawagoe’s
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`teachings, a POSITA would have understood that a uniformly-doped epitaxial
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`substrate is a suitable substrate because, among other benefits, it “drastically
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`reduce[s] the defect densities of the gate insulating films” of CMOS transistors.
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`Ex.1007, 12:8-40; Ex.1003, ¶77. Moreover, a POSITA would have understood that
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`susceptibility to latchup (a “short-circuit” failure condition in poorly designed
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`circuits) may not be a concern for all CMOS chips—see Ex.1008B, 406 (“four
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`conditions must exist in a CMOS circuit in order for latchup to occur.”); Ex.1026, 1
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`(“several conditions must be met” to cause latchup)—in which case it is unnecessary
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`to improve latchup resistance. Ex.1003, ¶77. Indeed, both single-well and twin-well
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`CMOS devices were commonly fabricated on uniformly-doped bulk substrates that
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`provide no improved latchup resistance. See, e.g., Ex.1008B, 387-388 (“With the
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`[twin-well] approach, ... [t]he substrate may be [] a lightly doped wafer ...”); , 652
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`(example 6.7). Even if latchup were to remain a concern, a POSITA would have
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`understood that improved latchup resistance can be achieved by other means
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`unrelated to the choice of substrate, such as careful circuit layout. Ex.1003, ¶78;
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`Ex.1008B, 381 (“La