IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`CIRRUS LOGIC, INC.;
`OMNIVISION TECHNOLOGIES, INC.; AND
`AMS SENSORS USA INC.,
`Petitioner,
`
`
`v.
`
`GREENTHREAD, LLC,
`Patent Owner.
`
`
`Case No. IPR2024-00018
`Patent No. 9,190,502
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO.
`9,190,502
`
`UNDER 35 U.S.C. §§ 312 AND 37 C.F.R. § 42.104
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES ............................................................................ 1
`A.
`Real Party-in-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Counsel Service Information ................................................................ 3
`D.
`37 C.F.R. §42.8(b)(4): Service Information ......................................... 4
`III. PAYMENT OF FEES UNDER 37 C.F.R. §42.103 ....................................... 4
`IV. CERTIFICATION OF GROUNDS FOR STANDING ................................. 5
`V. OVERVIEW OF CHALLENGE AND REQUESTED RELIEF ................... 5
`A.
`Prior Art Printed Publications .............................................................. 5
`B.
`Relief Requested ................................................................................... 6
`VI. THE ’502 PATENT ........................................................................................ 7
`VII. PERSON OF ORDINARY SKILL IN THE ART ......................................... 8
`VIII. CLAIM CONSTRUCTION ........................................................................... 9
`IX. SPECIFIC GROUNDS FOR PETITION ..................................................... 10
`A. Ground I ............................................................................................. 10
`1.
`Independent Claim 7 ................................................................ 10
`B. Grounds II-III ..................................................................................... 38
`1.
`Independent Claim 7 ................................................................ 38
`2.
`Dependent Claim 8: “The semiconductor device of claim
`7 wherein said first and second static unidirectional
`electric fields are adapted to respective grading of
`dopants to aid movements of carriers in respective active
`regions.” ................................................................................... 67
`i
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`3.
`
`2.
`
`3.
`
`Dependent Claim 11: “The semiconductor device of
`claim 7 wherein the semiconductor device is a flash
`memory device.” ...................................................................... 69
`C. Ground IV ........................................................................................... 70
`1.
`Dependent Claim 8: “The semiconductor device of claim
`7 wherein said first and second static unidirectional
`electric fields are adapted to respective grading of
`dopants to aid movements of carriers in respective active
`regions.” ................................................................................... 70
`D. Ground V ............................................................................................ 75
`1.
`Dependent Claim 9: The semiconductor device of claim
`7 wherein the semiconductor device is a central
`processing unit (CPU).” ........................................................... 76
`Dependent Claim 10: “The semiconductor device of
`claim 7 wherein the semiconductor device is a DRAM
`device.” .................................................................................... 78
`Dependent Claim 11: “The semiconductor device of
`claim 7 wherein the semiconductor device is a flash
`memory device.” ...................................................................... 79
`Ground VI ........................................................................................... 80
`1.
`Dependent Claim 9: The semiconductor device of claim
`7 wherein the semiconductor device is a central
`processing unit (CPU).” ........................................................... 80
`Dependent Claim 10: “The semiconductor device of
`claim 7 wherein the semiconductor device is a DRAM
`device.” .................................................................................... 81
`3. Motivation to combine Onoda and Wolf ................................. 81
`GROUND VII .................................................................................... 83
`1.
`Dependent Claim 12: “The semiconductor device of
`claim 7 wherein the semiconductor device is an image
`sensor device.” ......................................................................... 83
`ii
`
`E.
`
`2.
`
`F.
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`X.
`
`G. GROUND VIII ................................................................................... 85
`1.
`Dependent Claim 12: “The semiconductor device of
`claim 7 wherein the semiconductor device is an image
`sensor device.” ......................................................................... 85
`THE BOARD SHOULD INSTITUTE IPR ................................................. 89
`A.
`35 U.S.C. § 314(a) .............................................................................. 89
`B.
`35 U.S.C. § 325(d).............................................................................. 92
`C.
`Prior Terminated Petitions Do No Warrant Denying Institution ....... 96
`
`
`
`iii
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`
`
`TABLE OF EXHIBITS
`
`Exhibit
`Description
`No.
`U.S. Patent No. 9,190,502 to Rao (the “’502 Patent”)
`1001
`Prosecution History of the ’502 Patent (“the
`1002
`Prosecution History”)
`Declaration of Sanjay Banerjee, PhD
`1003
`Curriculum Vitae of Sanjay Banerjee, PhD
`1004
`U.S. Patent No. 4,684,971 (“Payne”)
`1005
`U.S. Patent No. 4,907,058 to Sakai (“Sakai”)
`1006
`U.S. Patent No. 6,043,114 to Kawagoe, et al., (“Kawagoe”)
`1007
`1008A Wolf and Tauber, Silicon Processing For The VLSI Era, Vol 1,
`Lattice Press (2000) (“Wolf.1”)
`1008B Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 2,
`Lattice Press (2000) (“Wolf.2”)
`1008C Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 3,
`Lattice Press (2000) (“Wolf.3”)
`1008D Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 4,
`Lattice Press (2000) (“Wolf.4”)
`1009
`U.S. Patent No. 4,160,985 (“Kamins”)
`1010
`U.S. Patent No. 4,481,522 (“Jastrzebski”)
`1011
`U.S. Patent Application Publication No. 2003/0042511 (“Rhodes”)
`U.S. Patent Application Publication No. 2002/0102783
`1012
`(“Fujimoto”)
`1013 Wang and Agrawal, Single Event Upset: An Embedded Tutorial,
`21st Intl Conf on VLSI Design, IEEE 2008 (“Wang”)
`Publication Declaration of Alyssa G. Resnick for Wolf.1 and
`Wolf.2 (“Resnick Decl.”)
`Publication Declaration of Rachel J. Watters for Wolf.3 and
`Wolf.4 (“Watters Decl.”)
`IPR2020-290, Patent Owner Preliminary Response
`U.S. Pat. No. 11,121,222 (the “’222 Patent”)
`U.S. Pat. No. 11,316,014 (the “’014 Patent”)
`Civil Action No. 2:19-cv-00147-JRG, Dkt. 67 (E.D. Tex. Apr. 20,
`2019)
`Prosecution History of U.S. Pat. No. 11,121,222
`
`1015
`1016
`1017
`1018
`1019
`1020
`
`1014
`
`iv
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`Exhibit
`No.
`1021
`1022
`
`1023
`
`1024
`
`1025
`1026
`
`1027
`
`1028
`1029
`1030
`1031
`1032
`1033
`1034
`1035
`1036
`1037
`1038
`1039
`1040
`1041
`1042
`
`1043
`1044
`1045
`1046
`
`Description
`Prosecution History of U.S. Pat. No. 11,316,014
`U.S. Patent Application Publication No. 2004/0063288 (“Kenney”)
`Jaeger, Introduction to Microelectronic Fabrication, Vol. V,
`Addison-Wesley Modular Series on Solid State Devices
`(1988) (“Jaeger”)
`U.S. District Courts – Case Statistics, obtained at
`https://www.uscourts.gov/statistics-reports/analysis-reports/
`federal-court-management-statistics, dated June 30, 2023
`U.S. Patent No. 4,435,896 (“Parrillo”)
`L.C. Parrillo, R.S. Payne et al., Twin-Tub CMOS - A Technology
`for VLSI Circuits, IEEE 1980 (“Parrillo2”)
`U.S. Patent Application Publication No. 2007/0045682 to Hong et
`al. (“Hong”)
`The Oxford American Dictionary and Language Guide, Oxford
`University Press (1996)
`Blank
`Patent Owner’s Responsive Claim Construction Brief
`Blank
`Patent Owner’s Sur-Reply Claim Construction Brief
`Proposed Claim Constructions in the District Court Case
`Redacted District Court Case Transfer Order
`Civil Action No. 2:19-cv-00147-JRG, Dkt. 105 (E.D. Tex. Jul. 9,
`2020)
`Publication Declaration of Sylvia Hall-Ellis for Wolf
`Dec. 21, 2022 Preliminary Claim Constructions in 6:22-CV-00105
`U.S. Patent Application Publication No. 2003/0183856 to
`Wieczorek (“Wieczorek”)
`Parrillo IEEE Citation List
`Dictionary of Scientific and Technical Terms, McGraw Hill (2003)
`Blank
`Certified translation of Japanese Unexamined Patent Application
`Publication No. H8-279598 (“Onoda”)
`Japanese Unexamined Patent Application Publication No. H8-
`279598, published on October 22, 1996
`IPR2020-290, Termination Order
`Oct. 31, 2022 Giapis Declaration, 6:22-CV-00105
`Prosecution History of U.S. Patent No. 8,421,195
`v
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`Exhibit
`No.
`1047
`1048
`1049
`1050
`
`Description
`U.S. Patent No. 6,614,560 to Silverbrook (“Silverbrook”)
`U.S. Patent No. 8,421,195 to Rao (the “’195 Patent”)
`U.S. Patent No. 5,986,924 (“Yamada”)
`Rabaey et al., Digital Integrated Circuits, A Design Perspective,
`Prentice Hall Electronics and VLSI Series (2003) (“Rabaey”)
`Sze, Semiconductor Devices Physics and Technology, 2d Ed., John
`Wiley & Sons (2002)
`Publication Declaration of Sean O’Bryan for Maziasz (“O’Bryan
`Decl.”)
`Publication Declaration of Martin L. Knott for Rabaey (“Knott
`1053
`Decl.”)
`1054 Maziasz and Hayes, Layout Minimization of CMOS Cells, Kluwer
`Academic Publishers (1992) (“Maziasz”)
`
`1051
`
`1052
`
`vi
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`Cirrus Logic, Inc., OmniVision Technologies, Inc., and ams Sensors USA,
`
`Inc. (collectively, “Petitioner”) requests inter partes review (“IPR”) of claims 7-12
`
`(the “Challenged Claims”) of U.S. Patent No. 9,190,502 (Ex.1001, “’502 Patent”).
`
`I.
`
`INTRODUCTION
`The ’502 Patent is directed to a Complementary Metal-Oxide Semiconductor
`
`(CMOS) device having graded dopant concentrations. Ex.1001, 4:52-67. This
`
`Petition demonstrates that the Challenged Claims are unpatentable as obvious.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`Cirrus Logic, Inc., OmniVision Technologies, Inc., ams Sensors USA, Inc.,
`
`OSRAM GmbH, ams-OSRAM AG, and GlobalFoundries U.S., Inc. are the real
`
`parties-in-interest.
`
`B. Related Matters
`The ’502 Patent is the subject of the following active proceedings:
`
`• Greenthread, LLC v. Cirrus Logic, Inc., Civil Action No. 1:23-cv-00369
`
`in the Western District of Texas, filed March 31, 2023 (“Cirrus District
`
`Court Case”);
`
`• Greenthread, LLC v. OmniVision Technologies, Inc., Civil Action No.
`
`2:23-cv-00212 in the Eastern District of Texas, filed May 10, 2023
`
`(“OmniVision District Court Case”);
`
`• Greenthread, LLC v. OSRAM GmbH et al., Civil Action No. 2:23-cv-
`
`1
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`00179 in the Eastern District of Texas, filed April 19, 2023 (“ams-
`
`OSRAM District Court Case”);
`
`• Greenthread, LLC v Texas Instruments Incorporated, Civil Action No.
`
`2:23-cv-00157 in the Eastern District of Texas, filed April 6, 2023; and
`
`• Greenthread, LLC v. Monolithic Power Systems, Inc., Civil Action No.
`
`1:23-cv-00579 in the District of Delaware, filed May 26, 2023.
`
`The ’502 Patent was previously subject to the following proceedings, which
`
`are no longer pending:
`
`• Greenthread, LLC v. Samsung Electronics Co., Ltd.. et al, Civil Action
`
`No. 2-19-cv-00147 in the Eastern District of Texas, filed April 30, 2019
`
`• Samsung Electronics Co., Ltd. v. Greenthread, LLC, IPR2020-00290
`
`before the Patent Trial and Appeal Board, filed December 23, 2019;
`
`• Greenthread, LLC v. Intel Corporation, Dell Inc., and Dell Technologies
`
`Inc., Civil Action No. 6:22-cv-105 in the Western District of Texas
`
`(“Intel Litigation”), filed January 27, 2022;
`
`• Greenthread, LLC v. Intel Corporation, Civil Action No. 6:22-cv-01293
`
`in the Western District of Texas, severed December 21, 2022, and
`
`transferred to District of Oregon as 3:22-cv-02001;
`
`• Greenthread, LLC v. Micron Technology, Inc. et al., Civil Action No.
`
`1:23-cv-00333 in the District of Delaware, filed March 24, 2023;
`
`2
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`• Intel Corporation v. Greenthread, LLC, IPR2023-00548, before the
`
`Patent Trial and Appeal Board, filed January 30, 2023; and
`
`• Greenthread, LLC v. Western Digital Corporation et al, Civil Action No.
`
`1:23-cv-00326 in the District of Delaware, filed March 24, 2023.
`
`C. Counsel Service Information
`Lead Counsel
`Scott Weidenfeller (No. 54,531)
`sweidenfeller@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5923
`Facsimile: (202) 778-5923
`
`Backup Counsel
`Anupam Sharma (No. 55,609)
`asharma@cov.com
`Covington & Burling LLP
`3000 El Camino Real,
`5 Palo Alto Square,
`Palo Alto, CA 94306
`Telephone: (650) 632-4720
`Facsimile: (650) 632-4800
`
`Han Park (No. 64,409)
`hpark@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5117
`Facsimile: (202) 778-5117
`
`Bert Greene (No. 48,366)
`bgreene@duanemorris.com
`Andrew Liddell (No. 65,693)
`waliddell@duanemorris.com
`DUANE MORRIS LLP
`Las Cimas IV
`900 S. Capital of Texas Hwy., Suite
`300, Austin, TX 78746
`Telephone: (512) 277-2246
`Facsimile: (512)277-2301
`
`3
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`Daniel G. Nguyen (No. 42,933)
`dnguyen@lockelord.com
`Emma A. Bennett (No. 80,631)
`emma.bennett@lockelord.com
`LOCKE LORD LLP
`600 Travis St., Suite 2800
`Houston, Texas 77002
`Telephone: (713) 226-1200
`Facsimile: (214) 223-3717
`
`David H. Bluestone (No. 44,542)
`david.bluestone@bfkn.com
`Barack Ferrazzano Kirschbaum &
`Nagelberg LLP
`200 West Madison St., Suite 3900
`Chicago, Illinois 60606
`Telephone: (312) 984-3106
`Facsimile: (312) 984-3150
`
`
`
`
`37 C.F.R. §42.8(b)(4): Service Information
`D.
`Service information is provided in the designation of counsel above. Petitioner
`
`consents to electronic service by email to GT-Cirrus-IPR@cov.com, osram-
`
`greenthread@lockelord.com,
`
`david.bluestone@bfkn.com,
`
`and
`
`BGreene@duanemorris.com.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. §42.103
`The Office is authorized to charge the fee set forth in 37 C.F.R. §42.15(a)(1)
`
`for this Petition to Deposit Account No. 60-3160. Review of 6 claims is requested.
`
`The undersigned further authorizes payment for any additional fees that may be due
`
`in connection with this Petition.
`
`4
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies under Rule 42.104(a) that the ’502 Patent is available for
`
`IPR and Petitioner is not barred or estopped from requesting IPR of the Challenged
`
`Claims on the grounds identified in this Petition.
`
`V. OVERVIEW OF CHALLENGE AND REQUESTED RELIEF
`Prior Art Printed Publications
`A.
`The ’502 Patent claims priority to September 3, 2004. Petitioner’s challenge
`
`is based on the following prior-art references, none of which were before the Patent
`
`Office during prosecution of the ’502 Patent:
`
`• Payne – U.S. Patent No. 4,684,971 to Payne (Ex.1005) issued on August 4, 1987
`
`and is prior art under §102(b).1
`
`• Onoda – Japanese Application H8-279598 to Onoda (Ex.1043, certified
`
`translation Ex.1042) published on October 22, 1996 and is prior art under
`
`§102(b).
`
`• Wolf – Wolf and Tauber, Silicon Processing, Lattice Press (2000) (Ex.1008A-
`
`D), was published and publicly available no later than 2002, and is prior art under
`
`§102(b). Exs. 1014-1015; Ex.1036.2
`
`
`1 Cites to 35 U.S.C. §§102 and 103 are to the pre-America Invents Act (pre-AIA).
`
`2 Petitioner is relying on its own retained independent librarian expert, Dr. Sylvia
`
`
`
`5
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`• Parrillo - U.S. Patent No. 4,435,896 to Parrillo and Payne (Ex.1025) issued on
`
`March 13, 1984 and is prior art under §102(b).
`
`• Silverbrook: U.S. Patent No. 6,614,560 to Silverbrook (Ex.1047) issued
`
`September 2, 2003 and is prior art under §102(b).
`
`B. Relief Requested
`The specific grounds of the challenge are set forth below and are supported
`
`by the declaration of Dr. Banerjee (Ex.1003).
`
`Ground
`
`Basis
`
`Challenged Claims
`
`Reference(s)
`
`§ 103
`
`§ 102
`
`§ 103
`
`§ 103
`
`§ 103
`
`§ 103
`
`§ 103
`
`§ 103
`
`I
`
`II
`
`III
`
`IV
`
`V
`
`VI
`
`VII
`
`VIII
`
`
`
` 7
`
`7, 8, 11
`
`7, 8, 11
`
`8
`
`9-11
`
`9, 10
`
`12
`
`12
`
`Payne
`
`Onoda
`
`Onoda
`
`Payne, Parrillo
`
`Payne, Wolf
`
`Onoda, Wolf
`
`Payne, Silverbrook
`
`Onoda, Silverbrook
`
`
`Hall-Ellis, to verify the public availability of the Wolf reference.
`
`6
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`VI. THE ’502 PATENT
`The ’502 Patent is directed to “grading the dopant concentration” in certain
`
`regions of a semiconductor device. Ex.1001, Title, Abstract. The Challenged Claims
`
`claim that a single drift layer (SDL) and a well region of a semiconductor device
`
`have graded dopant concentrations to aid movement of minority carriers from the
`
`surface layer to the substrate. Id., Cl. 7.
`
`The ’502 Patent admits that graded dopant concentrations were known. For
`
`example, the graded dopant concentration “B” (green) in Figure 1 below is described
`
`as one of “the two most popular” doping profiles used in prior art bipolar transistors,
`
`in contrast to the uniform doping profile “A” (red). Ex.1001, 2:17-19.
`
`
`
`Ex.1001, FIG. 1 (“Prior Art”).3 The ’502 Patent further admits that it was known to
`
`grade the dopant concentration in well regions of CMOS devices to affect the
`
`movement of carriers, but alleges, without support, that prior attempts were met with
`
`“little success.” Id., 1:63-2:9.
`
`7
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`The claims of the ’502 Patent issued after a terminal disclaimer was filed to
`
`overcome a double patenting rejection over the issued claims of the parent patent.
`
`Ex.1002, 50-53, 104. There were no prior art rejections. Id., 53. During prosecution
`
`of the parent ’195 Patent, the Examiner found that the prior art, including Kamins
`
`and Jastrzebski, teaches all the elements of then-pending independent claim 10.
`
`Ex.1046 (12/20/11 Office Action), 3–5; (8/13/12 Office Action), 3-5. In response,
`
`Applicant amended claim 10 to add an element which recites “at least one well
`
`region disposed in said single drift layer, said well region having a graded
`
`concentration of dopants ….” and which is substantially the same as current element
`
`[7.6]. Ex.1046 (10/15/12 Office Action Response), 3. The Examiner allowed the as-
`
`amended claim 10 (issued claim 1 of the ’195 Patent) and claims depending
`
`therefrom, citing this added element as the reason for allowance of these claims.
`
`Ex.1046, (12/12/12 Notice), 2-3; Ex.1048, claim 1.
`
`VII. PERSON OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (“POSITA”) of the subject matter of the
`
`’502 Patent would have had a Bachelor’s degree in electrical engineering, material
`
`science, applied physics, or a related field, and four years of experience in
`
`semiconductor design and manufacturing or equivalent work experience. Ex.1003,
`
`¶¶57-60. Additional education might compensate for a deficiency in experience, and
`
`8
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`vice-versa. Id. Notably, in the Intel Litigation, Patent Owner agreed with this
`
`characterization of a POSITA. Ex.1045, ¶13.
`
`VIII. CLAIM CONSTRUCTION
`Claims in an IPR are construed under Phillips v. AWH Corp., 415 F.3d 1303
`
`(Fed. Cir. 2005) (en banc). 37 C.F.R. §42.100(b). Petitioner is aware that Patent
`
`Owner took positions on the meaning of certain claim terms, which are listed below.
`
`See Exs. 1030, 1032-1033.5
`
`Claim Term
`
`“substrate”
`
`“active region”
`
`“to aid carrier movement from . . .
`[to/towards] . . .”
`“well region”
`
`“active region … within which
`transistors can be formed”
`
`
`
`Patent Owner’s Proposed
`Construction
`Plain and ordinary meaning, where
`the plain and ordinary meaning is an
`“underlying layer”
`Plain and ordinary meaning (“a doped
`silicon region at the surface of a
`semiconductor device where a
`transistor can be formed”)
`Plain and ordinary meaning
`
`Plain Meaning (“a doped region that
`surrounds the active region of a
`semiconductor device”)
`Plain Meaning (“a doped silicon
`region at the surface of a
`semiconductor device where a
`transistor can be formed”)
`
`
`5 As to the “active region” terms, Patent Owner’s position is reflected in its claim
`
`construction briefing. See Ex.1030, 28, 40.
`
`9
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
`
`Petitioner is further aware that, in the Intel Litigation, the Court provided its
`
`“preliminary constructions” in advance of the claim construction hearing, in which
`
`the Court offered a “preliminary construction” of plain and ordinary meaning as to
`
`each of the above-listed terms. See Ex. 1037. Petitioner does not believe any terms
`
`need be construed to resolve the issues presented in this Petition, and Petitioner takes
`
`no position regarding claim construction at this time. The Challenged Claims are
`
`unpatentable under either their plain and ordinary meaning, or under Patent Owner’s
`
`proposed constructions (except for the term “active region ... within which
`
`transistors can be formed,” which is addressed in the sections below). Petitioner
`
`reserves the right to respond to any purported claim constructions that Patent Owner
`
`raises.
`
`IX. SPECIFIC GROUNDS FOR PETITION
`A. Ground I
`Payne renders claim 7 obvious. Ex.1003, ¶¶72-119.
`
`1.
`
`Independent Claim 7
`Preamble: “A semiconductor device comprising:”
`a.
`Payne is directed to a semiconductor device. Ex.1003, ¶73; Ex.1005, Title,
`
`Abstract, 1:51-54 (“it is a primary object of the invention to provide a CMOS
`
`structure and method of manufacture which requires little semiconductor space and
`
`therefore permits a high packing density.”), 1:5-15 (“Complementary field effect
`
`transistors (hereinafter designated CMOS) [] comprise n-channel and p-channel
`
`10
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`devices . . .”). Payne’s Figure 10 illustrates a “p-channel” (PMOS) transistor (with
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`“P+” source/drain regions 21/22) adjacent to an “n-channel” (NMOS) transistor
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`(with “N+” source/drain regions 23/24) of a CMOS semiconductor device. Id., 2:50-
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`60, 5:18-34, 6:57-59.
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`Ex.1005, FIG. 10.3
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`Element [7.1]: “a surface layer;”
`b.
`Payne discloses, or at a minimum, renders obvious this element. Ex.1003,
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`¶¶74-76. According to Patent Owner (“PO”), a “surface layer” is “a layer at the
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`surface of the silicon” (or “a layer at the surface of the semiconductor device”)—
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`which PO annotated in blue below—“where the active region [(red)] is located.”
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`Ex.1030, 6, 9, 12, 13; Ex.1033.
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`3 All colors and colored annotations to figures added.
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`Ex.1001, FIG. 5(b); Ex.1030, 7, 12.
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`Payne satisfies element [7.1] to the same extent that Figure 5(b) of the ’502
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`Patent meets it. Ex.1003, ¶¶74-75. Payne’s Figure 10 discloses a surface layer (blue)
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`that matches the surface layer PO identified in Figure 5(b). Payne’s surface layer—
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`a subset of what Payne refers to as “surface region 18”—is at the surface of silicon
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`substrate 10, and “source and drain regions, 21 and 22 [(red)] of P+ conductivity” of
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`Payne’s p-channel transistor (left) are located in it. Ex.1005, 2:50-60; 5:21-27, 6:57-
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`59, FIG. 1.
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`Ex.1005, FIG. 10. Payne likewise discloses another surface layer—a subset of
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`“surface region 20”—containing “source and drain regions, 23 and 24, of N+
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`conductivity” of Payne’s n-channel transistor (right). Id., 5:24-27, 6:57-59; Ex.1003,
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`¶76.
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`Ex.1005, FIG. 10.
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`Element [7.2]: “a substrate;”
`c.
`Payne discloses this element. Ex.1003, ¶¶77-78. Payne’s Figure 10 illustrates
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`a CMOS device “fabricated in a silicon semiconductor substrate [(grey)] 10 of ‘N-’
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`conductivity type which typically has a doping concentration of approximately 1-
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`2x1014 ions/cm3[.]” Ex.1005, 1:60-62, 2:50-60.4
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`4 All emphases added unless otherwise noted.
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`Ex.1005, FIG. 10.
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`Payne satisfies element [7.2] under PO’s proposed construction of “plain and
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`ordinary meaning [i.e.] ‘an underlying layer.’” Ex.1033. Payne’s substrate also
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`matches PO’s identification of the substrate (grey) in Figure 5(b) of the ’502 Patent.5
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`5 Patent Owner used Figure 5(b) from the parent ’195 Patent as an example. Ex.
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`1030, 5-6. The ’502 Patent and the ’195 Patent have the identical specification and
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`figures, including Figure 5(b).
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`Ex.1030, 6-7, 16-17 (well region and drift layer can be part of substrate); Ex.1001,
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`FIG. 5(b). See also Ex.1005, 1:60-65, 2:50-60 (“the [CMOS] device is fabricated in
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`a silicon semiconductor substrate, 10”), FIGS. 1, 10.
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`d.
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`Element [7.3]: “an active region including a source and
`a drain, disposed on one surface of said surface layer;”
`Payne discloses or, at a minimum, renders obvious this element. Ex.1003,
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`¶¶79-83. According to PO, Figure 5(b) of the ’502 Patent depicts an active region
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`(red) “disposed on one surface [(top surface)] of said surface layer”:
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`Ex.1001, FIG. 5(b); Ex.1030, 6-7, 11 (“[T]he ‘active region’ is part of the ‘surface
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`layer’ … When the claim says the active region is ‘disposed on one surface of the
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`surface layer,’ it means the active region is located on the ‘ceiling’ of the silicon
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`inside the silicon.”) (emphasis in original), 12.
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`Payne satisfies element [7.3] under PO’s interpretation. Ex.1003, ¶80. Payne’s
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`Figure 10 below illustrates a “p-channel” transistor with source/drain regions 21/22
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`(left), and an “n-channel” transistor with source/drain regions 23/24 (right). Ex.1005,
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`5:18-29, 1:5-19, 6:57-59. These source/drain regions are formed with “a surface
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`impurity concentration of approximately 1019–1020 ions/cm3.” Ex.1005, 5:21-29,
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`1:43-45. The channel region between these source/drain regions is part of the surface
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`region, which has an impurity concentration of “typically 0.5-5X1016 ions/cm3.”
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`Ex.1005, 5:51-52, 4:31-39, 4:63-5:5. The source/drain regions of a transistor,
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`together with the channel region in between them, form an active region. Ex.1003
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`¶¶80-81; Ex.1008B, 299 (“The top surface of the [silicon substrate] body consists of
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`active or transistor regions as well as passive or (field) regions. The active regions
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`are those in which transistor action occurs; i.e., the channel and the heavily doped
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`source and drain regions.”), 300, FIG. 5-2, 382, FIG. 6-8(c), 387, FIG. 6-10;
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`Ex.1008C, 525, FIG. 8-1(e).
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`The active region (red) of each of Payne’s transistors is disposed on one
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`surface (top surface) of a corresponding surface layer (blue), exactly as depicted in
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`PO’s annotated Figure 5(b) above. Ex.1003, ¶82; §IX.A.1.b.
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`Ex.1005, FIG. 10.
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`Payne satisfies element [7.3] under PO’s position that “active region” means
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`“a doped silicon region at the surface of a semiconductor device (e.g., the source and
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`drain and silicon between them) where a transistor can be formed” (Ex.1033)
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`because the active region of a MOS transistor is “[its] channel and [its] heavily doped
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`source and drain regions,” highlighted in red below. Ex.1008B, 299; Ex.1003, ¶83.
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`Ex.1008B, FIG. 5-1; id., 298-301, 374, FIGS. 5-2, 6-4.
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`e.
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`Element [7.4]: “a single drift layer disposed between
`the other surface of said surface layer and said
`substrate,”
`Payne discloses or, at a minimum, renders obvious this element. Ex.1003,
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`¶¶84-88.
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`Single drift layer (“SDL”) – In its claim construction brief, PO identified the
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`SDL in tan in Figure 5(b). Ex.1030, 7. According to PO, the SDL (tan) is “disposed
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`between ‘the other surface [(bottom surface)] of said surface layer [(blue)]’ and
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`[said] substrate [(grey)]”:
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`Ex.1001, FIG. 5(b); Ex.1030, 7. The SDL in Figure 5(b) has a well region (green)
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`disposed in it, forming a nested structure, as required by the claim (see element
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`[7.6]), and as shown below:
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`Ex.1001, FIG. 5(b); Ex.1030 at 7; id., 11 (“the ‘well region’ is part of the ‘single
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`drift layer.’”).
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`Payne discloses a single drift layer (SDL) to the same extent the ’502 Patent’s
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`Figure 5(b) does. Ex.1003, ¶¶86-88. In Payne’s Figure 10, the “first tub region” 15
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`(tan) of Payne’s nested well structure—with shallow well (“surface region”) 18
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`disposed in it—is an example of the claimed single drift layer. Id.; Ex.1005, 3:28-42
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`(ion implantation for tub 15), 4:19-30 (thermal drive-in to achieve the desired depth
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`for tub 15), 4:31-39, 5:7-17, 5:44-48, 5:48-50 (“In a typical device, the final depth
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`of surface regions 18 and 20 would be approximately 1-2μ and the depth of the tub
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`regions 15 and 17 would be typically 3-8μ.”). This SDL (tan) is “disposed between
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`‘the other surface [(bottom surface)] of said surface layer [(blue)]’ and [said]
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`substrate [(grey)]” under PO’s interpretation, and in exactly the same way as
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`depicted in PO’s annotated Figure 5(b) above.
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`Ex.1005, FIG. 10. Payne’s tub 17 (right), in which shallow well 20 is disposed, is
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`likewise an SDL (tan) disposed between a surface layer (blue) and the substrate
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`(grey). Ex.1005, 4:3-30, 4:63-5:17, 5:44-50; Ex.1003, ¶87; §IX.A.1.b.
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`Payne meets all other claim requirements associated with the SDL to the same
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`extent Figure 5(b) meets them. See below and elements [7.5]-[7.6]; Ex.1003, ¶¶88.
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`Notably, as detailed in element [7.5], each of Payne’s tubs 15/17 is a single drift
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`layer (SDL) because it has a graded-dopant concentration that, according to PO,
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`creates a unidirectional electric drift field that aids the movement of minority carriers
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`in a single direction—from the surface layer to the substrate. Ex.1030, 7; Ex.1046,
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`253-54, 289-290; §IX.A.1.f.
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`f.
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`Element [7.5]: “said drift layer having a graded
`concentration of dopants generating a first static
`unidirectional electric drift field to aid the movement
`of minority carriers from said surface layer to said
`substrate; and”
`Payne discloses or, at a minimum, renders obvious this element. Ex.1003,
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`¶¶89-108.
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`Graded-dopant concentration – The ’502 Patent admits that graded-dopant
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`concentrations were known, Ex.1001, 2:17-19, FIG. 1 (“Prior Art”), and that it was
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`known to grade the dopant concentration in CMOS devices to affect the movement
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`of minority carriers. Id., 1:34-2:5, FIGS. 3(a)-3(d) (all “Prior art”). Payne’s SDL has
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`a graded-dopant concentration extending between the surface layer and the substrate.
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`Ex.1003 ¶90. Payne explains that the “impurity profile in both tubs [15/17] thereby
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`has the general shape illustrated in FIG. 11” which exhibits “[t]he major advantage”
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`of a “high-low implant profile.” Ex.1005, 2:38-41, 5:14-17, 5:56-57. Payne’s Figure
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`Petition for Inter Partes Review of U.S. Patent No. 9,190,502
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`11 (below right) illustrates the dopant concentration measured along the red dotted
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`line in Figure 10 (below left), which starts at the bottom of the surface layer (blue)
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`and extends to the substrate (grey). As shown below, Payne discloses a downward-
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`slo