IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`CIRRUS LOGIC, INC.;
`OMNIVISION TECHNOLOGIES, INC.; AND
`AMS SENSORS USA INC.,
`Petitioner,
`
`
`v.
`
`GREENTHREAD, LLC,
`Patent Owner.
`
`
`Case No. IPR2024-00017
`Patent No. 8,421,195
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO.
`8,421,195
`
`UNDER 35 U.S.C. §§ 312 AND 37 C.F.R. § 42.104
`
`
`
`
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,421,195
`
`TABLE OF CONTENTS
`INTRODUCTION .......................................................................................... 1
`I.
`II. MANDATORY NOTICES ............................................................................ 1
`A.
`Real Party-in-Interest ........................................................................... 1
`B.
`Related Matters ..................................................................................... 1
`C.
`Counsel Service Information ................................................................ 3
`D.
`37 C.F.R. §42.8(b)(4): Service Information ......................................... 4
`PAYMENT OF FEES UNDER 37 C.F.R. §42.103 ....................................... 4
`III.
`IV. CERTIFICATION OF GROUNDS FOR STANDING ................................. 5
`V. OVERVIEW OF CHALLENGE AND REQUESTED RELIEF ................... 5
`A.
`Prior Art Printed Publications .............................................................. 5
`B.
`Relief Requested ................................................................................... 6
`VI. PERSON OF ORDINARY SKILL IN THE ART ......................................... 6
`VII. CLAIM CONSTRUCTION ........................................................................... 7
`VIII. SPECIFIC GROUNDS FOR PETITION ....................................................... 8
`A. Ground I: .............................................................................................. 8
`1.
`Independent Claim 1 .................................................................. 8
`2.
`Dependent Claim 2: “The CMOS semiconductor device
`of claim 1 wherein the said drift layer is a deeply-
`implanted layer.” ...................................................................... 36
`Dependent Claims 4/5: “The CMOS Semiconductor
`device of claim 1, wherein said graded concentration
`follows a [linear/quasilinear] gradient.” .................................. 38
`Dependent Claim 6: “The CMOS Semiconductor device
`of claim 1, wherein said graded concentration follows an
`exponential gradient.” .............................................................. 41
`i
`
`3.
`
`4.
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,421,195
`
`B.
`
`3.
`
`4.
`
`C.
`
`Grounds II–III ..................................................................................... 44
`1.
`Independent Claim 1 ................................................................ 44
`2.
`Dependent Claim 2: “The CMOS semiconductor device
`of claim 1 wherein the said drift layer is a deeply-
`implanted layer.” ...................................................................... 77
`Dependent Claim 3: “The CMOS semiconductor device
`of claim 1 wherein said drift layer is an epitaxial layer.” ........ 81
`Dependent Claims 4/5: “The CMOS Semiconductor
`device of claim 1, wherein said graded concentration
`follows a [linear/quasi-linear] gradient.” ................................. 82
`Dependent Claim 6: “The CMOS Semiconductor device
`of claim 1, wherein said graded concentration follows an
`exponential gradient.” .............................................................. 86
`Ground IV ........................................................................................... 89
`1.
`Dependent Claim 2: “The CMOS semiconductor device
`of claim 1 wherein the said drift layer is a deeply-
`implanted layer.” ...................................................................... 89
`Dependent Claim 3: “The CMOS semiconductor device
`of claim 1 wherein said drift layer is an epitaxial layer.” ........ 92
`D. Ground V ............................................................................................ 94
`1.
`Dependent Claim 3: “The CMOS semiconductor device
`of claim 1 wherein said drift layer is an epitaxial layer.” ........ 94
`IX. THE BOARD SHOULD INSTITUTE IPR ................................................. 97
`A.
`35 U.S.C. § 314(a) .............................................................................. 97
`B.
`35 U.S.C. § 325(d)............................................................................ 100
`C.
`Prior Terminated Petitions Do No Warrant Denying Institution ..... 104
`
`
`
`5.
`
`2.
`
`ii
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,421,195
`
`
`
`TABLE OF EXHIBITS
`
`Exhibit
`Description
`No.
`U.S. Patent No. 8,421,195 to Rao (the “’195 Patent”)
`1001
`Prosecution History of the ’195 Patent (“the
`1002
`Prosecution History”)
`Declaration of Sanjay Banerjee, PhD
`1003
`Curriculum Vitae of Sanjay Banerjee, PhD
`1004
`U.S. Patent No. 4,684,971 (“Payne”)
`1005
`U.S. Patent No. 4,907,058 to Sakai (“Sakai”)
`1006
`U.S. Patent No. 6,043,114 to Kawagoe, et al., (“Kawagoe”)
`1007
`1008A Wolf and Tauber, Silicon Processing For The VLSI Era, Vol 1,
`Lattice Press (2000) (“Wolf.1”)
`1008B Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 2,
`Lattice Press (2000) (“Wolf.2”)
`1008C Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 3,
`Lattice Press (2000) (“Wolf.3”)
`1008D Wolf and Tauber, Silicon Processing For The VLSI Era, Vol. 4,
`Lattice Press (2000) (“Wolf.4”)
`1009
`U.S. Patent No. 4,160,985 (“Kamins”)
`1010
`U.S. Patent No. 4,481,522 (“Jastrzebski”)
`1011
`U.S. Patent Application Publication No. 2003/0042511 (“Rhodes”)
`U.S. Patent Application Publication No. 2002/0102783
`1012
`(“Fujimoto”)
`1013 Wang and Agrawal, Single Event Upset: An Embedded Tutorial,
`21st Intl Conf on VLSI Design, IEEE 2008 (“Wang”)
`Publication Declaration of Alyssa G. Resnick for Wolf.1 and
`Wolf.2 (“Resnick Decl.”)
`Publication Declaration of Rachel J. Watters for Wolf.3 and
`Wolf.4 (“Watters Decl.”)
`IPR2020-00289, Patent Owner Preliminary Response
`U.S. Pat. No. 11,121,222 (the “’222 Patent”)
`U.S. Pat. No. 11,316,014 (the “’014 Patent”)
`Civil Action No. 2:19-cv-00147-JRG, Dkt. 67 (E.D. Tex. Apr. 20,
`2019)
`Prosecution History of U.S. Pat. No. 11,121,222
`
`1015
`1016
`1017
`1018
`1019
`1020
`
`1014
`
`iii
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,421,195
`
`Exhibit
`No.
`1021
`1022
`
`1023
`
`1024
`
`1025
`1026
`
`1027
`
`1028
`1029
`1030
`1031
`1032
`1033
`1034
`1035
`1036
`1037
`1038
`1039
`1040
`
`1041
`
`1042
`
`1043
`
`Description
`Prosecution History of U.S. Pat. No. 11,316,014
`U.S. Patent Application Publication No. 2004/0063288 (“Kenney”)
`Jaeger, Introduction to Microelectronic Fabrication, Vol. V,
`Addison-Wesley Modular Series on Solid State Devices
`(1988) (“Jaeger”)
`U.S. District Courts – Case Statistics, obtained at
`https://www.uscourts.gov/statistics-reports/analysis-reports/
`federal-court-management-statistics, dated June 30, 2023
`U.S. Patent No. 4,435,896 (“Parrillo”)
`L.C. Parrillo, R.S. Payne et al., Twin-Tub CMOS - A Technology
`for VLSI Circuits, IEEE 1980 (“Parrillo2”)
`U.S. Patent Application Publication No. 2007/0045682 to Hong et
`al. (“Hong”)
`The Oxford American Dictionary and Language Guide, Oxford
`University Press (1996)
`Blank
`Patent Owner’s Responsive Claim Construction Brief
`Blank
`Patent Owner’s Sur-Reply Claim Construction Brief
`Proposed Claim Constructions in the District Court Case
`Redacted District Court Case Transfer Order
`Civil Action No. 2:19-cv-00147-JRG, Dkt. 105 (E.D. Tex. Jul. 9,
`2020)
`Publication Declaration of Sylvia Hall-Ellis for Wolf
`Dec. 21, 2022 Preliminary Claim Constructions in 6:22-CV-00105
`U.S. Patent Application Publication No. 2003/0183856 to
`Wieczorek (“Wieczorek”)
`Parrillo IEEE Citation List
`Dictionary of Engineering, McGraw Hill (2003)
`Rubin et al., Ranges and Moments of Depth Distributions of Boron
`and Phosphorus Implanted into Silicon in the Energy Range 1.7 -
`5.0 MeV with an Eaton NV-GSD/VHE Implanter, IEEE 1997
`(“Rubin”)
`Certified translation of Japanese Unexamined Patent Application
`Publication No. H8-279598 (“Onoda”)
`Japanese Unexamined Patent Application Publication No. H8-
`279598, published on October 22, 1996
`iv
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 8,421,195
`
`Exhibit
`No.
`1044
`1045
`
`Description
`IPR2020-289, Termination Order
`Oct. 31, 2022 Giapis Declaration, 6:22-CV-00105
`
`v
`
`

`

`
`
`Cirrus Logic, Inc., OmniVision Technologies, Inc., and ams Sensors USA, Inc.
`
`(collectively, “Petitioner”) requests inter partes review (“IPR”) of claims 1-6 (the
`
`“Challenged Claims”) of U.S. Patent No. 8,421,195 (Ex.1001, “’195 Patent”).
`
`I.
`
`INTRODUCTION
`The ’195 Patent is directed to a Complementary Metal-Oxide Semiconductor
`
`(CMOS) device having graded dopant concentrations. Ex.1001, 4:13-29. This
`
`Petition demonstrates that the Challenged Claims are unpatentable as anticipated and
`
`obvious.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`Cirrus Logic, Inc., OmniVision Technologies, Inc., ams Sensors USA, Inc.,
`
`OSRAM GmbH, ams-OSRAM AG, and GlobalFoundries U.S., Inc. are the real
`
`parties-in-interest.
`
`B. Related Matters
`The ’195 Patent is the subject of the following active proceedings:
`
`• Greenthread, LLC v. Cirrus Logic, Inc., Civil Action No. 1:23-cv-00369
`
`in the Western District of Texas, filed March 31, 2023 (“Cirrus District
`
`Court Case”);
`
`• Greenthread, LLC v. OmniVision Technologies, Inc., Civil Action No.
`
`2:23-cv-00212 in the Eastern District of Texas, filed May 10, 2023
`
`(“OmniVision District Court Case”);
`- 1 -
`
`

`

`
`
`• Greenthread, LLC v. OSRAM GmbH et al., Civil Action No. 2:23-cv-
`
`00179 in the Eastern District of Texas, filed April 19, 2023 (“ams-
`
`OSRAM District Court Case”);
`
`• Greenthread, LLC v Texas Instruments Incorporated, Civil Action No.
`
`2:23-cv-00157 in the Eastern District of Texas, filed April 6, 2023; and
`
`• Greenthread, LLC v. Monolithic Power Systems, Inc., Civil Action No.
`
`1:23-cv-00579 in the District of Delaware, filed May 26, 2023.
`
`The ’195 Patent was previously subject to the following proceedings, which
`
`are no longer pending:
`
`• Greenthread, LLC v. Samsung Electronics Co., Ltd.. et al, Civil Action
`
`No. 2-19-cv-00147 in the Eastern District of Texas, filed April 30, 2019
`
`• Samsung Electronics Co., Ltd. v. Greenthread, LLC, IPR2020-00289
`
`before the Patent Trial and Appeal Board, filed December 23, 2019;
`
`• Greenthread, LLC v. Intel Corporation, Dell Inc., and Dell Technologies
`
`Inc., Civil Action No. 6:22-cv-105 in the Western District of Texas
`
`(“Intel Litigation”), filed January 27, 2022;
`
`• Greenthread, LLC v. Intel Corporation, Civil Action No. 6:22-cv-01293
`
`in the Western District of Texas, severed December 21, 2022, and
`
`transferred to District of Oregon as 3:22-cv-02001;
`
`• Greenthread, LLC v. Micron Technology, Inc. et al., Civil Action No.
`
`- 2 -
`
`

`

`
`
`1:23-cv-00333 in the District of Delaware, filed March 24, 2023;
`
`• Intel Corporation v. Greenthread, LLC, IPR2023-00548, before the
`
`Patent Trial and Appeal Board, filed January 30, 2023; and
`
`• Greenthread, LLC v. Western Digital Corporation et al, Civil Action No.
`
`1:23-cv-00326 in the District of Delaware, filed March 24, 2023.
`
`C. Counsel Service Information
`Lead Counsel
`Scott Weidenfeller (No. 54,531)
`sweidenfeller@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5923
`Facsimile: (202) 778-5923
`
`Backup Counsel
`Anupam Sharma (No. 55,609)
`asharma@cov.com
`Covington & Burling LLP
`3000 El Camino Real,
`5 Palo Alto Square,
`Palo Alto, CA 94306
`Telephone: (650) 632-4720
`Facsimile: (650) 632-4800
`
`Han Park (No. 64,409)
`hpark@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5117
`Facsimile: (202) 778-5117
`
`Bert Greene (No. 48,366)
`bgreene@duanemorris.com
`Andrew Liddell (No. 65,693)
`waliddell@duanemorris.com
`DUANE MORRIS LLP
`Las Cimas IV
`900 S. Capital of Texas Hwy., Suite
`300, Austin, TX 78746
`Telephone: (512) 277-2246
`- 3 -
`
`

`

`
`
`Facsimile: (512)277-2301
`
`Daniel G. Nguyen (No. 42,933)
`dnguyen@lockelord.com
`Emma A. Bennett (No. 80,631)
`emma.bennett@lockelord.com
`LOCKE LORD LLP
`600 Travis St., Suite 2800
`Houston, Texas 77002
`Telephone: (713) 226-1200
`Facsimile: (214) 223-3717
`
`David H. Bluestone (No. 44,542)
`david.bluestone@bfkn.com
`Barack Ferrazzano Kirschbaum &
`Nagelberg LLP
`200 West Madison St., Suite 3900
`Chicago, Illinois 60606
`Telephone: (312) 984-3106
`Facsimile: (312) 984-3150
`
`
`
`
`37 C.F.R. §42.8(b)(4): Service Information
`D.
`Service information is provided in the designation of counsel above. Petitioner
`
`consents to electronic service by email to GT-Cirrus-IPR@cov.com, osram-
`
`greenthread@lockelord.com,
`
`david.bluestone@bfkn.com,
`
`and
`
`BGreene@duanemorris.com.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. §42.103
`The Office is authorized to charge the fee set forth in 37 C.F.R. §42.15(a)(1)
`
`for this Petition to Deposit Account No. 60-3160. Review of 6 claims is requested.
`
`- 4 -
`
`

`

`
`
`The undersigned further authorizes payment for any additional fees that may be due
`
`in connection with this Petition.
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies under Rule 42.104(a) that the ’195 Patent is available for
`
`IPR and Petitioner is not barred or estopped from requesting IPR of the Challenged
`
`Claims on the grounds identified in this Petition.
`
`V. OVERVIEW OF CHALLENGE AND REQUESTED RELIEF
`Prior Art Printed Publications
`A.
`The ’195 Patent claims priority to September 3, 2004. Petitioner’s challenge
`
`is based on the following prior-art references, none of which were before the Patent
`
`Office during prosecution of the ’195 Patent:
`
`• Payne – U.S. Patent No. 4,684,971 to Payne (Ex.1005) issued on August 4, 1987
`
`and is prior art under §102(b).1
`
`• Onoda – Japanese Application H8-279598 to Onoda (Ex.1043, certified
`
`translation Ex.1042) published on October 22, 1996 and is prior art under
`
`§102(b).
`
`
`1 Cites to 35 U.S.C. §§102 and 103 are to the pre-America Invents Act (pre-AIA).
`
`- 5 -
`
`

`

`
`
`• Wolf – Wolf and Tauber, Silicon Processing, Lattice Press (2000) (Ex.1008A-
`
`D), was published and publicly available no later than 2002, and is prior art under
`
`§102(b). Exs. 1014-1015; Ex.1036.2
`
`• Parrillo - U.S. Patent No. 4,435,896 to Parrillo and Payne (Ex.1025) issued on
`
`March 13, 1984 and is prior art under §102(b).
`
`B. Relief Requested
`The specific grounds of the challenge are set forth below and are supported
`
`by the declaration of Dr. Banerjee (Ex.1003).
`
`Ground
`
`Basis
`
`Challenged Claims Reference(s)
`
`I
`
`II
`
`III
`
`IV
`
`V
`
`§ 103
`
`§ 102
`
`§ 103
`
`§ 103
`
`§ 103
`
`1-2, 4-6
`
`1-6
`
`1-6
`
`2, 3
`
`3
`
`Payne
`
`Onoda
`
`Onoda/Wolf
`
`Payne/Wolf
`
`Payne/Parrillo
`
`
`VI. PERSON OF ORDINARY SKILL IN THE ART
`A person of ordinary skill in the art (“POSITA”) of the subject matter of the
`
`’195 Patent would have had a Bachelor’s degree in electrical engineering, material
`
`
`2 Petitioner is relying on its own retained independent librarian expert, Dr. Sylvia
`
`Hall-Ellis, to verify the public availability of the Wolf reference.
`
`- 6 -
`
`

`

`
`
`science, applied physics, or a related field, and four years of experience in
`
`semiconductor design and manufacturing or equivalent work experience. Ex.1003,
`
`¶¶55-58. Additional education might compensate for a deficiency in experience, and
`
`vice-versa. Id. Notably, in the Intel Litigation, Patent Owner agreed with this
`
`characterization of a POSITA. Ex.1045, ¶13.
`
`VII. CLAIM CONSTRUCTION
`Claims in an IPR are construed under Phillips v. AWH Corp., 415 F.3d 1303
`
`(Fed. Cir. 2005) (en banc). 37 C.F.R. §42.100(b). Petitioner is aware that Patent
`
`Owner took positions on the meaning of certain claim terms, which are listed below.
`
`See Exs.1030, 1032, 1033.5
`
`Claim Term
`
`“surface layer”
`
`“substrate”
`
`“active region”
`
`“to aid carrier movement from . . .
`[to/towards] . . .”
`“well region”
`
`Patent Owner’s Proposed
`Construction
`Plain and ordinary meaning (“a layer
`at the surface”)
`Plain and ordinary meaning
` (“underlying layer”)
`Plain and ordinary meaning (“a doped
`silicon region at the surface of a
`semiconductor device where a
`transistor can be formed”)
`Plain and ordinary meaning
`
`Plain and ordinary meaning (“a doped
`region that surrounds the active region
`of a semiconductor device”)
`
`
`5 As to the “active region” terms, Patent Owner’s position is reflected in its claim
`
`construction briefing. See Ex.1030, 28, 40.
`
`- 7 -
`
`

`

`
`
`“active region … within which
`transistors can be formed”
`
`Plain and ordinary meaning (“a
`doped silicon region at the surface of a
`semiconductor device where a
`transistor can be formed”)
`
`
`Petitioner is further aware that, in the Intel Litigation, the Court provided its
`
`“preliminary constructions” in advance of the claim construction hearing, in which
`
`the Court offered a “preliminary construction” of plain and ordinary meaning as to
`
`each of the above-listed terms. See Ex.1037. Petitioner does not believe any terms
`
`need be construed to resolve the issues presented in this Petition, and Petitioner takes
`
`no position regarding claim construction at this time. The Challenged Claims are
`
`unpatentable under either their plain and ordinary meaning, or under Patent Owner’s
`
`proposed constructions (except for the term “active region ... within which
`
`transistors can be formed,” which is addressed in the sections below). Petitioner
`
`reserves the right to respond to any purported claim constructions that Patent Owner
`
`raises.
`
`VIII. SPECIFIC GROUNDS FOR PETITION
`A. Ground I:
`Payne renders claims 1-2 and 4-6 obvious. Ex.1003, ¶¶72-130.
`
`1.
`
`Independent Claim 1
`Preamble:
`“A CMOS
`a.
`comprising:”
`Payne is directed to a CMOS semiconductor device. Ex.1003, ¶73; Ex.1005,
`
`semiconductor
`
`device
`
`Title, Abstract, 1:51-54 (“it is a primary object of the invention to provide a CMOS
`- 8 -
`
`

`

`
`
`structure and method of manufacture which requires little semiconductor space and
`
`therefore permits a high packing density.”), 1:5-15. Payne Figure 10 illustrates a “p-
`
`channel” (PMOS) transistor (with “P+” source/drain regions 21/22) adjacent to an
`
`“n-channel” (NMOS) transistor (with “N+” source/drain regions 23/24) of a CMOS
`
`semiconductor device. Id., 2:50-60, 5:18-34, 6:57-59.
`
`Ex.1005, FIG. 10.3
`
`
`
`
`
`Element [1.1]: “a surface layer;”
`b.
`Payne discloses, or at a minimum, renders obvious this element. Ex.1003,
`
`¶¶74-76. According to Patent Owner (“PO”), a “surface layer” is “a layer at the
`
`surface of the silicon” (or “a layer at the surface of the semiconductor device”)—
`
`
`3 All colors and colored annotations to figures added.
`
`- 9 -
`
`

`

`
`
`which PO annotated in blue below—“where the active region [(red)] is located.”
`
`Ex.1030, 6, 9, 12, 13; Ex.1033.
`
`
`
`Ex.1001, FIG. 5(b); Ex.1030, 7, 12.
`
`Payne satisfies element [1.1] to the same extent that Figure 5(b) meets it.
`
`Ex.1003, ¶¶74-75. Payne’s Figure 10 discloses a surface layer (blue) that matches
`
`the surface layer PO identified in Figure 5(b). Payne’s surface layer—a subset of
`
`what Payne refers to as “surface region 18”—is at the surface of silicon substrate 10,
`
`and “source and drain regions, 21 and 22 [(red)] of P+ conductivity” of Payne’s p-
`
`channel transistor (left) are located in it. Ex.1005, 2:50-60; 5:21-27, 6:57-59, FIG.
`
`1.
`
`- 10 -
`
`

`

`
`
`
`Ex.1005, FIG. 10. Payne likewise discloses another surface layer—a subset of
`
`“surface region 20”—containing “source and drain regions, 23 and 24, of N+
`
`conductivity” of Payne’s n-channel transistor (right). Id., 5:24-27, 6:57-59; Ex.1003,
`
`¶76.
`
`Ex.1005, FIG. 10.
`
`Element [1.2]: “a substrate;”
`c.
`Payne discloses this element. Ex.1003, ¶¶77-78. Payne’s Figure 10 illustrates
`
`a CMOS device “fabricated in a silicon semiconductor substrate [(grey)] 10 of ‘N-’
`
`
`
`- 11 -
`
`

`

`
`
`conductivity type which typically has a doping concentration of approximately 1-
`
`2x1014 ions/cm3[.]” Ex.1005, 1:60-62, 2:50-60.4
`
`Ex.1005, FIG. 10.
`
`Payne satisfies element [1.2] under PO’s proposed construction of “plain and
`
`ordinary meaning [i.e.] ‘an underlying layer.’” Ex.1033. Payne’s substrate also
`
`matches PO’s identification of the substrate (grey) in Figure 5(b) of the ’195 Patent.
`
`
`
`
`4 All emphases added unless otherwise noted.
`
`- 12 -
`
`

`

`
`
`
`
`Ex.1030, 6-7, 16-17 (well region and drift layer can be part of substrate); Ex.1001,
`
`FIG. 5(b). See also Ex.1005, 1:60-65, 2:50-60 (“the [CMOS] device is fabricated in
`
`a silicon semiconductor substrate, 10”), FIGS. 1, 10.
`
`d.
`
`Element [1.3]: “an active region including a source and
`a drain, disposed on one surface of said surface layer;”
`Payne discloses or renders obvious this element. Ex.1003, ¶¶79-83.
`
`According to PO, Figure 5(b) of the ’195 Patent depicts an active region (red)
`
`“disposed on one surface [(top surface)] of said surface layer”:
`
`- 13 -
`
`

`

`
`
`
`
`Ex.1001, FIG. 5(b); Ex.1030, 6-7, 11 (“[T]he ‘active region’ is part of the ‘surface
`
`layer’ … When the claim says the active region is ‘disposed on one surface of the
`
`surface layer,’ it means the active region is located on the ‘ceiling’ of the silicon
`
`inside the silicon.”) (emphasis in original), 12.
`
`Payne satisfies element [1.3] under PO’s interpretation. Ex.1003, ¶83. Payne’s
`
`Figure 10 below illustrates a “p-channel” transistor with source/drain regions 21/22
`
`(left), and an “n-channel” transistor with source/drain regions 23/24 (right). Ex.1005,
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`5:18-29, 1:5-19, 6:57-59. These source/drain regions are formed with “a surface
`
`impurity concentration of approximately 1019–1020 ions/cm3.” Ex.1005, 5:21-29,
`
`1:43-45. The channel region between them is part of the surface region, which has
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`an impurity concentration of “typically 0.5-5x1016 ions/cm3.” Ex.1005, 5:51-52,
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`4:31-39, 4:63-5:5. The source/drain regions of a transistor, together with the channel
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`region in between them, form an active region. Ex.1003 ¶¶81-82; Ex.1008B, 299
`
`(“The top surface of the [silicon substrate] body consists of active or transistor
`
`regions as well as passive or (field) regions. The active regions are those in which
`
`transistor action occurs; i.e., the channel and the heavily doped source and drain
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`regions.”), 300, FIG. 5-2, 382, FIG. 6-8(c), 387, FIG. 6-10; Ex.1008C, 525, FIG. 8-
`
`1(e). The active region (red) of each of Payne’s transistors is disposed on one surface
`
`(top surface) of a corresponding surface layer (blue), exactly as depicted in PO’s
`
`annotated Figure 5(b) above. Ex.1003, ¶83; §VIII.A.1.b.
`
`
`
`Ex.1005, FIG. 10.
`
`Payne satisfies element [1.3] under PO’s position that “active region” means
`
`“a doped silicon region at the surface of a semiconductor device (e.g., the source and
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`drain and silicon between them) where a transistor can be formed” (Ex.1033)
`
`because the active region of a MOS transistor is “[its] channel and [its] heavily doped
`
`source and drain regions,” highlighted below (red). Ex.1008B, 299; Ex.1003, ¶83.
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`
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`Ex.1008B, FIG. 5-1; id., 298-301, 374, FIGS. 5-2, 6-4.
`
`e.
`
`Element [1.4]: “a single drift layer disposed between
`the other surface of said surface layer and said
`substrate,
`said drift
`layer having a graded
`concentration of dopants extending between said
`surface layer and said substrate,”
`Payne discloses or renders obvious this element. Ex.1003, ¶¶84-93.
`
`Single drift layer (“SDL”) – In its claim construction brief, PO identified the
`
`SDL in tan in Figure 5(b). Ex.1030, 7. According to PO, the SDL (tan) is “disposed
`
`between ‘the other surface [(bottom surface)] of said surface layer [(blue)]’ and
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`[said] substrate [(grey)]”:
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`- 16 -
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`
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`Ex.1001, FIG. 5(b); Ex.1030, 7. The SDL in Figure 5(b) has a well region (green)
`
`disposed in it, forming a nested structure, as required by the claim (see element
`
`[1.6]), and as shown below:
`
`
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`Ex.1001, FIG. 5(b); Ex.1030 at 7; id., 11 (“the ‘well region’ is part of the ‘single
`
`
`
`drift layer.’”).
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`
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`Payne discloses a single drift layer (SDL) to the same extent the ’195 Patent’s
`
`Figure 5(b) does. Ex.1003, ¶¶85-87. In Payne’s Figure 10, the “first tub region” 15
`
`(tan) of Payne’s nested well structure—with shallow well (“surface region”) 18
`
`disposed in it—is an example of the claimed single drift layer. Id.; Ex.1005, 3:28-42
`
`(ion implantation for tub 15), 4:19-30 (thermal drive-in to achieve the desired depth
`
`for tub 15), 4:31-39, 5:7-17, 5:44-48, 5:48-50 (“In a typical device, the final depth
`
`of surface regions 18 and 20 would be approximately 1-2μ and the depth of the tub
`
`regions 15 and 17 would be typically 3-8μ.”). This SDL (tan) is “disposed between
`
`‘the other surface [(bottom surface)] of said surface layer [(blue)]’ and [said]
`
`substrate [(grey)]” under PO’s interpretation, and in exactly the same way as
`
`depicted in PO’s annotated Figure 5(b) above.
`
`Ex.1005, FIG. 10. Payne’s tub 17 (right), in which shallow well 20 is disposed, is
`
`likewise an SDL (tan) disposed between a surface layer (blue) and the substrate
`
`(grey). Ex.1005, 4:3-30, 4:63-5:17, 5:44-50; Ex.1003, ¶87; §VIII.A.1.b.
`
`
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`Payne meets all other claim requirements associated with the SDL to the same
`
`extent Figure 5(b) meets them. See below and elements [1.5]-[1.6]; Ex.1003, ¶¶88-
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`93. Notably, as detailed in element [1.5], each of Payne’s tubs 15/17 is a single drift
`
`layer (SDL) because it has a graded-dopant concentration that, according to PO,
`
`creates a unidirectional electric drift field that aids the movement of minority carriers
`
`in a single direction—from the surface layer to the substrate. Ex.1030, 7; Ex.1002,
`
`253-54, 289-290; §VIII.A.1.f.
`
`Graded-dopant concentration – The ’195 Patent admits that graded-dopant
`
`concentrations were known, Ex.1001, 2:13-15, FIG. 1 (“Prior Art”), and that it was
`
`known to grade the dopant concentration in CMOS devices to affect the movement
`
`of minority carriers. Id., 1:34-2:5, FIGS. 3(a)-3(d) (all “Prior art”). Payne’s SDL has
`
`a graded-dopant concentration extending between the surface layer and the substrate.
`
`Ex.1003 ¶89. Payne explains that the “impurity profile in both tubs [15/17] thereby
`
`has the general shape illustrated in FIG. 11” which exhibits “[t]he major advantage”
`
`of a “high-low implant profile.” Ex.1005, 2:38-41, 5:14-17, 5:56-57. Payne’s Figure
`
`11 (below right) illustrates the dopant concentration measured along the red dotted
`
`line in Figure 10 (below left), which starts at the bottom of the surface layer (blue)
`
`and extends to the substrate (grey). As shown below, Payne discloses a downward-
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`
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`sloping graded-dopant concentration in the SDL (tan) associated with Payne’s
`
`PMOS transistor (left).5
`
`
`
`Ex.1005, FIGS. 10-11. Dr. Banerjee has annotated Figure 11 to reflect exemplary
`
`(maximum) dopant concentrations at various depths disclosed in Payne: (1) 5x1016
`
`ions/cm3 at the surface of the shallow wells (depth 0µm), (2) 1016 ions/cm3 at a depth
`
`of ~2µm (boundary of deep and shallow wells), and (3) 2x1014 ions/cm3 at a depth
`
`of ~8µm (boundary of substrate and deep wells). Ex.1003, ¶¶90-91.
`
`
`5 Cf. Kingsford Prod. Co., LLC v. Creative Spark, LLC, No. IPR2016-01831, Paper
`
`32 at 32 (P.T.A.B. Mar. 9, 2018) (“Figures that are not drawn to scale may be relied
`
`upon to disclose qualitative relationships between measured quantities…”).
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`- 20 -
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`Ex.1005, FIG. 11. Indeed, Payne explains that “[t]he surface impurity concentration
`
`of the surface regions [18/20] is typically 0.5-5x1016 ions/cm3 and that [the surface
`
`impurity concentration] of the tub regions [15/17] is typically 1015-1016 ions/cm3,
`
`with the former concentration being at least twice as much as the latter over these
`
`ranges.” Id., 5:51-55. The concentration is lowest at the substrate, where it is “1-
`
`2x1014 ions/cm3.” Id., 2:56-59. Payne also explains that “the final depth of surface
`
`regions 18 and 20 would be approximately 1-2µ and the depth of tub regions 15 and
`
`17 would be typically 3-8µ.” Id., 5:48-50.
`
`While the above discusses the SDL associated with Payne’s PMOS transistor
`
`(left in Figure 10), Payne teaches that the SDL associated with Payne’s NMOS
`
`transistor (right) also has a downward-sloping graded-dopant concentration.
`
`Ex.1005, 5:14-17; Ex.1003, ¶¶91-93.
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`- 21 -
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`f.
`
`Element [1.5]: “said drift layer further having a first
`static unidirectional electric drift field to aid the
`movement of minority carriers from said surface layer
`to said substrate; and”
`Payne discloses or, at a minimum, renders obvious this element. Ex.1003,
`
`¶¶94-107. As shown below, Payne’s SDL (tan) has a downward-sloping graded-
`
`dopant concentration extending between the surface layer (blue) and the substrate
`
`(grey). §VIII.A.1.e.
`
`
`
`Ex.1005, FIGS. 10-11.
`
`Payne’s downward-sloping graded-dopant concentration aids the movement
`
`of minority carriers from the surface layer to the substrate to the same extent to which
`
`Applicant relied on the prior art and admitted to the Patent Office that such carrier
`
`movement would occur under the same scenario. Ex.1003, ¶¶95-99. During
`
`prosecution, Applicant represented to the Patent Office that a downward-sloping
`
`graded-dopant concentration was known in the prior art to create an “inherent ‘built-
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`- 22 -
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`
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`in’ unidirectional electric field” that moves carriers deep into the substrate (while an
`
`upward-sloping concentration, not at issue in Payne, would move those carriers in
`
`the opposite direction towards the surface):
`
`[T]he graded dopant concentration itself creates a ‘built-in’
`
`electrical field that forces the movement of carriers into a
`
`particular direction, whereby the ‘direction’ of the electrical
`
`field and the resulting direction of the carrier movement
`
`depends solely on the slope of the graded concentration of
`
`dopant.
`
`Ex.1002, 289-290 (underlining in original); Ex.1003, ¶¶95-96. Applicant further
`
`represented that “a unidirectional drift (electric) field necessarily affects all the
`
`present minority carriers in the same way…. Depending on the particular slope of
`
`the graded concentration of dopant, all minority carriers are either swept ‘down’ …
`
`or ‘up…’” Ex.1002, 289. Applicant cited Jastrzebski in support. Id., 290. In
`
`Jastrzebski, the graded-dopant concentration is “decreasing with depth” from the top
`
`surface 11 (purple) of the substrate 10, as shown in Figure 1b below. Ex.1010, 5:14-
`
`22. Jastrzebski teaches that this downward-sloping graded-dopant concentration
`
`creates an electric drift field that “force[s] most of the charge carriers … deep into
`
`the substrate[.]” Id., 5:14-22; id., 2:27-32 (“This is done by creating a field, such as
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`- 23 -
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`
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`a drift field, in the semiconductor substrate to sweep minority charge carriers…into
`
`the bulk [substrate], away from the electrode-bearing surface of the substrate.”).
`
`
`
`Ex.1010, FIGS. 1a-1b.
`
`Applicant made the same representation to the Patent Office regarding
`
`Kamins. Ex.1002, 237-238, 253-254. According to Applicant, Kamins’ Figure 3
`
`shows “two electrical fields with opposing directions” (highlighted in blue and
`
`yellow) that correspond to increasing and decreasing graded-dopant concentrations,
`
`respectively. Id., 237, 253 (citing Ex.1009, 3:6-13, FIGS. 2-3). Applicant explained
`
`that Kamins “show[s] minority carrie[r]s accelerated into the substrate.” Id., (citing
`
`Ex.1009, FIG. 2 and quoting Ex.1009, 3:6-13 (“carriers… accelerated… away from
`
`the surface… into the substrate”)). According to Applicant, the electric field
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`- 24 -
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`

`

`
`
`associated with the downward-sloping graded concentration at depth beyond ~10µm
`
`(red) causes “[minority] carriers created [in that region to be] … accelerated into
`
`the substrate ….” Id. (citing Ex.1009, 3:6-13, FIGS. 2-3); Ex.1030 at 24 (Kamin’s
`
`“bottom electric field [(yellow)] draws a minority carrier from the substrate to a
`
`deeper part of the substrate.”); Ex.1009, 2:67-3:14 (“The non-uniform dopant
`
`concentration in the substrate creates electric fields in the substrate indicated by
`
`arrows labeled ‘ε’ in FIGS. 2 and 3” such that “[minority] carriers created below the
`
`maximum dopant concentration are accelerated into the substrate.”), FIG. 2
`
`(referring to these carriers as “photogene