IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`CIRRUS LOGIC, INC.;
`OMNIVISION TECHNOLOGIES, INC.; AND
`AMS SENSORS USA INC.,
`Petitioner,
`
`
`v.
`
`GREENTHREAD, LLC,
`Patent Owner.
`
`
`Case No. IPR2024-00016
`Patent No. 10,510,842
`
`
`
`PETITION FOR INTER PARTES REVIEW OF U.S. PATENT NO.
`10,510,842
`
`UNDER 35 U.S.C. §§ 312 AND 37 C.F.R. § 42.104
`
`
`
`

`

`
`
`
`Exhibit
`1001
`1002
`1003
`1004
`1005
`
`1006
`
`1007
`1008A
`
`1008B
`
`1008C
`
`1008D
`
`1009
`
`1010
`1011
`
`1012
`
`1013
`
`1014
`1015
`1016
`
`1017
`1018
`1019
`1020
`1021
`
`
`
`LIST OF EXHIBITS
`
`Description
`U.S. Patent No. 10,510,842 to Rao (the “’842 Patent”)
`Prosecution History of the ’842 Patent
`Declaration of Sanjay Banerjee, PhD
`Curriculum Vitae of Sanjay Banerjee, PhD
`Publication Declaration of Sean O’Bryan for Maziasz
`(“O’Bryan Decl.”)
`U.S. Patent Application Publication No. 2003/0183856 to
`Wieczorek (“Wieczorek”)
`U.S. Patent No. 6,043,114 to Kawagoe, et al. (“Kawagoe”)
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol 1,
`Lattice Press (2000) (“Wolf.1”)
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol 2,
`Lattice Press (2000) (“Wolf.2”)
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol 3,
`Lattice Press (2000) (“Wolf.3”)
`Wolf and Tauber, Silicon Processing For The VLSI Era, Vol 4,
`Lattice Press (2000) (“Wolf.4”)
`Wang and Agrawal, Single Event Upset: An Embedded Tutorial,
`21st Intl Conf. on VLSI Design, IEEE 2008 (“Wang”)
`U.S. Patent No. 4,481,522 (“Jastrzebski”)
`Publication Declaration of Martin L. Knott for Rabaey (“Knott
`Decl.”)
`Publication Declaration of Alyssa G. Resnick for Wolf.1 and
`Wolf.2 (“Resnick Decl.”)
`Publication Declaration of Rachel J. Watters for Wolf.3 and
`Wolf.4 (“Watters Decl.”)
`U.S. Patent No. 6,163,877 (“Gupta”)
`U.S. Patent No. 6,534,805 (“Jin”)
`Excerpts from the Prosecution History of U.S. Patent No.
`8,421,195 (the “’195 Patent”)
`Patent Owner’s Proposed Constructions
`Blank
`Blank
`Patent Owner’s Responsive Claim Construction Brief
`Blank
`
`- i -
`
`

`

`
`
`Description
`Sze, Semiconductor Devices Physics and Technology, 2d Ed.,
`John Wiley & Sons (2002)
`Maziasz and Hayes, Layout Minimization of CMOS Cells,
`Kluwer Academic Publishers (1992) (“Maziasz”)
`U.S. District Courts – Case Statistics, obtained at
`https://www.uscourts.gov/statistics-reports/analysis-reports/
`federal-court-management-statistics, dated June 30, 2023
`Rabaey et al., Digital Integrated Circuits, A Design Perspective,
`Prentice Hall Electronics and VLSI Series (2003) (“Rabaey”)
`Gregory and Shafer, “Latch-Up In CMOS Integrated Circuits,”
`IEEE Transactions on Nuclear Science, Volume 20, Issue 6
`(1973)
`U.S. Patent Application Publication No. 2007/0045682 to Hong
`et al. (“Hong”)
`Excerpts from the Prosecution History of U.S. Patent
`Application No. 10/934,915 (the “’915 App.”)
`Excerpts from the Prosecution History of U.S. Patent No.
`9,190,502 (the “’502 Patent”)
`Excerpts from the Prosecution History of U.S. Patent
`Application No. 13/854,319 (the “’319 App.”)
`U.S. Patent No. 4,160,985 to Kamins et al. (“Kamins”)
`McGraw-Hill Dictionary of Scientific and Technical Terms
`(2003)
`Excerpts from the Prosecution History of U.S. Patent No.
`11,121,222 (the “’222 Patent”)
`U.S. Patent No. 9,647,070 to Rao (the “’070 Patent”)
`U.S. Patent Application Publication No. 2003/0030488 to
`Hueting et al. (“Hueting”)
`Publication Declaration of Sylvia Hall-Ellis for Wolf
`Law360 Article “Stays Pending IPR In Del. District Courts Are
`Here To Stay,” Kraning and Del Dotto, March 11, 2022.
`Dec. 21, 2022 Preliminary Claim Constructions in 6:22-CV-
`00105
`Oct. 31, 2022 Giapis Declaration, 6:22-CV-00105
`
`Exhibit
`1022
`
`1023
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`1032
`
`1033
`
`1034
`1035
`
`1036
`1037
`
`1038
`
`1039
`
`
`- ii -
`
`

`

`
`
`Table of Contents
`INTRODUCTION ...............................................................................1
`
`I.
`II. MANDATORY NOTICES ...................................................................1
`
`Real Party-in-Interest ..................................................................1
`Related Matters ..........................................................................1
`Counsel Service Information ........................................................3
`37 C.F.R. § 42.8(b)(4): Service Information ...................................5
`
`A.
`B.
`C.
`D.
`
`OVERVIEW OF CHALLENGE AND REQUESTED RELIEF .................5
`A.
`Prior Art Printed Publications .......................................................5
`B.
`Relief Requested.........................................................................6
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. §42.103...................................5
`IV. CERTIFICATION OF GROUNDS FOR STANDING..............................5
`V.
`VI. THE ’842 PATENT .............................................................................7
`VII. PERSON OF ORDINARY SKILL IN THE ART................................... 10
`VIII. CLAIM CONSTRUCTION ................................................................ 10
`IX. OVERVIEW OF THE PRIOR ART ..................................................... 11
`
`A. Kawagoe ................................................................................. 11
`B. Wieczorek ............................................................................... 13
`C. Wolf ....................................................................................... 15
`D. Gupta ...................................................................................... 15
`SPECIFIC GROUNDS FOR PETITION............................................... 15
`A. Ground I .................................................................................. 15
`1.
`Independent Claim 1 ........................................................ 15
`
`X.
`
`- iii -
`
`

`

`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`
`
`2.
`
`3.
`
`Claim 2: “The semiconductor device of claim 1, wherein the
`substrate is a p-type substrate.” .......................................... 36
`Claim 3: “The semiconductor device of claim 1, wherein the
`substrate is an n-type substrate.” ........................................ 36
`Claim 4: “The semiconductor device of claim 1, wherein the
`substrate has epitaxial silicon on top of a nonepitaxial
`substrate.” ....................................................................... 37
`Claim 5: “The semiconductor device of claim 1, wherein the
`first active region and second active region contain one of either
`p-channel and n-channel devices.” ..................................... 37
`Claim 6: “The semiconductor device of claim 1, wherein the
`first active region and second active region contain either p-
`channel or n-channel devices in n-wells or p-wells, respectively,
`and each well has a graded dopant.” ................................... 37
`Claim 7: “The semiconductor device of claim 1, wherein the
`first active region and second active region are each separated
`by at least one isolation region.” ........................................ 39
`Claim 8: “The semiconductor device of claim 1, wherein the
`graded dopant is fabricated with an ion implantation process.”
`...................................................................................... 39
`Independent Claim 9 ........................................................ 40
`9.
`10. Claim 10: “The semiconductor device of claim 9, wherein the
`substrate is a p-type substrate.” .......................................... 42
`11. Claim 11: “The semiconductor device of claim 1, wherein the
`substrate is an n-type substrate.” ........................................ 42
`12. Claim 12: “The semiconductor device of claim 9, wherein the
`substrate has epitaxial silicon on top of a nonepitaxial
`substrate.” ....................................................................... 43
`13. Claim 13: “The semiconductor device of claim 9, wherein the
`first active region and second active region contain at least one
`of either p-channel and n-channel devices.” ......................... 43
`
`- iv -
`
`

`

`
`
`14. Claim 14: “The semiconductor device of claim 9, wherein the
`first active region and second active region contain either p-
`channel or n-channel devices in n-wells or p-wells, respectively,
`and each well has a graded dopant.” ................................... 43
`15. Claim 15: “The semiconductor device of claim 9, wherein the
`first active region and second active region are each separated
`by at least one isolation region.” ........................................ 43
`16. Claim 16: “The semiconductor device of claim 9, wherein the
`graded dopant is fabricated with an ion implantation process.”
`...................................................................................... 43
`17. Claim 17: “The semiconductor device of claim 1, wherein the
`first and second active regions are formed adjacent the first
`surface of the substrate.” ................................................... 43
`18. Claim 18: “The semiconductor device of claim 1, wherein the
`transistors which can be formed in the first and second active
`regions are CMOS transistors requiring a source, a drain, a gate
`and a channel region.” ...................................................... 44
`B. Ground II ................................................................................. 45
`1.
`Independent Claim 1 ........................................................ 47
`2.
`Claim 2: “The semiconductor device of claim 1, wherein the
`substrate is a p-type substrate.” .......................................... 61
`Claim 3: “The semiconductor device of claim 1, wherein the
`substrate is an n-type substrate.” ........................................ 61
`Claim 5: “The semiconductor device of claim 1, wherein the
`first active region and second active region contain one of either
`p-channel and n-channel devices.” ..................................... 62
`Claim 6: “The semiconductor device of claim 1, wherein the
`first active region and second active region contain either p-
`channel or n-channel devices in n-wells or p-wells, respectively,
`and each well has a graded dopant.” ................................... 62
`
`3.
`
`4.
`
`5.
`
`- v -
`
`

`

`
`
`6.
`
`7.
`
`8.
`9.
`
`Claim 7: “The semiconductor device of claim 1, wherein the
`first active region and second active region are each separated
`by at least one isolation region.” ........................................ 63
`Claim 8: “The semiconductor device of claim 1, wherein the
`graded dopant is fabricated with an ion implantation process.”
`...................................................................................... 64
`Independent Claim 9 ........................................................ 64
`Claim 10: “The semiconductor device of claim 9, wherein the
`substrate is a p-type substrate.” .......................................... 67
`10. Claim 11: “The semiconductor device of claim 1, wherein the
`substrate is an n-type substrate.” ........................................ 67
`11. Claim 13: “The semiconductor device of claim 9, wherein the
`first active region and second active region contain at least one
`of either p-channel and n-channel devices.” ......................... 67
`12. Claim 14: “The semiconductor device of claim 9, wherein the
`first active region and second active region contain either p-
`channel or n-channel devices in n-wells or p-wells, respectively,
`and each well has a graded dopant.” ................................... 67
`13. Claim 15: “The semiconductor device of claim 9, wherein the
`first active region and second active region are each separated
`by at least one isolation region.” ........................................ 67
`14. Claim 16: “The semiconductor device of claim 9, wherein the
`graded dopant is fabricated with an ion implantation process.”
`...................................................................................... 67
`15. Claim 17: “The semiconductor device of claim 1, wherein the
`first and second active regions are formed adjacent the first
`surface of the substrate.” ................................................... 67
`16. Claim 18: “The semiconductor device of claim 1, wherein the
`transistors which can be formed in the first and second active
`regions are CMOS transistors requiring a source, a drain, a gate
`and a channel region.” ...................................................... 68
`C. GROUNDS III-IV .................................................................... 69
`
`- vi -
`
`

`

`XI. THE BOARD SHOULD INSTITUTE IPR............................................ 76
`
`
`
`A.
`B.
`C.
`
`35 U.S.C. § 314(a) .................................................................... 76
`35 U.S.C. § 325(d) .................................................................... 79
`Prior Terminated Petitions Do Not Warrant Denying Institution...... 81
`
`
`
`
`
`
`
`
`- vii -
`
`

`

`
`
`Cirrus Logic, Inc., OmniVision Technologies, Inc., and ams Sensors USA,
`
`Inc. (collectively, “Petitioner”) requests inter partes review (“IPR”) of claims 1-18
`
`(the “Challenged Claims”) of U.S. Patent No. 10,510,842 (Ex. 1001, “’842
`
`Patent”).
`
`I.
`
`
`INTRODUCTION
`The ’842 Patent is directed to a semiconductor device having a graded
`
`dopant concentration in an active region to aid carrier movement. Ex. 1001, 4:45-
`
`60 (claim 1), 5:14-29 (claim 9). This Petition demonstrates that the Challenged
`
`Claims are unpatentable as obvious.
`
`II. MANDATORY NOTICES
`A. Real Party-in-Interest
`Cirrus Logic, Inc., OmniVision Technologies, Inc., ams Sensors USA, Inc.,
`
`OSRAM GmbH, ams-OSRAM AG, and GlobalFoundries U.S., Inc. are the real
`
`parties-in-interest.
`
`B. Related Matters
`The ’842 Patent is the subject of the following active proceedings:
`
`• Greenthread, LLC v. Cirrus Logic, Inc., Civil Action No. 1:23-cv-00369
`
`in the Western District of Texas, filed March 31, 2023 (“Cirrus District
`
`Court Case”);
`
`• Greenthread, LLC v. OmniVision Technologies, Inc., Civil Action No.
`
`2:23-cv-00212 in the Eastern District of Texas, filed May 10, 2023
`
`- 1 -
`
`

`

`
`
`(“OmniVision District Court Case”);
`
`• Greenthread, LLC v. OSRAM GmbH et al., Civil Action No. 2:23-cv-
`
`00179 in the Eastern District of Texas, filed April 19, 2023 (“ams-
`
`OSRAM District Court Case”);
`
`• Greenthread, LLC v. ON Semiconductor Corporation and Semiconductor
`
`Components Industries, LLC, Civil Action No. 1:23-cv- 00443 in the
`
`District of Delaware, filed April 21, 2023;
`
`• Greenthread, LLC v Texas Instruments Incorporated, Civil Action No.
`
`2:23-cv-00157 in the Eastern District of Texas, filed April 6, 2023;
`
`• Greenthread, LLC v. Monolithic Power Systems, Inc., Civil Action No.
`
`1:23-cv-00579 in the District of Delaware, filed May 26, 2023; and
`
`• Semiconductor Components Industries, LLC v. Greenthread, LLC,
`
`IPR2023-01243, before the Patent Trial and Appeal Board, filed July 27,
`
`2023.
`
`
`
`The ’842 Patent was previously subject to the following proceedings, which
`
`are no longer pending:
`
`
`
`
`
`• Greenthread, LLC v. Intel Corporation, Dell Inc., and Dell Technologies
`
`Inc., Civil Action No. 6:22-cv-105 in the Western District of Texas
`
`(“Intel Litigation”), filed January 27, 2022;
`
`• Greenthread, LLC v. Intel Corporation, Civil Action No. 6:22-cv-01293
`
`- 2 -
`
`

`

`
`
`in the Western District of Texas, severed December 21, 2022, and
`
`transferred to District of Oregon as 3:22-cv-02001;
`
`• Greenthread, LLC v. Micron Technology, Inc. et al., Civil Action No.
`
`1:23-cv-00333 in the District of Delaware, filed March 24, 2023;
`
`• Greenthread, LLC v. Western Digital Corporation et al, Civil Action No.
`
`1:23-cv-00326 in the District of Delaware, filed March 24, 2023;
`
`• Intel Corporation v. Greenthread, LLC, IPR2023-00308, before the
`
`Patent Trial and Appeal Board, filed December 5, 2022;
`
`• Dell Technologies Inc. et al v. Greenthread, LLC, IPR2023-00506,
`
`before the Patent Trial and Appeal Board, filed January 27, 2023; and
`
`• Sony Group Corporation v. Greenthread, LLC, IPR2023-00376, before
`
`the Patent Trial and Appeal Board, filed December 17, 2022.
`
`C. Counsel Service Information
`Lead Counsel
`Scott Weidenfeller (No. 54,531)
`sweidenfeller@cov.com
`Covington & Burling LLP
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5923
`Facsimile: (202) 778-5923
`
`Backup Counsel
`Anupam Sharma (No. 55,609)
`asharma@cov.com
`Covington & Burling LLP
`3000 El Camino Real,
`5 Palo Alto Square,
`Palo Alto, CA 94306
`Telephone: (650) 632-4720
`Facsimile: (650) 632-4800
`
`Raj Paul (No. 64,492)
`rpaul@cov.com
`Covington & Burling LLP
`
`- 3 -
`
`

`

`
`
`One CityCenter,
`850 Tenth Street, NW
`Washington, DC 20001-4956
`Telephone: (202) 662-5740
`Facsimile: (202) 778-5923
`
`Bert Greene (No. 48,366)
`bgreene@duanemorris.com
`Andrew Liddell (No. 65,693)
`waliddell@duanemorris.com
`DUANE MORRIS LLP
`Las Cimas IV
`900 S. Capital of Texas Hwy., Suite
`300, Austin, TX 78746
`Telephone: (512) 277-2246
`Facsimile: (512)277-2301
`
`Daniel G. Nguyen (No. 42,933)
`dnguyen@lockelord.com
`Emma A. Bennett (No. 80,631)
`emma.bennett@lockelord.com
`LOCKE LORD LLP
`600 Travis St., Suite 2800
`Houston, Texas 77002
`Telephone: (713) 226-1200
`Facsimile: (214) 223-3717
`
`David H. Bluestone (No. 44,542)
`david.bluestone@bfkn.com
`Barack Ferrazzano Kirschbaum &
`Nagelberg LLP
`200 West Madison St., Suite 3900
`Chicago, Illinois 60606
`Telephone: (312) 984-3106
`Facsimile: (312) 984-3150
`
`
`- 4 -
`
`
`
`
`

`

`
`
`37 C.F.R. § 42.8(b)(4): Service Information
`D.
`Petitioner concurrently files a Power of Attorney, 37 C.F.R. §42.10(b), and
`
`consents to electronic service directed to the following email address: GT-Cirrus-
`
`IPR@cov.com.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. §42.103
`
`
`
`The Office is authorized to charge the fee set forth in 37 C.F.R. §42.15(a)(1)
`
`for this Petition to Deposit Account No. 60-3160. Review of 18 claims is
`
`requested. The undersigned further authorizes payment for any additional fees that
`
`may be due in connection with this Petition.
`
`IV. CERTIFICATION OF GROUNDS FOR STANDING
`Petitioner certifies under Rule 42.104(a) that the ’842 Patent is available for
`
`IPR and Petitioner is not barred or estopped from requesting IPR of the Challenged
`
`Claims on the grounds identified in this Petition.
`
`V. OVERVIEW OF CHALLENGE AND REQUESTED RELIEF
`Prior Art Printed Publications
`A.
`The ’842 Patent claims priority to September 3, 2004. Petitioner’s challenge
`
`is based on the following prior-art references, none of which were before the
`
`Patent Office during prosecution of the ’842 Patent:
`
`- 5 -
`
`

`

`
`
`• Kawagoe: U.S. Patent No. 6,043,114 to Kawagoe et al. (Ex. 1007) issued
`on March 28, 2000 and is prior art under 35 U.S.C. §102(b). 1
`
`• Wieczorek: U.S. Patent Application Publication 2003/0183856 to
`Wieczorek et al. (Ex. 1006) was filed on October 29, 2002 and published
`on October 2, 2003. Wieczorek is prior art under 35 U.S.C. §102(a) and
`§102(e).
`
`• Wolf: Wolf and Tauber, Silicon Processing for the VLSI Era, Lattice
`Press (2000) (Exs. 1008A-D), was published and publicly available no
`later than 2002, and is prior art under 35 U.S.C. §102(b). Exs. 1012-
`1013; Ex. 1036. 2
`
`• Gupta: U.S. Patent No. 6,163,877 to Gupta (Ex. 1014) issued on
`December 19, 2000 and is prior art under 35 U.S.C. §102(b).
`
`B. Relief Requested
`The specific grounds of the challenge are set forth below and are supported
`
`by the declaration of Dr. Banerjee (Ex. 1003).
`
`Ground
`
`I
`
`II
`
`Basis
`
`§103
`
`§103
`
`Challenged Claims
`
`Reference(s)
`
`1-18
`
`Kawagoe
`
`1-3, 5-11, 13-18
`
`Wieczorek, Wolf
`
`
`1 Cites to 35 U.S.C. §§102 and 103 are to the pre-America Invents Act (pre-AIA).
`
`2 Petitioner is relying on its own retained independent librarian expert, Dr. Sylvia
`
`Hall-Ellis, to verify the public availability of the Wolf reference.
`
`- 6 -
`
`

`

`III
`
`IV
`
`§103
`
`§103
`
`
`
`1-18
`
`1-3, 5-11, 13-18
`
`Kawagoe, Gupta
`
`Wieczorek, Wolf,
`Gupta
`
`
`
`VI. THE ’842 PATENT
`The ’842 Patent is directed to “grading the dopant concentration” in certain
`
`regions of a semiconductor device. Ex. 1001, Abstract. The Challenged Claims
`
`specifically claim that an active region of a semiconductor device has a “graded
`
`dopant concentration to aid carrier movement.” Id., Cl. 1.
`
`The ’842 Patent admits that graded dopant concentrations were known. For
`
`example, the graded dopant concentration “B” (green) in Figure 1 below is
`
`described as one of “the two most popular” doping profiles used in prior art bipolar
`
`transistors, in contrast to the uniform doping profile “A” (red). Ex. 1001, 2:35-38.
`
`- 7 -
`
`

`

`
`
`
`Ex. 1001, FIG. 1 (“Prior Art”). 3 The ’842 Patent further admits that it was known
`
`to grade the dopant concentration in well regions of CMOS devices to affect the
`
`movement of carriers, but alleges, without support, that prior attempts
`
`demonstrated “little success” in “improv[ing] soft error immunity in SRAMs and
`
`visual quality in imaging circuits.” Id., 2:14-27.
`
`The entire description of graded dopant concentration and purported carrier
`
`movement in CMOS devices is confined to two short paragraphs of the
`
`specification and associated Figures 5A-5C. Ex. 1001, 3:44-4:25, FIGS. 5A-5C.
`
`
`3 All colors and colored annotations to figures added.
`
`- 8 -
`
`

`

`
`
`These paragraphs provide no guidance on how to grade a dopant concentration to
`
`“aid” carrier movement or the nature of such “aiding.” The specification, in fact,
`
`uses “graded” dopant broadly to describe a non-uniform dopant concentration. Id.
`
`at 4:10-13. The specification also does not describe grading in an active region of a
`
`CMOS device to move carriers to the substrate as claimed. Ex. 1001, Cl. 1.
`
`Instead, the specification only discusses grading the channel region of an active
`
`region “to accelerate majority carriers towards the drain.” Ex. 1001, 4:5-7. 4
`
`The Challenged Claims issued after two office actions rejecting the pending
`
`claims over Hong. Ex. 1002, 66-69, 109-113. According to the Examiner, the
`
`claims were eventually allowed because Hong does not teach two separate “active”
`
`regions within which transistors can be formed “in conjunction with ‘at least one
`
`graded dopant concentration to aid carrier movement from the first surface to the
`
`second surface of the substrate.’” Ex. 1002, 154-155.
`
`Hong is in fact not prior art because it was filed on August 31, 2005, long
`
`after the claimed priority date of the ’842 Patent. Ex. 1027. None of the prior art
`
`relied on in this Petition was cited or considered by the Examiner.
`
`
`4 Petitioner reserves the right to present invalidity arguments based on Section 112
`
`in the District Court Cases.
`
`- 9 -
`
`

`

`
`
`VII. PERSON OF ORDINARY SKILL IN THE ART
`
`A person of ordinary skill in the art (“POSITA”) of the subject matter of the
`
`’842 Patent would have had a Bachelor’s degree in electrical engineering, material
`
`science, applied physics, or a related field, and four years of experience in
`
`semiconductor design and manufacturing or equivalent work experience. Ex. 1003,
`
`¶¶47-50. Additional education might compensate for a deficiency in experience,
`
`and vice-versa. Id. Notably, in the Intel Litigation, Patent Owner agreed with this
`
`characterization of a POSITA. Ex. 1039, ¶13.
`
`VIII. CLAIM CONSTRUCTION
`Claims in an IPR are construed under the principles set forth in Phillips v.
`
`AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). 37 C.F.R. §42.100(b).
`
`Petitioner is aware that Patent Owner took positions on the meaning of certain
`
`claim terms, which are listed below. See Exs. 1017, 1020. 5
`
`Claim Term
`
`“substrate”
`
`“active region”
`
`Patent Owner’s Proposed
`Construction
`Plain and ordinary meaning, where
`the plain and ordinary meaning is an
`“underlying layer”
`Plain and ordinary meaning (“a doped
`silicon region at the surface of a
`semiconductor device where a
`transistor can be formed”)
`
`
`5 As to the “active region” terms, Patent Owner’s position is reflected in its claim
`
`construction briefing. See Ex. 1020, 28, 40.
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`“to aid carrier movement from . . .
`[to/towards] . . .”
`“active region . . . within which
`transistors can be formed”
`
`
`
`
`
`Plain and ordinary meaning
`
`Plain and ordinary meaning (“a doped
`silicon region at the surface of a
`semiconductor device where a
`transistor can be formed”)
`
`Petitioner is further aware that, in the Intel Litigation, the Court provided its
`
`“preliminary constructions” in advance of the claim construction hearing, in which
`
`the Court offered a “preliminary construction” of plain and ordinary meaning as to
`
`each of the above-listed terms. See Ex. 1038. Petitioner does not believe any terms
`
`need be construed to resolve the issues presented in this Petition, and Petitioner
`
`takes no position regarding claim construction at this time. The Challenged Claims
`
`are unpatentable under either their plain and ordinary meaning, or under Patent
`
`Owner’s proposed constructions (except for the term “active region ... within
`
`which transistors can be formed,” which is addressed in Sections X.A.1.c-d,
`
`X.A.9.c-d, X.B.1.c-d, X.B.8.c-d, and X.C below). Ex. 1003, ¶54. Petitioner
`
`reserves the right to respond to any purported claim constructions that Patent
`
`Owner raises.
`
`IX.
`
`
`
` OVERVIEW OF THE PRIOR ART
`A. Kawagoe
`Kawagoe describes CMOS devices fabricated using twin-well CMOS
`
`technology and an epitaxial substrate, whereby the epitaxial layer can be doped at
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`the same level or at a lower level than the substrate body. Ex. 1007, 3:32-38, 6:65-
`
`7:3, 8:40-53, 15:13-17, 15:26-40. Kawagoe’s figure below depicts a twin-well
`
`CMOS structure. Ex. 1007, 15:26-40, 18:18-23.
`
`
`Id., FIG. 23. Kawagoe further teaches that the well regions have a graded dopant
`
`concentration that decreases with depth, as illustrated below in Figure 17 (which
`
`corresponds to Figure 23). Id., 14:46-55, 15:62-16:40 (“p-well 6p and n-well 6n
`
`have their impurity concentrations gradually lowered in the depthwise
`
`direction ...”).6
`
`
`6 All emphases added unless otherwise noted.
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`Id., FIGS. 17, 23. The graded dopant concentration reduces soft errors by sweeping
`
`unwanted carriers into the substrate body. Id., 16:2-11 (“electrons produced by the
`
`α-ray are attracted to the substrate body 2S by that concentration gradient ... so
`
`that the soft errors can be reduced.”).
`
`B. Wieczorek
`This Petition relies on Wieczorek’s description of conventional prior art
`
`
`
`CMOS devices, such as the twin-well CMOS device illustrated below in Figure 1b.
`
`Ex. 1006, [0007], [0012], [0020]-[0021].
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`
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`Id., FIG. 1b. Wieczorek explains that graded dopant concentrations in prior art
`
`CMOS devices peak at the surface of the substrate and decrease with depth, as
`
`shown below. Id., [0004], [0007]-[0013], [0020]-[0021] (the Fig. 2b profile
`
`(below, right) corresponds to the Fig. 1b semiconductor device (below, left)).
`
`Id., FIGS. 1b, 2b.
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`
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`C. Wolf
`Wolf is a four-volume textbook directed to semiconductor devices, with
`
`
`
`particular focus on CMOS devices. Exs. 1008A-D. This textbook provides helpful
`
`context regarding the disclosures of Kawagoe and Wieczorek.
`
`D. Gupta
`Gupta is directed to circuit layout of CMOS devices. Ex. 1014, 1:7-10. As
`
`
`
`Gupta explains, “[c]onservation of semiconductor area is a primary goal in
`
`semiconductor chip development” and a common technique to conserve area is “by
`
`placing transistors so as to share diffusion area.” Id., 1:32-54, 2:17-21.
`
`X.
`
`
`
`SPECIFIC GROUNDS FOR PETITION
`A. Ground I
`Independent Claim 1
`1.
`Preamble: “A semiconductor device, comprising:”
`a)
`Kawagoe is directed to a “semiconductor integrated circuit device” and
`
`process for making the same. Ex. 1007, Title, 1:13-23, 14:46-67, FIGS. 16-17, 23.
`
`The present Ground I primarily focuses on the twin-well CMOS device in Figure
`
`23 (Embodiment 4), fabricated on a uniformly-doped epitaxial substrate, taught in
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`Embodiment 1. 7 See X.A.1.b.
`
`
`
`Ex. 1007, FIG. 23.
`
`
`
`b) Element [1.1]: “a substrate of a first doping type at a
`first doping level having first and second surfaces;”
`Kawagoe discloses a substrate (“semiconductor substrate 2”) of a first
`
`doping type (p-type) having a silicon “epitaxial layer 2E [] doped with a p-type
`
`impurity such as boron” formed over non-epitaxial “semiconductor substrate body
`
`2S [also] doped with a p-type impurity such as boron....” Ex. 1007, 14:61-15:12,
`
`6:50-7:3. The substrate (orange) has top (“first surface”) and bottom (“second
`
`
`7 Figures 16-17 and 23 are all directed to Kawagoe’s Embodiment 4. Ex. 1007,
`
`14:46-60. Figure 23 shows the same twin-well CMOS structures depicted in Figure
`
`16 without the metal layers that are not recited in the Challenged Claims. Ex. 1007,
`
`17:10-18:38; Ex. 1003, ¶66.
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`surface”) surfaces, as indicated below. Ex. 1003, ¶67.
`
`
`
`Id., FIG. 23.
`
`Kawagoe satisfies element [1.1] under Patent Owner’s plain meaning
`
`construction. Section VIII; Ex. 1007, 6:50-56, 14:61-67, 17:10-18:38; Ex. 1003,
`
`¶68.
`
`Ex. 1007, FIG. 20.
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`
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`As detailed below, Ground I relies on a uniformly-doped epitaxial substrate
`
`in which silicon epitaxial layer 2E of the substrate is doped at the same level as
`
`silicon substrate body 2S, so that the entire substrate in Figure 20 is “at a first
`
`doping level” as claimed. Ex. 1007, 6:60-7:3; Ex. 1003, ¶69.
`
`“at a first doping level” - Kawagoe teaches an epitaxial substrate (2S+2E),
`
`illustrated in Figure 20, in which the non-epitaxial silicon substrate body (2S) is
`
`either doped at the same or higher level compared to the epitaxial silicon layer
`
`(2E). For example, Embodiment 1 describes a uniformly-doped epitaxial substrate
`
`in which the “epitaxial layer 2E is doped ... in a concentration equal to the
`
`[concentration] of the semiconductor substrate body 2S, e.g., 1.3x1015 atoms/cm3.”
`
`Ex. 1007, 6:60-7:3; id., Abstract (describing “an epitaxial layer which contains an
`
`impurity of the same conduction type [and at] ... the same concentration” as the
`
`bulk substrate), 2:57-3:9 (same). This uniformly-doped epitaxial substrate is
`
`Kawagoe’s benchmark substrate repeatedly discussed in other embodiments,
`
`including Embodiment 4. Ex. 1007, 12:64-65, 13:12-15, 13:66-67, 14:18-20, 15:7-
`
`25. Embodiment 4 introduces the option of a latchup-resistant substrate in which
`
`“the impurity concentration of the semiconductor substrate body 2S is made higher
`
`than that of the epitaxial layer 2E ... to improve the resistance to the latchup.” Ex.
`
`1007, 15:13-17; see also id., 3:60-63 (there is a high “degree of freedom for setting
`
`the impurity concentration” in the disclosed semiconductor substrate so “as to
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`facilitate the control of the formation”). Kawagoe teaches that the “substrate body
`
`2S is doped with a p-type impurity such as boron at a concentration of about 1.5 x
`
`1015 atoms/cm3.” Id., 14:64-67; Ex. 1003, ¶71.
`
`“[A] POSITA would have understood that Kawagoe teaches forming Figure
`
`23’s twin-well CMOS device (Embodiment 4) on either a uniformly-doped
`
`epitaxial substrate described in Embodiment 1 or the optional latchup-resistant
`
`substrate described in Embodiment 4.” Ex. 1003, ¶72. Specifically, a POSITA
`
`would have appreciated that Kawagoe teaches that a tradeoff between improving
`
`latchup resistance and minimizing manufacturing cost. This understanding is
`
`consistent with the teachings of Wolf. See Ex. 1008C, 524 (“There are many trade-
`
`offs involved in the optimization of a CMOS process” including “fabrication cost[]
`
`and susceptibility to latchup.”); Ex. 1003, ¶72.
`
`Kawagoe emphasizes the benefits of Embodiment 1’s uniformly-doped
`
`epitaxial substrate and explains that the substrate used in Embodiment 4 is formed
`
`“as in the foregoing embodiment 1 so that ... the cost of the semiconductor
`
`substrate 2 is lowered to about one half.” Ex. 1007, 15:7-25. Additionally, a
`
`POSITA would have been motivated to use a uniformly-doped epitaxial substrate
`
`(disclosed for Embodiment 1) to form Figure 23’s twin-well CMOS device
`
`because this substrate provides “excellent film quality” that “drastically reduce[s]
`
`the defect densities of the gate insulating films” and “improve[s] the [device’s]
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`performance, reliability and