Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 1 of 57
`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 1 of 57
`
`EXHIBIT 1
`EXHIBIT 1
`
`CIRRUS EX. 1039 - 1/57
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`CIRRUS EX. 1039 - 1/57
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`

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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 2 of 57
`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`Greenthread, LLC
`
`Plaintiff,
`
`Civil Action No. 6:22-cv-105-ADA
`
`v.
`
`Intel Corporation;
`Dell Inc.; and
`Dell Technologies Inc.
`
`Defendants.
`
`JURY TRIAL DEMANDED
`
`DECLARATION OF KONSTANTINOS P. GIAPIS IN SUPPORT OF
`GREENTHREAD’S RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
`CIRRUS EX. 1039 - 2/57
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`

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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 3 of 57
`
`TABLE OF CONTENTS
`
`TABLE OF EXHIBITS ................................................................................................................. iii
`
`DISPUTED CLAIM CONSTRUCTIONS .................................................................................... iv
`
`I.
`
`
`TT.
`
`
`TTL
`
`
`IV.
`
`
`V.
`
`
`INTRODUCTION ...............................................................................................................1
`
`BACKGROUND AND QUALIFICATIONS .....................................................................1
`
`SCOPE OF ASSIGNMENT AND MATERIALS CONSIDERED ....................................2
`
`PERSON OF ORDINARY SKILL IN THE ART (POSITA) .............................................3
`
`RELEVANT
`THE
`BACKGROUND OF
`GENERAL
`TECHNOLOGY AND THE PATENTS-IN-SUIT .............................................................5
`
`A.
`
`B.
`
`C.
`
`D.
`
`Dopants ....................................................................................................................5
`
`Overview of Dr. Rao’s Inventions ...........................................................................6
`
`Exemplary Claim 1 of the ’195 Patent ...................................................................10
`
`Exemplary Claim 1 of the ’842 Patent ...................................................................14
`
`VI.
`
`
`LEGAL
`CONSTRUCTION
`CLAIM
`APPLICABLE
`STANDARDS....................................................................................................................15
`
`VII.
` MEANING OF CLAIM TERMS TO PERSONS OF ORDINARY
`SKILL ................................................................................................................................16
`
`A.
`
`Claim Terms Found in Exemplary Claim 195:1 ....................................................17
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`“surface layer” terms (195:1; 502:7; 222:44) ............................................17
`
`“substrate” (195:1; 502:7; 842:1, 9; 481:1, 20; 222:1,
`21, 39, 41, 42, 44; 014:1, 21) .....................................................................23
`
`“active region” (195:1; 502:7; 842:1, 9; 481:1, 20;
`222:1, 21, 39, 41, 42, 44; 014:1, 21) ..........................................................25
`
`“unidirectional electric drift field” terms (195:1;
`502:7; 222:44) ............................................................................................26
`
`“to aid the movement” terms (195:1; 502:7; 842:1, 9;
`481:1, 20; 222:1, 21, 39, 41, 42, 44; 014:1, 21) .........................................31
`
`“well region” (195:1; 502:7; 842:1, 9; 481:1, 20;
`222:1, 21, 39, 41, 42, 44; 014:1, 21) ..........................................................33
`
`i
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 4 of 57
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`B.
`
`Claim Term Found in Exemplary Claim 842:1 .....................................................34
`
`7.
`
`“active region…within which transistors can be
`formed” (842:1, 9; 481:1, 20; 222:1, 21, 39, 41, 42;
`014:1, 21) ...................................................................................................34
`
`VIII.
` CONCLUSION ..................................................................................................................38
`
`IX.
`
`
`
`
`
`APPENDIX A (CV) ...........................................................................................................40
`
`
`
`ii
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 5 of 57
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`
`
`Exhibit
`
`TABLE OF EXHIBITS
`
`Description
`
`1
`
`2
`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`Intentionally omitted
`
`U.S. Patent No. 8,421,195 to G.R. Mohan Rao (“195 patent”) (GREENTHREAD-
`WDTX-000027–40)
`
`U.S. Patent No. 10,510,842 to G.R. Mohan Rao (“842 patent”) (GREENTHREAD-
`WDTX-000070–84)
`
`Excerpts from Chen, J. Y., CMOS Devices and Technology for VLSI, Prentice-Hall
`(1990) (GREENTHREAD-WDTX-007426–007682) (“Chen”)
`
`Greenthread, LLC v. Samsung Elecs. Co., Ltd., No. 2:19-cv-00147-JRG, Dkt. 67
`(Claim Construction Memorandum Opinion and Order), E.D. Tex. Apr. 20, 2020
`(GREENTHEAD-WDTX-002761–002792) (“EDTX Markman Order”)
`
`Samsung Elecs. Co., Ltd. v. Greenthread, LLC, IPR2020-00289, Ex. 1003 (Apr. 14,
`2020) (GREENTHREAD-WDTX-003869–003959) (“Dr. Smith declaration”)
`
`The American Heritage Dictionary of the English Language, Third Edition (2002),
`at 1792 (defining “substrate”) (GREENTHREAD-WDTX-007794–007797)
`
`Excerpts from Webster’s Third New International Dictionary of the English
`Language Unabridged, Merriam-Webster, Inc. (1992) (GREENTHREAD-WDTX-
`002826 – GREENTHREAD-WDTX–002834, GREENTHREAD-WDTX-007793)
`
`Excerpts from Baker, R. J., CMOS Circuit Design, Layout, and Simulation, IEEE
`(1998) (GREENTHREAD-WDTX-002674–002715) (“Baker”)
`
`Defendants’ Preliminary Claim Constructions, No. 6:22-cv-105-ADA (W.D. Tex.)
`(served Sept. 19, 2022)
`
`File History of U.S. Patent No. 10,510,842 (“842 file history”) (GREENTHREAD-
`WDTX-001059–1246)
`
`Excerpts from Howe, R. T., Microelectronics: An Integrated Approach, Prentice-
`Hall (1997) (“Howe”) (GREENTHREAD-WDTX-002793–2813)
`
`Excerpts from Wolf S., Silicon Processing for the VLSI Era Volume 2: Process
`Integration, Lattice Press (1990)
`
`Excerpts from Wolf S., Silicon Processing for the VLSI Era Volume 3: The
`Submicron MOSFET, Lattice Press (1995) (GREENTHREAD-WDTX-002877–
`2883)
`
`
`
`
`
`iii
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 6 of 57
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`DISPUTED CLAIM CONSTRUCTIONS
`
`# Claim(s)1
`
`Terms
`
`Greenthread
`
`Defendants
`
`1
`
`195:1
`502:7
`222:44
`
`2
`
`3
`
`4
`
`195:1
`502:7
`842:1, 9
`481:1, 20
`222:1, 21,
`39,
`41, 42, 44
`014:1, 21
`
`195:1
`502:7
`842:1, 9
`481:1, 20
`222:1, 21,
`39,
`41, 42, 44
`014:1, 21
`
`195:1
`502:7
`222:44
`
`“surface layer” and
`related terms (“an
`active region . . .
`disposed on one
`surface of said
`surface layer” / “a
`single drift layer
`disposed between the
`other surface of said
`surface layer and
`[said/the] substrate”)
`
`“substrate”
`
`Indefinite
`
`Plain and
`ordinary meaning,
`where the plain
`and ordinary
`meaning is “a
`layer at the
`surface”
`
`Plain and
`ordinary meaning,
`where the plain
`and ordinary
`meaning is an
`“underlying
`layer”
`
`“the initial
`material within
`which or on
`which the
`semiconductor
`device is
`fabricated”
`
`“active region”
`
`Plain and
`ordinary meaning
`
`“region that forms
`the current path
`of a device”
`
`“said [drift layer
`further/well region
`…] having a
`[first/second] static
`unidirectional electric
`drift field”
`
`Plain and
`ordinary meaning
`
`
`
`“said [drift layer
`further/well
`region …] having
`a
`[first/second]
`static electric drift
`field
`that
`is
`unidirectional
`over
`the
`[drift
`layer/well region”
`
`“said [drift layer
`further/well region]
`having a graded
`
`1 The notation “195:1” (for example) denotes claim 1 of the ’195 patent. Patent numbers are
`specified below in Section I.
`
`“said [drift layer
`further/well
`region] having a
`
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 7 of 57
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`concentration of
`dopants generating a
`[first/second] static
`unidirectional electric
`drift field”
`
`“to aid the movement
`of minority carriers
`from ... to …”
`
`Plain and
`ordinary meaning
`
`
`
`“to aid carrier
`movement from ...
`[to/towards]”
`
`“well region”
`
`Plain and
`ordinary meaning,
`where portions of
`a well are not
`well regions.
`
`graded
`concentration of
`dopants
`generating a
`[first/second]
`static electric drift
`field that is
`unidirectional
`over the [drift
`layer/well
`region]”
`
`Indefinite
`
`Alternative
`construction: “to
`sweep the
`minority carriers
`from … to …
`
`
`
`Indefinite
`
`Alternative
`construction: “to
`sweep the carriers
`from …
`[to/towards] …
`
`“A well, whether
`formed by single
`or multiple
`implants.
`Portions of a well
`are not well
`regions.”
`
`“active region …
`within which
`transistors can be
`formed”
`
`Plain and
`ordinary meaning
`
`Indefinite
`
`5
`
`6
`
`7
`
`195:1
`502:7
`842:1, 9
`481:1, 20
`222:1, 21,
`39,
`41, 42, 44
`014:1, 21
`
`195:1
`502:7
`842:1, 9
`481:1, 20
`222:1, 21,
`39,
`41, 42, 44
`014:1, 21
`
`842:1, 9
`481:1, 20
`222:1, 21,
`39,
`41, 42
`014:1, 21
`
`
`
`v
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`CIRRUS EX. 1039 - 7/57
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 8 of 57
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`
`
`DECLARATION OF KONSTANTINOS P. GIAPIS
`
`I, Konstantinos P. Giapis, do hereby declare as follows:
`
`I.
`
`
`INTRODUCTION
`
`1.
`
`
`I have been retained on behalf of Greenthread, LLC (“Greenthread”), and its
`
`counsel, McKool Smith, P.C., as an expert in this proceeding, in which I understand Intel
`
`Corporation, Dell Inc., and Dell Technologies Inc. are the defendants (“Defendants”). I am
`
`personally knowledgeable about the matters stated herein and am competent to make this
`
`declaration.
`
`2.
`
`
`I understand that Greenthread will submit this Declaration in connection with a
`
`brief supporting its proposed construction of various terms in certain claims of U.S. Patent Nos.
`
`8,421,195 (“the ’195 patent); 9,190,502 (“the ’502 patent”); 10,510,842 (“the ’842 patent”);
`
`10,734,481 (“the ’481 patent”); 11,121,222 (“the ’222 patent”); and 11,316,014 (“the ’014 patent”)
`
`(collectively, “the Patents-in-Suit” or “the Asserted Patents” or “Dr. Rao’s patents”).
`
`3.
`
`
`I receive compensation at an hourly rate of $700 per hour for my time working on
`
`technical consulting in this matter, plus expenses. I have no financial interest in Greenthread or in
`
`the patents involved in this litigation, and my compensation is not dependent on the outcome of
`
`this litigation. The conclusions I present are due to my own judgment.
`
`II.
`
`
`BACKGROUND AND QUALIFICATIONS
`4.
`
`
`I am a Professor of Chemical Engineering at the California Institute of Technology
`
`(“Caltech”). I have held that position since 1992. My research relates to processing of
`
`semiconductors, dielectrics, and metals, as performed in the fabrication of semiconductor devices,
`
`including microprocessors and digital memories. In particular, my work has focused upon
`
`patterning layers of electronic materials to fabricate sub-micron features such as transistor gates,
`
`vias, and metal lines found in VLSI circuits. I have also conducted modeling and simulations of
`
`the evolution of poly-silicon and metal gate profiles subjected to plasma etching and studied their
`
`charging interactions with plasmas. Since the start of my graduate career in 1985, I have
`
`
`
`1
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 9 of 57
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`accumulated over 35 years of experience on semiconductor materials, devices, and their
`
`processing.
`
`5.
`
`
`In my professorial duties at Caltech, I have developed and taught new
`
`undergraduate and graduate level courses on semiconductor device physics and their processing.
`
`These innovative courses combined solid state physics and electronic materials processing
`
`technologies with the more traditional chemical engineering subjects of transport phenomena and
`
`chemical thermodynamics. The courses have prepared several generations of students for
`
`successful careers in the semiconductor industry.
`
`6.
`
`
`During my research career, I have authored or co-authored 98 peer-reviewed
`
`papers, 12 refereed conference proceedings, and two book chapters. Most of my publications
`
`relate to semiconductor device processing. My papers on charging damage of high-density
`
`integrated devices such as microprocessors, and digital memories are highly cited. I have also
`
`been granted 13 patents.
`
`7.
`
`
`My curriculum vitae is provided as Appendix A to this Declaration
`
`III.
`
`
`SCOPE OF ASSIGNMENT AND MATERIALS CONSIDERED
`
`8.
`
`
`I have been retained by Greenthread to provide an explanation to the Court
`
`regarding the inventions described in the Patents-In-Suit. I understand that the patents have been
`
`asserted by Greenthread against Defendants in this proceeding. I have also been retained to provide
`
`my opinion regarding the meaning of certain terms to persons of ordinary skill in the field of the
`
`inventions and to address certain issues of claim indefiniteness alleged by the Defendants.
`
`9.
`
`
`In preparing this Declaration, I am relying on my own knowledge and expertise as
`
`well as the following documents:
`
` The Patents-In-Suit:
`
`o U.S. Patent No. 8,421,195 to Dr. G.R. Mohan Rao (“the ’195 patent);
`
`o U.S. Patent No. 9,190,502 to Dr. G.R. Mohan Rao (“the ’502 patent”);
`
`o U.S. Patent No. 10,510,842 to Dr. G.R. Mohan Rao (“the ’842 patent”);
`
`
`
`2
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 10 of 57
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`o U.S. Patent No. 10,734,481 to Dr. G.R. Mohan Rao (“the ’481 patent”);
`
`o U.S. Patent No. 11,121,222 to Dr. G.R. Mohan Rao (“the ’222 patent”); and
`
`o U.S. Patent No. 11,316,014 to Dr. G.R. Mohan Rao (“the ’014 patent”);
`
` Prosecution histories for the Patents-In-Suit, which I understand constitute the
`
`exchange of correspondence between the Patent Office and the applicant;
`
` Petitioner Samsung Electronics Co., Ltd. (“Samsung”)’s petitions for inter partes
`
`review, Nos. IPR2021-00289 and -00290 regarding the ’195 and ’502 patents, the
`
`declarations of Dr. Bruce Smith submitted in support thereof, and Greenthread’s
`
`preliminary responses in those IPRs;
`
` Defendants’ Opening Claim Construction Brief (Dkt. 82)2 and exhibits to that brief
`
` Greenthread’s extrinsic evidence disclosure statement (September 26, 2022),
`
`Greenthread’s supplemental extrinsic evidence disclosure statement (October 6,
`
`2022), Defendants’ extrinsic evidence disclosure statement (September 26, 2022),
`
`Defendants’ supplemental extrinsic evidence disclosure statement (October 10,
`
`2022), and extrinsic evidence cited in those statements;
`
` The exhibits listed in the Table of Exhibits at the beginning of this Declaration; and
`
` The other references cited within this Declaration.
`
`IV.
`
`
`PERSON OF ORDINARY SKILL IN THE ART (POSITA)
`
`10.
` When interpreting a patent, I understand that it is important to view the disclosure
`
`and claims of that patent from the level of ordinary skill in the relevant art at the time of the
`
`invention. My opinion of the level of ordinary skill in the art with regard to the Patents-in-Suit is
`
`based on my personal experience working and teaching in the field of semiconductor processing,
`
`including work with semiconductor technologies, my knowledge of the background and education
`
`
`2 In this Declaration, I cite to certain documents as “Dkt. XXX” where XXX indicates what I am
`informed is the docket number of such documents on this case’s court docket. Regarding such
`documents, my cites to specific page numbers refer to the page numbers stamped in blue in the
`header at the top right of each page in the format “Page __ of __.”
`
`
`
`3
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 11 of 57
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`of colleagues and others working in that general field as of and for several years prior to the 2002
`
`to 2004 time frame, my study of the Patents-in-Suit, and their file histories, and my knowledge of:
`
` The level of education and experience of persons actively working in the field at the
`
`time the subject matter at issue was developed;
`
` The types of problems encountered in the art at the time the subject matter was
`
`developed;
`
` The prior art patents and publications;
`
` The activities of others working in that same technical field;
`
` Prior art solutions to the problems addressed by the relevant art; and
`
` The sophistication of the technology at issue in this case.
`
`11.
`
`
`In determining the level of ordinary skill in the art, I also considered the following
`
`factors: (1) the sophistication of the relevant technology; (2) the rapidity with which innovations
`
`are made in that field; and (3) the educational level of active workers in that field. It is my further
`
`understanding that these factors are not exhaustive and are merely a useful guide to determining
`
`the level of ordinary skill in the art.
`
`12.
`
`
`Taking the above factors into account, in my opinion a POSITA in the technology
`
`field of the Patents-in-Suit would be a person with at least a Bachelor’s of Science degree in
`
`electrical or computer engineering, materials science, chemical engineering, applied physics, or a
`
`related field, with emphasis on semiconductor manufacturing, or an equivalent degree, and at least
`
`four years of experience in semiconductor design and manufacturing. Additional education in a
`
`relevant field, or industry experience may compensate for a deficit in one of the other aspects of
`
`the requirements stated above.
`
`13.
`
`
`I understand that Defendants’ expert in this proceeding, Dr. Scott Thompson, has
`
`stated a different characterization of a POSITA. Dkt. 82-26 (Declaration of Dr. Scott Thompson),
`
`¶2 (“[A] person of ordinary skill in the art at the time of the Asserted Patents would have had a
`
`Bachelor’s degree in electrical engineering, material science, applied physics, or a related field,
`
`and four years of experience in semiconductor design and manufacturing or equivalent work
`
`
`
`4
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 12 of 57
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`experience. This description is approximate, and a higher level of education or skill might make
`
`up for less experience, and vice-versa.”). I agree with his characterization, as chemical engineering
`
`is a related field in this context. I was at least a POSITA as of September 3, 2004, which I
`
`understand is the filing date of U.S. Application No. 10/934,915, to which the Patents-in-Suit claim
`
`priority.
`
`14.
` My opinions regarding claim construction for the claim terms in dispute in this
`
`proceeding are based on the relevant knowledge and skillset of a POSITA for the Patents-in-Suit.
`
`v.
`
`
`GENERAL BACKGROUND OF THE RELEVANT TECHNOLOGY AND THE
`PATENTS-IN-SUIT
`
`A.
`
`Dopants
`
`15.
`
`
`Silicon is an example of a semiconductor. In its pure form it is typically an insulator
`
`but it can become a conductor of electricity when impurities called “dopants” are added into the
`
`silicon crystal. These dopants are usually phosphorous or boron atoms that have one more or one
`
`fewer valence electron than the silicon atom, respectively. If the dopant has one more valence
`
`electron than silicon, that electron is available for electronic conduction in the silicon. If the dopant
`
`has one fewer valence electron than silicon, then it creates what is called a “hole,” which is a
`
`positive unit of charge. Such holes are conventionally assumed to be capable of conducting
`
`positive current through the silicon. Thus, electric charge in semiconductors is thought to be
`
`carried by both electrons and holes, which are then referred to as “charge carriers.”
`
`16.
`
`
`The extra electrons or holes in a doped region of silicon disturb the local charge
`
`equilibrium and they can create local electric fields, which will influence the motion of other
`
`charge carriers passing by. This phenomenon is called “carrier drift.” Ex. 12, 38-39. When the
`
`dopant concentration is graded in a particular direction, the ensuing electric field points in the
`
`direction of the gradient and, thus, charge carriers will also drift in the gradient direction or
`
`opposite to it depending on the charge carrier’s polarity. Id., 103-106.
`
`
`
`5
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 13 of 57
`
`B.
`
`Overview of Dr. Rao’s Inventions
`
`17.
`
`
`At the time of Dr. Rao’s inventions claimed in the Patents-In-Suit, most
`
`semiconductor devices relied on uniform concentrations of dopants. Ex. 2 (195 patent), Abstract;
`
`1:36-40, 50-51. Dr. Rao recognized that graded concentrations of dopants can be used to improve
`
`the performance of transistors and other semiconductor devices. Id., Abstract; 3:3-13, 33-35. Dr.
`
`Rao’s invention is clearly disclosed in Figures 5B and 5C of his patents, and the corresponding
`
`parts of the specification.
`
`18.
`
`
`A surface-channel MOSFET is a well-known type of transistor that is capable of
`
`controlling current flow at or along the surface of the semiconductor substrate. Dkt. 82-16 (Wolf
`
`Vol 2), 5-6; Ex. 4 (Chen), 27 (“carriers propagate slightly under the semiconductor surface”). The
`
`current flow occurs in a thin layer of silicon near the surface, called the “channel”, located between
`
`two terminals called the source and the drain. MOSFETs come in two flavors, NMOS and PMOS,
`
`depending on whether the current flow is based on electrons or holes, respectively. The carrier
`
`type in channel conduction requires oppositely doped silicon regions to build the transistors in,
`
`specifically, p-type for NMOS, and n-type for PMOS.
`
`19.
` MOSFETs are built in active regions, defined on the wafer surface by isolation
`
`regions. Ex. 13, 327 (Wolf Vol 2) (“Active region and field region definitions”). Since the
`
`substrate is typically doped either n-type or p-type, only one kind of devices can be built on a
`
`typical substrate. When both NMOS and PMOS transistors are used in complementary metal oxide
`
`semiconductor (CMOS) applications, isolated regions of opposite type dopant than present in the
`
`starting material are created within a substrate called “wells.” Dkt. 82-16, 17-20. The
`
`corresponding transistor is then built in a surface layer located in the upper part of the well. In
`
`specialized CMOS applications, wells are created in a substrate for both NMOS and PMOS
`
`transistors, known as “twin-wells.” Ex. 13, 387-389. Sometimes, wells within wells of the
`
`opposite dopant type are used for better isolation from the substrate.
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`6
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 14 of 57
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`20.
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`Conventional wells are formed by implanting dopants and then diffusing them to
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`the desired depth. However, diffusion occurs laterally as well as vertically, which increases the
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`width of the well and reduces packing density. This problem is avoided by using high energy
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`implants to place the dopants at the desired depth without further diffusion. Such deeply implanted
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`wells are known as “retrograde wells”. The retrograde doping profile is different from the
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`conventional uniform or downward sloping profile: the impurity concentration decreases as it
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`approaches the wafer surface. Ex. 13, 389; Ex. 14, 531.
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`21.
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`Figure 5B of the 195 patent, annotated below, shows an n-channel MOS (NMOS)3
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`transistor that is formed in a p-type surface layer of silicon. The transistor comprises (1) a gate;
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`(2) a thin oxide separating the gate from the surface layer; and (3) two doped regions called the
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`source and drain (shaded red). Ex. 2, 3:10-11 (“electrons can be swept from source to drain”);
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`3:42-43 (“accelerate majority carriers towards the drain”). In Fig. 5B, the N+ means that these
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`regions are heavily doped with an n-type dopant that creates a surplus of negative carriers (i.e.,
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`electrons).4 The specification explains that the NMOS transistor in Fig. 5B can be a surface-
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`channel MOSFET. Ex. 3:41-43.
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`
`
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`3 MOS stands for “metal oxide semiconductor.” It refers generally to metal and oxide layers that
`are formed on top of a semiconductor (e.g., silicon). In some MOS devices, the metal is replaced
`with another conductor such as doped polysilicon. Ex. 4, 10.
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`4 A helpful way to understand the dopants is that an “N” region or layer will have more electrons,
`and thus an abundance of “negative charge carriers.” A “P” layer will have more holes, and thus
`an abundance of “positive charge carriers.” The “+” or “-” refers to the amount of doping. A “+”
`means heavily doped; “-” lightly doped.
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`
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`7
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 15 of 57
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`AccessTransistor
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`Storage Capacitor or
`• nsor element
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`Graded dopant region to pull minority carriers from surface
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`
`
`Ex. 2, Fig. 5B (annotated). Meanwhile, the p-type silicon between the source and drain (shaded
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`blue) has an abundance of positively charged holes (green circles). Electrons are still present in
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`the silicon, but the overwhelming majority of the carriers are holes.
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`22.
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`In the simplest terms, an NMOS transistor switches between two states, ON and
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`OFF. With no bias applied on the gate, electron conduction between source and drain is not
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`possible in the arrangement described above with a p-type silicon between the N+ source and drain
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`terminals. The transistor is described as being in the OFF state. When a positive voltage is applied
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`to the gate, an electric field forms in the oxide, which extends further into the silicon below the
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`oxide. This electric field perturbs the local charge equilibrium: it repels the holes away from the
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`oxide, while it attracts electrons (red circles) closer to the oxide. When enough electrons have
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`accumulated in the surface layer of silicon below the oxide, they form a conductive channel for
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`electrons between the source and the drain, and current can begin to flow through the transistor.
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`Current flow through the transistor corresponds to the transistor turning ON.
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`
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`8
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 16 of 57
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`AccessTransistor
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`Storage Capacitor or
`nso r element
`
`Graded dopant region to pull minority carriers from surface
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`
`
`Ex. 2, Fig. 5B (annotated)5 In order to turn the transistor OFF, the positive voltage is removed
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`from the gate, causing the conductive channel of electrons to vanish as the holes return to the
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`surface layer.
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`23.
`
`
`The term “well region” describes typically the doped silicon that surrounds the
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`source and drain. Since wells are totally isolated from the substrate, well contacts are made to
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`control the potential of each well. Ex. 14, 523 (“When wells are present, however, the well regions
`
`must also be connected to the appropriate circuit voltages….”).
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`24.
`
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`Dr. Rao recognized that by using graded concentrations of dopants in the well
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`region and a drift layer (shaded pink), it is possible to “pull” carriers from the silicon’s surface. In
`
`this example, pulling the repelled holes further away from the surface layer when a positive voltage
`
`is applied to the gate, allows the transistor to turn “on” more quickly. This improves the speed
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`and performance of the transistor. Ex. 2, 3:8-13.
`
`25.
`
`
`As its name suggests, the channel in a surface channel MOSFET forms at or along
`
`the surface. But it is slightly more complicated that. As shown in the well-known figure below,
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`the n-channel starts at the source (on the left) and expands towards the drain (on the right) as the
`
`
`5 Because the channel is formed by electrons with a negative charge, the MOSFET is referred to
`as an n-channel MOSFET. In an n-channel MOSFET, the electrons are referred to as the “majority
`carriers,” and the “minority carriers” are holes.
`
`
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`9
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 17 of 57
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`voltage applied to the gate increases. There is a thin layer below the surface (shaded red) where
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`the channel actually forms. The cross-hatched region underneath is known as the depletion region.
`V9 > V,
`Channel
`
`Vd sma ll
`
`p
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`
`
`Ex. 4, 19 (shaded). As shown above, the n-channel does not actually form on the surface but rather
`
`in the layer just below the surface (i.e., the surface layer).
`
`C.
`
`Exemplary Claim 1 of the ’195 Patent
`
`26.
`
`
`Six of the seven disputed claim terms can be found in exemplary claim 195:1.
`
`These six claim terms are numbered and color coded below.
`
`
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`10
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 18 of 57
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`Term
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`U.S. Patent No. 8,421,195, Claim 1 (195:1)
`
`1
`
`2
`
`4
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`
`
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`5
`
`6
`
`
`
`
`
`
`
`
`
`
`
`
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`A CMOS Semiconductor device comprising:
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`a surface layer;
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`a substrate;
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`an active region including a source and a drain, disposed on one surface of said
`surface layer;
`
`a single drift layer disposed between the other surface of said surface layer and said
`substrate, said drift layer having a graded concentration of dopants extending
`between said surface layer and said substrate, said drift layer further having a first
`static unidirectional electric drift field
`
`to aid the movement of minority carriers from said surface layer to said
`substrate; and
`
`at least one well region disposed in said single drift layer, said well region having a
`graded concentration of dopants and a second static unidirectional electric drift field
`to aid the movement of minority carriers from said surface layer to said substrate.
`
`27.
`
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`I am informed that Defendants contend that certain claim terms render claim 1 of
`
`the ’195 patent indefinite. In my opinion, far from being indefinite, claim 1 lines up exactly with
`
`Fig. 5B and the corresponding parts of the specification. Fig. 5B confirms what is meant by each
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`claim term. As the preamble states, Fig. 5B illustrates a CMOS semiconductor device with metal
`
`and oxide layers on a silicon substrate. Ex. 2, 2:27-31; 3:41-43. The specification mentions
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`verbatim that the CMOS device may be a surface channel MOSFET. Id., 3:41-43; see also 1:43-
`
`45.
`
`28.
`
`
`As seen below, the CMOS semiconductor device comprises a surface layer (blue)
`
`and a substrate (gray). Id., 3:30-45. The substrate is lightly doped with holes (P-), and the surface
`
`layer is a layer at the surface of the silicon. As explained below, the invention is concerned with
`
`moving minority carriers from this surface layer to the substrate.
`
`
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`11
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 19 of 57
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`AccessTransi sl or
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`Storage Capacitor or
`nsor element
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`1 SURFACE LAYER
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`Graded doponl region to pull minority carriers from surface
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`2 SUBSTRATE
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`P-substrate
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`
`
`Ex. 2, Fig. 5B (annotated).6
`
`29.
`
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`The surface layer has at least two surfaces, which claim 195:1 refers to as the “one
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`surface of said surface layer” and “the other surface of said surface layer.”
`AccessTransistor
`
`Storage ◄
`nso
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`"ONE SURFACE OF SAID SURFACE LAYER"
`
`1
`../
`"THE OTHER SURFACE OF SAID SURFACE LAYER"
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`Graded dopant region to pull minority carriers from surface
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`
`
`Ex. 2, Fig. 5B (annotated); id., 4:16-19.
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`30.
`
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`Next, the claim specifies an active region with a source and drain. Id., 4:16-17.
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`Figure 5B shows how the active region is “disposed on one surface of said surface layer.”
`
`
`6 As explained below, “substrate” is a relative term, and Dr. Rao sometimes used it to refer to the
`bottom layer, and other times he used it to refer to the wells that are underneath the surface layer
`and active region. In both cases, the “substrate” is an “underlying layer.”
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`
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`12
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`CIRRUS EX. 1039 - 19/57
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`Case 6:22-cv-00105-ADA Document 96-1 Filed 10/31/22 Page 20 of 57
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`AccessTTansistor
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`"ONE SURFACE OF SAID SURFACE LAYER"
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`Graded dopant region to pull minority carriers from surface
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`
`
`Ex. 2, Fig. 5B (annotated).
`
`31.
`
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`The “active region” is a doped region where a transistor or other active device can
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`be formed. Ex. 2, 1:61-63; 2:18-23; 3:1-3, 30-33. As explained below, Dr. Rao contemplated that
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`the CMOS device may have multiple active regions where transistors are formed in some, but not
`
`all of the active regions.
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`32.
`
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`Next, the claim specifies there is a single drift layer disposed between “the other
`
`surface of said