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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
`
`SONY GROUP CORPORATION
`
`Petitioner
`
`v.
`
`GREENTHREAD, LLC
`
`(record) Patent Owner
`
`IPR2023-00376
`Patent No. 10,510,842
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.200 ET. SEQ
`
`
`
`
`
`
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`Patent No. 10,510,842
`
`TABLE OF CONTENTS
`TABLE OF EXHIBITS ............................................................................................. 4
`NOTICE OF LEAD AND BACKUP COUNSEL ..................................................... 7
`NOTICE OF RELATED MATTERS ........................................................................ 7
`NOTICE OF THE REAL-PARTIES-IN-INTEREST ............................................... 7
`NOTICE OF SERVICE INFORMATION ................................................................ 7
`GROUNDS FOR STANDING .................................................................................. 8
`STATEMENT OF PRECISE RELIEF REQUESTED .............................................. 8
`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW ......................... 8
`I.
`INTRODUCTION ........................................................................................... 8
`A.
`Technical Background ........................................................................... 8
`CLAIM CONSTRUCTION ............................................................................ 9
`II.
`III. DETAILED EXPLANATION OF THE REASONS FOR
`UNPATENTABILITY .......................................................................... 9
`Ground 1. Claims 1-5, 7-13, and 15-18 were obvious over Miyagawa ................. 9
`A.
`Effective Prior Art Date of Miyagawa .................................................. 9
`B.
`Overview of Miyagawa ....................................................................... 10
`C.
`Overview of the Ground ...................................................................... 15
`D.
`Rationale (Motivation) Supporting Obviousness ................................ 15
`E.
`Graham Factors ................................................................................... 17
`F.
`Reasonable Expectation of Success .................................................... 17
`G. Analogous Art ..................................................................................... 18
`H.
`Claim Mapping .................................................................................... 18
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`Ground 2. Claims 1-18 were obvious over Yamashita ........................................ 37
`A.
`Effective Prior Art Date of Yamashita ................................................ 37
`B.
`Overview of the Combination ............................................................. 38
`C.
`Rationale (Motivation) Supporting Obviousness ................................ 40
`D. Graham Factors ................................................................................... 40
`E.
`Reasonable Expectation of Success .................................................... 41
`F.
`Analogous Art ..................................................................................... 42
`G.
`Claim Mapping .................................................................................... 42
`Ground 3. Claims 1-18 are obvious over Yamashita and Nishi. .......................... 67
`A.
`Effective Prior Art Dates ..................................................................... 67
`B.
`Overview of the Ground ...................................................................... 67
`C.
`Rationale (Motivation) Supporting Obviousness ................................ 70
`D. Graham Factors ................................................................................... 74
`E.
`Reasonable Expectation of Success .................................................... 74
`F.
`Analogous Art ..................................................................................... 74
`G.
`Claim Mapping .................................................................................... 75
`IV. DISCRETIONARY INSTITUTION ............................................................. 75
`A.
`The Board should not deny the petition under 35 U.S.C. §325(d) ..... 75
`B.
`The Board should not deny the petition under 35 U.S.C. §314(a) ...... 76
`CONCLUSION .............................................................................................. 78
`V.
`CERTIFICATE OF SERVICE ................................................................................ 80
`CERTIFICATE OF WORD COUNT ...................................................................... 81
`
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`Patent No. 10,510,842
`
`Exhibit No.
`1001
`1002
`1003
`1004
`1005
`1006
`
`1007
`
`1008
`1009
`1010
`1011
`1012
`
`1013
`
`1014
`
`1015
`
`TABLE OF EXHIBITS
`
`Description
`U.S. Patent No. 10,510,842 (“the ’842 patent”).
`Declaration of R. Michael Guidash.
`C.V. of R. Michael Guidash.
`U.S. Pat. No. 6,614,560 (“Silverbrook”).
`U.S. Pat. No. 6,420,763 (“Yamashita”).
`File History of U.S. App. Ser. No. 11/622,496 (issued as U.S. Pat.
`No. 8,421,195).
`File History of U.S. App. Ser. No. 15/590,282 (issued as the
`’842 patent).
`U.S. Pat. No. 4,481,522 (“Jastrzebski”).
`Redline comparison of claim 1 and claim 9
`U.S. Pat. Pub. 2004/0063288 A1 (“Kenney”).
`U.S. Pat. Pub. 2001/0032983 A1 (“Miyagawa”).
`Excerpt from Nishi, et al. (eds.) Handbook of Semiconductor
`Manufacturing, Marcel Dekker, Inc., New York (2000)
`(“Nishi”).
`Defendants’ Opening Claim Construction Brief in Greenthread,
`LLC v. Intel Corp., et al., Case No. 6:22-cv-105-ADA (W.D. Tex.
`Oct. 10, 2022).
`Plaintiffs’ Claim Construction Brief in Greenthread, LLC v. Intel
`Corp., et al., Case No. 6:22-cv-105-ADA (W.D. Tex. Oct. 31,
`2022).
`Complaint in Greenthread, LLC v. Intel Corp., et al., Case No.
`6:22-cv-105-ADA (W.D. Tex. January 27, 2022).
`
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`Patent No. 10,510,842
`
`1016
`
`1017
`
`1018
`1019
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`1025
`1026
`1027
`1028
`
`1029
`
`Amended Complaint in Greenthread, LLC v. Intel Corp., et al.,
`Case No. 6:22-cv-105-ADA (W.D. Tex. April 29, 2022).
`Exhibit 12 from Amended Complaint in Greenthread, LLC v.
`Intel Corp., et al., Case No. 6:22-cv-105-ADA (W.D. Tex. April
`29, 2022).
`U.S. Pat. App. Pub. 2003/0136982A1 (“Rhodes”).
`Scheduling Order in Greenthread, LLC v. Intel Corp., et al., Case
`No. 6:22-cv-105-ADA (W.D. Tex. May 23, 2022).
`United States District Courts — National Judicial Caseload
`Profile,
`March
`31,
`2022,
`available
`at
`https://www.uscourts.gov/statistics/table/na/federal-court-
`management-statistics/2022/03/31-1
`Scheduling Order in Topia Tech., Inc. v. Box, Inc., et al., Case
`No. 6:21-cv-01372-ADA (W.D. Tex. May 20, 2022).
`Scheduling Order in Parus Holdings, Inc., v. Apple Inc., et al.,
`Case No. 6:21-cv-00570-ADA (W.D. Tex. August 22, 2022).
` Scheduling Order in Lone Start SCM Systems, Ltd. V. Zebra
`Tech. Corp., Case No. 6:21-cv-00570-ADA (W.D. Tex. August
`3, 2022).
`U.S. Pat. No. 6,483,176 (“Noguchi”).
`U.S. Pat. App. Pub. 2003/0063272A1 (“Zaidi”).
`U.S. Pat. App. Pub. 2003/0081463A1 (“Bocian”).
`U.S. Pat. App. Pub. 2003/0098419A1 (“Ji”).
`Screen capture of https://www.bestbuy.com/site/sony-alpha-a7-
`iii-mirrorless-4k-video-camera-body-only-
`black/6213101.p?skuId=6213101
`Excerpt from Pierret, Semiconductor Fundamentals, Vol. I,
`Addison-Wesley Publishing Company, Reading, MA, 1983.
`
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`Patent No. 10,510,842
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`1030
`
`1031
`
`1032
`
`Excerpt from Grove, Physics and Technology of Semiconductor
`Devices, John Wiley & Sons, 1967.
`Excerpt from Sze, VLSI Technology, McGraw-Hill Book
`Company, 1983.
`Excerpt from Wolf and Tauber, Silicon Processing for the VLSI
`ERA, Lattice Press, Sunset Beach, CA, (2000).
`
`
`
`
`
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`Patent No. 10,510,842
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`Petitioner respectfully requests inter partes review under 35 U.S.C. §311 of
`
`claims 1-18 of U.S. Pat. No. 10,510,842 (“the ’842 patent”).
`
`NOTICE OF LEAD AND BACKUP COUNSEL
`Lead Counsel
`Backup Counsel
`Matthew A. Smith
`Andrew S. Baluch
`Reg. No. 49,003
`Reg. No. 57,503
`SMITH BALUCH LLP
`SMITH BALUCH LLP
`700 Pennsylvania Ave. SE, Ste 2060
`700 Pennsylvania Ave. SE, Ste 2060
`Washington, DC 20003
`Washington, DC 20003
`(202) 669-6207
`(202) 880-2397
`smith@smithbaluch.com
`baluch@smithbaluch.com
`
`
`NOTICE OF RELATED MATTERS
`The ’842 patent has been asserted in Greenthread, LLC v. Intel Corporation
`
`
`
`et al, Case No. 6-22-cv-00105 (W.D. Tex.), filed January 27, 2022, and is the subject
`
`of Intel Corporation v. Greenthread, LLC, IPR2023-00308. A submission
`
`addressing multiple proceedings is filed herewith.
`
`NOTICE OF THE REAL-PARTIES-IN-INTEREST
`The real-parties-in-interest (“RPIs”) are Sony Group Corporation, Sony
`
`Corporation, Sony Semiconductor Solutions Corporation, Sony Semiconductor
`
`Manufacturing Corporation, Sony Taiwan Ltd., Sony Corporation of America, Sony
`
`Electronics Inc., Dell Inc., and Dell Technologies Inc.
`
`NOTICE OF SERVICE INFORMATION
`Please address all correspondence to the lead counsel at the addresses shown
`
`above.
`
`Petitioner
`
`consents
`
`to
`
`electronic
`
`service
`
`by
`
`email
`
`at:
`
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`Patent No. 10,510,842
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`smith@smithbaluch.com, baluch@smithbaluch.com.
`
`GROUNDS FOR STANDING
`Petitioner hereby certifies that the patent for which review is sought is
`
`available for inter partes review, and that the Petitioner is not barred or estopped
`
`from requesting inter partes review on the grounds identified in the petition.
`
`STATEMENT OF PRECISE RELIEF REQUESTED
`Petitioner respectfully requests that claims 1-18 of the ’842 patent be canceled
`
`based on the following grounds:
`
`Ground 1: Claims 1-5, 7-13, and 15-18 were obvious over Miyagawa
`
`Ground 2: Claims 1-18 were obvious over Yamashita.
`
`Ground 3: Claims 1-18 were obvious over Yamashita and Nishi.
`
`THRESHOLD REQUIREMENT FOR INTER PARTES REVIEW
`As shown in the Grounds set forth below, the information presented in the
`
`instant petition, if unrebutted, demonstrates that “it is more likely than not that at
`
`least 1 of the claims challenged in the petition is unpatentable.” 35 U.S.C. § 314(a).
`
`I.
`
`INTRODUCTION
`A. Technical Background
`The ’842 patent relates to semiconductor devices having graded dopant
`
`concentrations. Petitioner’s expert, Mr. Guidash, provides an introduction to the
`
`technology concepts relevant to the ’842 patent. (Ex. 1002, ¶¶24-68).
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`Patent No. 10,510,842
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`II. CLAIM CONSTRUCTION
`“In an inter partes review proceeding, a claim of a patent…shall be construed
`
`using the same claim construction standard that would be used to construe the claim
`
`in a civil action under 35 U.S.C. 282(b), including construing the claim in
`
`accordance with the ordinary and customary meaning of such claim as understood
`
`by one of ordinary skill in the art and the prosecution history pertaining to the
`
`patent.” 37 C.F.R. §42.100(b).
`
`Petitioner does not believe that claim construction is required for the Board to
`
`evaluate obviousness in this Petition.
`
`Greenthread LLC and defendants related to Dell and Intel have taken claim
`
`construction positions in the co-pending litigation, as reflected in Exhibits 1013 and
`
`1014.
`
`III. DETAILED EXPLANATION OF THE REASONS FOR
`UNPATENTABILITY
`
`Ground 1. Claims 1-5, 7-13, and 15-18 were obvious over Miyagawa
`Claims 1-5, 7-13, and 15-18 were obvious under pre-AIA 35 U.S.C. §103(a)
`
`over U.S. Pat. Pub. 2001/0032983 A1 (“Miyagawa”)(Ex. 1011).
`
`A. Effective Prior Art Date of Miyagawa
`Miyagawa is a U.S. patent application publication that published on October
`
`25, 2001, and is thus prior art under pre-AIA 35 U.S.C. §102(b).
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`Patent No. 10,510,842
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`B. Overview of Miyagawa
`Miyagawa teaches semiconductor devices useful for MOS (Metal Oxide
`
`Semiconductor) image sensors. (Ex. 1011, Title, Abstract)(Ex. 1002, ¶72). Such
`
`image sensors are usually fabricated using CMOS techniques in a silicon substrate.
`
`(Ex. 1002, ¶72). Within that domain, Miyagawa teaches the techniques for arranging
`
`the semiconductor structure of pixels within image sensor arrays. A “pixel” or
`
`“picture element” is a single dot in an image. (Ex. 1002, ¶72). A pixel is also a
`
`portion of an image sensor that senses the intensity of incoming light at a particular
`
`position in space that corresponds to a position in an image. (Ex. 1002, ¶72).
`
`Miyagawa uses a particular type of pixel circuit called an “amplifier-type” pixel.
`
`(Ex. 1011, ¶0001)(Ex. 1002, ¶72). An “amplifier-type” pixel is a pixel that uses a
`
`photodiode to convert incoming light to an electric charge, but also has transistors
`
`within the area of the pixel circuit to move and amplify the charge of the photodiode.
`
`(Ex. 1002, ¶72).
`
`A circuit diagram of a portion of an image sensor, showing multiple pixels
`
`(one of which is highlighted by an added, red-dashed box), is provided in
`
`Miyagawa’s Fig. 3, reproduced here:
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`(Ex. 1011, Fig. 3, ¶¶0030, 0057-0058)(Ex. 1002, ¶73). In Fig. 3, the pixel elements
`
`are laid out in a grid (nine elements of which are shown in Fig. 3, although typically
`
`there would be millions). (Ex. 1002, ¶73). Within the grid, each pixel element has
`
`a photodiode 36 (symbol:
`
`) and several transistors (symbol:
`
`). (Ex. 1002, ¶73).
`
`Incoming light enters the area of the photodiode 36 in each pixel, is converted to
`
`charge, processed by transistors in the pixel, and ultimately converted to form the
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`Patent No. 10,510,842
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`numerical values of a digital image. (Ex. 1002, ¶73).
`
`Miyagawa provides semiconductor arrangements for portions of individual
`
`pixels. An example is shown in Fig. 9E, reproduced below, which is a cross-section
`
`of a semiconductor image sensor device in a portion of a pixel:
`
`
`(Ex. 1011, Fig. 9E, ¶¶0036, 0110-0116)(Ex. 1002, ¶74). In Fig. 9E, there is a
`
`photodiode formed by the contact between the n-type region 54 and the p-type region
`
`42. (Ex. 1011, Abstract, ¶¶0110, 0113, 0067)(Ex. 1002, ¶74). This photodiode will
`
`convert incoming light to electric charge (specifically: electrons and holes, with the
`
`electrons collected in the photodiode). (Ex. 1002, ¶74). The electrons can be read
`
`out through a read-out transistor formed from n-type region 54 (the source),
`
`electrode 52 (the gate electrode), and n-type region 58 (the drain). (Ex. 1011,
`
`¶0113)(Ex. 1002, ¶74).
`
`Miyagawa teaches active regions that have graded dopant regions. (Ex. 1011,
`
`Figs. 12-17, ¶¶0043, 0121-0132)(Ex. 1002, ¶75). Miyagawa, for example, teaches
`
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`Patent No. 10,510,842
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`a Seventh Embodiment having a dopant profile with depth as shown in Fig. 16,
`
`reproduced here (where the top surface of the substrate is on the left):
`
`
`(Ex. 1011, Fig. 16, ¶¶0043, 0125-0132)(Ex. 1002, ¶75). The dopant profile in Fig.
`
`16 results in the relationship between the depth from the substrate surface and the
`
`electric potential as shown in Fig. 17, reproduced here:
`
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`Patent No. 10,510,842
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`
`(Ex. 1011, Fig. 17, ¶0044)(Ex. 1002, ¶75). As shown in Fig. 17, charge carriers
`
`(shown as small circles with negative signs within them) that are near the surface
`
`(left side) are aided in their movement toward the lower portion of the substrate by
`
`the electric field that results from graded dopant profiles. (Ex. 1002, ¶75). Similarly,
`
`negative charge carriers that occur deeper are aided in their movement toward the
`
`lower portion of the substrate by the graded dopant profile. (Ex. 1011, ¶0131-
`
`0132)(Ex. 1002, ¶75). Miyagawa teaches that this arrangement is advantageous:
`
`“Thus, in a photodiode having an impurity concentration distribution
`profile as shown in FIG. 16, signal charges are apt to defect to the
`storage section when they are few in number, whereas they show a
`downward gradient toward the substrate when the substrate is
`
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`Patent No. 10,510,842
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`irradiated with highly bright light so that the storage section is less
`liable to be saturated with signals as excessive signal charges are
`diffused toward the substrate to increase the dynamic range where
`the number of stored signals is increased in response to the intensity
`of incident light.”
`
`(Ex. 1011, ¶0132)(Ex. 1002, ¶75). This arrangement is “designed to realize a high
`
`dynamic range.” (Ex. 1011, ¶0124)(Ex. 1002, ¶75).
`
`C. Overview of the Ground
`Miyagawa nearly anticipates the independent claims. This ground is
`
`presented as one of obviousness because Miyagawa does not expressly state that the
`
`dopant profile of Fig. 16 is used with the semiconductor structure shown in Fig. 9E.
`
`This ground thus posits that the dopant profile of Fig. 16 of Miyagawa would have
`
`been obvious to use with the structure shown in Fig. 9E of Miyagawa. (Ex. 1002,
`
`¶76). This ground further posits that it would have been obvious to arrange adjacent
`
`pixel cells, each having an active region such as the one shown in Fig. 9E, to form
`
`an image sensor. Finally, this ground posits that Miyagawa renders certain
`
`dependent claims obvious.
`
`D. Rationale (Motivation) Supporting Obviousness
`It would have been obvious to use the dopant profile of Fig. 16 and the
`
`attendant electrical potential profile of Fig. 17 in the semiconductor cross-section
`
`shown in Fig. 9E. (Ex. 1002, ¶77).
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`Patent No. 10,510,842
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`First, the disclosure of the two embodiments in Miyagawa already suggests
`
`their combination. (Ex. 1002, ¶78). Miyagawa presents a number of related,
`
`structural embodiments (Figs. 4-9) directed at specific semiconductor arrangements
`
`for addressing a problem of leakage current. (e.g., Ex. 1011, ¶0066-0067, 0112,
`
`0116)(Ex. 1002, ¶78). Miyagawa then presents a number of embodiments that
`
`address a problem of saturation in bright light to provide a high dynamic range. (Ex.
`
`1011, ¶¶0131-0132)(Ex. 1002, ¶78). It would have been obvious to combine these
`
`two techniques. See Boston Sci. Scimed, Inc., et al. v. Cordis Corp., et al., 554 F.3d
`
`982, 991 (Fed. Cir. 2009)(“Combining two embodiments disclosed adjacent to each
`
`other in a prior art patent does not require a leap of inventiveness.”).
`
`Furthermore, a POSITA would have been motivated to use the techniques of
`
`the Seventh Embodiment (including Figs. 16 and 17) in the device of Fig. 9E in order
`
`to achieve the advantage of high dynamic range, as expressly taught by Miyagawa.
`
`(Ex. 1011, ¶¶0001, 0025, 0124-0125, 0132)(Ex. 1002, ¶79). The embodiments were
`
`compatible and could have been combined with no unpredictable results. (Ex. 1002,
`
`¶79).
`
`Finally, the structure of Fig. 9E represents a known device that was ready for
`
`improvement using the known techniques of the Seventh Embodiment of Miyagawa,
`
`which would have been predictable and within ordinary skill to implement. (Ex.
`
`1002, ¶80). See KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416-21 (2007).
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`Patent No. 10,510,842
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`To the extent additional rationales to support obviousness are necessary, they
`
`will be explained in the Claim Mapping section below as appropriate.
`
`E. Graham Factors
`The level of ordinary skill encompassed a person having a Bachelor’s Degree
`
`in electrical engineering, microelectronics engineering or a related field and three
`
`years of experience relating to semiconductor device manufacturing, where a higher
`
`level of education may substitute for experience and vice versa. (Ex. 1002, ¶82).
`
`The scope and content of the prior art are discussed throughout the Ground.
`
`The differences between the prior art and the claims are discussed in the
`
`sections entitled “Overview of the Ground” and “Rationale (Motivation) Supporting
`
`Obviousness”, above, and in the claim mapping, below.
`
`Petitioner is not aware of any secondary considerations that would make an
`
`inference of non-obviousness more likely.
`
`F. Reasonable Expectation of Success
`A person of ordinary skill in the art (“POSITA”) in the relevant timeframe
`
`would have had a reasonable expectation of success in using the prior art in the
`
`manner discussed in this petition. (Ex. 1002, ¶86). As Mr. Guidash explains, the art
`
`was relatively predictable in the relevant timeframe (September 2004), with
`
`commercially available sophisticated circuit design, process modeling, and physic-
`
`based transistor modeling software tools. (Ex. 1002, ¶86). A POSITA would have
`
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`Patent No. 10,510,842
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`been able to make any necessary modifications to implement the Ground, and in
`
`particular would have been able to apply the techniques of Miyagawa’s Seventh
`
`Embodiment in an image sensor having the structure of Fig. 9E in its pixel regions.
`
`(Ex. 1002, ¶86).
`
`G. Analogous Art
`Miyagawa is analogous art because it is in the same field as the ’842 patent
`
`(semiconductor devices). (Ex. 1001, Abstract)(Ex. 1011, Abstract, ¶0001).
`
`Furthermore, the methods of Miyagawa would have been reasonably pertinent to the
`
`problems facing the named inventors, for example, the problem of controlling
`
`carriers in CMOS image sensors. (Ex. 1001, 3:44-64)(Ex. 1011, ¶¶0123-0133)(Ex.
`
`1002, ¶87). See Wyers v. Master Lock Co., 616 F.3d 1231, 1238 (Fed. Cir.
`
`2010)(“The Supreme Court’s decision in KSR [cite omitted], directs us to construe
`
`the scope of analogous art broadly….”).
`
`H. Claim Mapping
`This section maps the challenged claims to the relevant disclosures of
`
`Miyagawa, where the claim text appears in bold-italics, and the relevant mapping
`
`follows the claim text. The Petitioner has added numbering and lettering in brackets
`
`(e.g., 1[a], [1b]) to certain claim elements, to facilitate the discussion.
`
`CLAIM 1
`
`“1[a]. A semiconductor device, comprising:”
`
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`Patent No. 10,510,842
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`Miyagawa teaches a semiconductor device, one example of which is shown
`
`in cross-section in Fig. 9E, reproduced here:
`
`
`
`
`(Ex. 1011, Fig. 9, ¶¶0110-0111)(Ex. 1002, ¶89). The device shown in Fig. 9E is a
`
`cross section of the “solid-state imaging apparatus” of Miyagawa, which is also a
`
`semiconductor device. (Ex. 1011, ¶0001)(Ex. 1002, ¶89).
`
`“[1b] a substrate of a first doping type at a first doping level having
`first and second surfaces;”
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`The device of Fig. 9E of Miyagawa has a substrate of a first doping type at
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`a first doping level having first and second surfaces, in the form of a “p-type”
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`semiconductor substrate 42. (Ex. 1011, ¶¶0110-0113, 0060)(Ex. 1002, ¶90). The
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`substrate is of a first doping type because it is “p-type”, which refers to a type of
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`doping, and must obviously have a first doping level. (Id.). The substrate has first
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`and second surfaces, which are the top surface and bottom surface of the device,
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`respectively. (Ex. 1002, ¶90). The surfaces are shown by the added, red-dashed
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`lines in Fig. 9E, reproduced again here:
`
`
`(Ex. 1011, Fig. 9E)(Ex. 1002, ¶90). As Mr. Guidash explains, the substrate
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`comprises almost the entire thickness of a semiconductor device, whereas active
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`devices, such as transistors and photodiodes, are built with relatively shallow depths
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`at the top of the substrate. (Ex. 1002, ¶90).
`
`“[1c] a first active region disposed adjacent the first surface of the
`substrate with a second doping type opposite in conductivity to the
`first doping type and within which transistors can be formed;”
`
`Miyagawa teaches a first active region disposed adjacent the surface in the
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`form of a region indicated by the added red arrow in Fig. 9E, reproduced below:
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`(Ex. 1011, Fig. 9E)(Ex. 1002, ¶91). Laterally, the active region extends between
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`the isolating oxide portions 50 on the right and left sides of the figure. (Ex. 1002,
`
`¶91). The active region is adjacent the surface because it is formed in the surface
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`of the substrate. (Ex. 1002, ¶91).
`
`The active region furthermore has a second doping type opposite in
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`conductivity to the first doping type. (Ex. 1011, ¶0113)(Ex. 1002, ¶92).
`
`Specifically, there are n-type doping regions 58 and 54 in the active region. (Ex.
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`1011, ¶0113)(Ex. 1002, ¶92). N-type doping is opposite in conductivity to the first
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`doping type. (Ex. 1011, ¶¶0060, 0110-0113)(Ex. 1002, ¶92). The first doping type
`
`was p-type, as explained above under limitation [1b]. (Ex. 1002, ¶92).
`
` Transistors can be formed within the active region. (Ex. 1002, ¶93).
`
`Specifically, the active region has a “read-out transistor” with a “gate electrode 52”
`
`(Ex. 1011, ¶0113), which is formed from n-type source and drain regions 58 and 54,
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`as well as p-type channel region under the gate electrode 52. (Ex. 1002, ¶93). This
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`meets the claim language under the Patent Owner’s interpretation of the claim. (Ex.
`
`1014, p. 33). Furthermore, an amplifier and other transistors are found in each pixel
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`region (Ex. 1011, ¶¶0113, 0057-0058, 0001, Fig. 3), making it obvious to form these
`
`in the same “active region” to maximize photodiode area by avoiding additional
`
`separation regions. (Ex. 1002, ¶93).
`
`“[1d] a second active region separate from the first active region
`disposed adjacent to the first active region and within which
`transistors can be formed;”
`
`Miyagawa renders obvious a second active region separate from the first
`
`active region disposed adjacent to the first active region and within which
`
`transistors can be formed. (Ex. 1002, ¶94). The second active region is similar
`
`to the first, but in an adjacent pixel cell in the image sensor array. (Ex. 1002, ¶94).
`
`Specifically, Miyagawa teaches an image sensor, including “an imaging
`
`means comprising an array of pixels, each having at least a photodiode for a
`
`photoelectric conversion region….” (Ex. 1011, claim 17, see also claims 22, 24,
`
`¶¶0001-0003, 0015, 0019-0021, 0058, 0110, 0157, Figs. 2-3)(Ex. 1002, ¶95). An
`
`array of pixel cells is shown in Fig. 3 of Miyagawa, reproduced below, which “is a
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`schematic circuit diagram of a typical solid state imaging apparatus comprising an
`
`amplifier type MOS sensor.” (Ex. 1011, ¶0030)(Ex. 1002, ¶95). In Fig. 3 below, a
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`red-dashed box has been added around a single unit cell:
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` (Ex. 1011, Fig. 3, ¶¶0030, 0057-0058)(Ex. 1002, ¶95). Each unit cell has a
`
`photodiode 36 with an associated set of transistors, including the read-out transistor
`
`connected directly to the photodiode. (Ex. 1011, ¶¶0057-0058)(Ex. 1002, ¶95).
`
`As is obvious from Fig. 3 and associated teachings in Miyagawa, each unit
`
`cell containing a photodiode and transistors is adjacent to multiple other unit cells.
`
`(Ex. 1011, Fig. 3, ¶¶0057-0058)(Ex. 1002, ¶96). This was obvious both from the
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`direct teachings of Miyagawa (Ex. 1011, claims 17, 22, 24, ¶¶0001-0003, 0019-
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`0021, 0058, 0110, 0157, Figs. 2-3)(Ex. 1002, ¶96), and because this was standard
`
`operation for an image sensor in the relevant timeframe. (Ex. 1002, ¶96).
`
`An additional active region, containing a photodiode with n-type regions 58
`
`and 54 as well as a read-out transistor (having the same characteristics explained
`
`above for the first active region under element [1c]) is obviously found within each
`
`unit cell. (Ex. 1011, ¶¶0058-0059, 0110-0111)(Ex. 1002, ¶¶97). The active region
`
`in a unit pixel cell is obviously separated from adjacent unit pixels by oxide portions
`
`50 and inter-pixel separation regions. (Ex. 1011, ¶¶0061, 0111, 0130)(Ex. 1002,
`
`¶¶97).
`
`Miyagawa thus renders obvious a second active region separate from the
`
`first active region disposed adjacent to the first active region and within which
`
`transistors can be formed, in the form of the active region of an adjacent pixel
`
`cell. (Ex. 1002, ¶98).
`
`“[1e] transistors formed in at least one of the first active region or
`second active region; and”
`
`As discussed above under limitations [1c] and [1d], at least a read-out
`
`transistor with source and drain regions 58 and 54 is formed in each of the first and
`
`second active regions. This meets the claim language under the Patent Owner’s
`
`interpretation of the claim. (Ex. 1011, ¶¶0113, 0057-0058, 0001, Fig. 3)(Ex. 1002,
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`¶99)(Ex. 1014, p. 8)(Patent Owner arguing “According to claim 842:1, there may be
`
`multiple active regions (i.e., the first and second active regions), where a transistor
`
`is formed in at least one of them (i.e., transistors formed in at least one of the active
`
`regions).”)(Emphasis added).
`
`Furthermore, an amplifier and other transistors are found in each pixel region
`
`(Ex. 1011, ¶¶0113, 0057-0058, 0001, Fig. 3), making it obvious to form these in the
`
`same “active region” to maximize photodiode area by avoiding additional separation
`
`regions. (Ex. 1002, ¶99).
`
`“[1f] at least a portion of at least one of the first and second active
`regions having at least one graded dopant concentration to aid
`carrier movement from the first surface to the second surface of the
`substrate.”
`
`Miyagawa renders obvious a portion of the first active region having at
`
`least one graded dopant concentration to aid carrier movement from the first
`
`surface to the second surface of the substrate. Specifically, Miyagawa teaches a
`
`dopant profile as shown in connection with the Seventh Embodiment, in order to
`
`achieve a high dynamic range. (Ex. 1011, ¶¶0124-0125)(Ex. 1002, ¶100). The
`
`graded dopant profile is shown in Fig. 16, reproduced below, where the left side of
`
`the figure represents the surface of the device (“A”, see Fig. 14), with increasing
`
`depth to the right-hand side of the device.
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`(Ex. 1011, Fig. 16, ¶¶0043, 0127, 0131-0132)(Ex. 1002, ¶100). As can be seen from
`
`the Figure, there is no portion of the dopant profile that is not graded, as would be
`
`expected from Miyagawa’s description of the processes involved. (Ex. 1011,
`
`¶¶0124-0133)(Ex. 1002, ¶100).
`
`Under the Patent Owner’s claim construction apparent from both its claim
`
`construction briefing and its infringement contentions,1 Miyagawa teaches that the
`
`
`1 (Ex. 1014, pp. 26)(patent owner’s claim construction briefing, interpreting all
`
`claim terms in all asserted patents containing “to aid the movement” of carriers,
`
`
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`graded dopant concentrations aid carrier movement from the first surface to the
`
`second surface of the substrate, because graded dopant profiles of Miyagawa move
`
`carriers downward in the device. Specifically, Miyagawa teaches that the dopant
`
`profile shown in Fig. 16 results in a potential function as shown in Fig. 17,
`
`reproduced here:
`
`
`stating “[t]he claim even says where the movement occurs: it is in the drift