( 12 ) United States Patent
`Rao
`
`US 11,121,222 B2
`( 10 ) Patent No .:
`( 45 ) Date of Patent :
`Sep. 14 , 2021
`
`US011121222B2
`
`( 54 )
`
`( 71 )
`
`( * ) Notice :
`
`SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`Applicant : GREENTHREAD , LLC , Dallas , TX
`( US )
`( 72 ) Inventor : G.R. Mohan Rao , Allen , TX ( US )
`( 73 ) Assignee : GREENTHREAD , LLC , Dallas , TX
`( US )
`Subject to any disclaimer , the term of this
`patent is extended or adjusted under 35
`U.S.C. 154 ( b ) by 0 days .
`( 21 ) Appl . No .: 16 / 947,294
`( 22 ) Filed :
`Jul . 27 , 2020
`( 65 )
`Prior Publication Data
`Jan. 7 , 2021
`US 2021/0005716 A1
`Related U.S. Application Data
`Continuation of application No. 16 / 717,950 , filed on
`Dec. 17 , 2019 , now Pat . No. 10,734,481 , which is a
`( Continued )
`
`( 60 )
`
`( 51 ) Int . Ci .
`HOIL 29/10
`HOIL 27/11524
`
`( 52 ) U.S. CI .
`CPC
`
`( 2006.01 )
`( 2017.01 )
`( Continued )
`HOIL 29/1095 ( 2013.01 ) ; HOIL 27/11521
`( 2013.01 ) ; HOIL 27/11524 ( 2013.01 ) ;
`( Continued )
`( 58 ) Field of Classification Search
`CPC
`
`( Continued )
`
`HO1L 29/1095
`
`( 56 )
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,001,864 A
`4,160,985 A
`
`1/1977 Gibbons
`7/1979 Kamins et al .
`( Continued )
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`
`3/1989
`s6482563 A
`2/2003
`2003051551 A
`( Continued )
`
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`P.D. Moor , Advanced CMOS - based pixel sensors , https : // indico .
`cem.ch/event/122027/contributions/88236/attachments/69340/99377/
`FEEimecPdM.pdf , 2011 , 41 pages .
`( Continued )
`Primary Examiner — Ajay Arora
`( 74 ) Attorney , Agent , or Firm Gregory M. Howison
`( 57 )
`ABSTRACT
`Most semiconductor devices manufactured today , have uni
`form dopant concentration , either in the lateral or vertical
`device active ( and isolation ) regions . By grading the dopant
`concentration , the performance in various semiconductor
`devices
`be significantly improved . Performance
`can
`improvements can be obtained in application specific areas
`like increase in frequency of operation for digital logic ,
`various power MOSFET and IGBT ICs , improvement in
`refresh time for DRAMs , decrease in programming time for
`nonvolatile memory , better visual quality including pixel
`resolution and color sensitivity for imaging ICs , better
`sensitivity for varactors in tunable filters , higher drive capa
`bilities for JFETs , and a host of other applications .
`44 Claims , 10 Drawing Sheets
`
`Access Transistor
`
`Storage Capacitor or
`Csensor element
`
`H
`
`!!!!
`
`Graded dopant region to pull minority carriers from surface
`
`P substrate
`
`CMOS Substrate for a DRAM or image sensor with one embodiment of the invention
`
`Greenthread Ex. 2064, p. 1 of 17
`Cirrus Logic, et al. v. Greenthread
`IPR2024-000016
`
`

`

`US 11,121,222 B2
`Page 2
`
`( 56 )
`
`Related U.S. Application Data
`continuation of application No. 15 / 590,282 , filed on
`May 9 , 2017 , now Pat . No. 10,510,842 , which is a
`continuation of application No. 14 / 931,636 , filed on
`Nov. 3 , 2015 , now Pat . No. 9,647,070 , which is a
`continuation of application No. 14 / 515,584 , filed on
`Oct. 16 , 2014 , now Pat . No. 9,190,502 , which is a
`continuation of application No. 13 / 854,319 , filed on
`Apr. 1 , 2013 , now abandoned , which is a continuation
`of application No. 11 / 622,496 , filed on Jan. 12 , 2007 ,
`now Pat . No. 8,421,195 which is a division of
`application No. 10 / 934,915 , filed on Sep. 3 , 2004 ,
`now abandoned .
`( 51 ) Int . Ci .
`HOIL 27/146
`HOIL 27/11521
`HOIL 29/739
`HOIL 29/36
`HOIL 27/02
`HOIL 27/108
`( 52 ) U.S. CI .
`CPC
`
`( 2006.01 )
`( 2017.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`( 2006.01 )
`HOIL 27/14643 ( 2013.01 ) ; HOIL 29/36
`( 2013.01 ) ; HOIL 29/7395 ( 2013.01 ) ; HOIL
`27/0214 ( 2013.01 ) ; HOIL 27/10844 ( 2013.01 )
`( 58 ) Field of Classification Search
`USPC
`257/25
`See application file for complete search history .
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`
`Greenthread Ex. 2064, p. 2 of 17
`Cirrus Logic, et al. v. Greenthread
`IPR2024-000016
`
`

`

`US 11,121,222 B2
`Page 3
`
`( 56 )
`
`References Cited
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`IPR2020-00288 – Exhibit 2007 – Minutes for Markman Hearing
`Held via Video Conference Before U.S. District Judge Rodney
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`( Invalidity Contention based on U.S. Pat . No.6,384,431 to Takahashi .
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`ment , Greenthread , LLC v . Samsung Electronics Co. , Ltd. , et al . ,
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`struction Brief - District Court .
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`dix A of Samsung Electronics Co. , Ltd.'s Invalidity Contentions .
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`
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`nology .
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`* cited by examiner
`
`Greenthread Ex. 2064, p. 3 of 17
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`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 1 of 10
`
`US 11,121,222 B2
`
`Cm
`
`
`
`( per
`
`
`
`Dopant Concentration
`
`1 Collector
`
`1
`
`7
`$
`3
`5
`3
`t
`
`Emitter
`
`3
`t
`7
`6
`
`5
`B
`7
`4
`1
`
`BASE
`
`Distance
`
`
`
`Figure 1 Prior Art
`
`
`
`Creation ( Dopant Concentration per
`
`
`
`
`
`
`
`Greenthread Ex. 2064, p. 4 of 17
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`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 2 of 10
`
`US 11,121,222 B2
`
`GATE
`
`Emitter
`
`P
`
`uniform ) .
`
`
`
`
`concentration is n epitaxial drift region ( n - dopant
`
`Collector
`
`
`
`N + buffer layer P - t substrate
`
`
`
`FIGURE 2 Prior art
`
`TEZLEREK
`
`Greenthread Ex. 2064, p. 5 of 17
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`

`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 3 of 10
`
`US 11,121,222 B2
`
`#
`
`
`
`Active devices
`
`? } I
`
`} ?? i
`
`P well
`
`mm
`
`n well
`
`XXXT
`
`P well
`
`P substrate
`
`
`
`
`
`
`
`Prior art Twin well CMOS for a CMOS integrated circuit
`
`
`
`
`
`
`
`
`
`FIGURE JA
`
`Greenthread Ex. 2064, p. 6 of 17
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`IPR2024-000016
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`

`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 4 of 10
`
`US 11,121,222 B2
`
`Tunnel Insulator
`
`layer ,
`
`? ?
`
`
`
`Storage gate ( for program / erase )
`
`Access Transistor
`
`P substrate
`
`
`
`Prior art for a two - device EEPROM memory cell
`
`
`
`
`
`FIGURE 3B
`
`Greenthread Ex. 2064, p. 7 of 17
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`IPR2024-000016
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`

`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 5 of 10
`
`US 11,121,222 B2
`
`
`
`Storage capacitor
`
`N +
`
`N +
`
`Access Transistor
`
`P substrate
`
`
`
`
`
`FIGURE 3C Prior art for a 1T - IC DRAM memory cell
`
`
`
`
`
`Greenthread Ex. 2064, p. 8 of 17
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`IPR2024-000016
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`

`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 6 of 10
`
`US 11,121,222 B2
`
`N *
`
`Nato
`
`N +
`
`Control / Select Transistor
`
`Control / Select Transistor
`
`Storage
`
`Storage
`
`Storage
`
`w P substrate
`
`FIGURE 3D Prior art for a NAND flash memory cell
`
`
`
`
`
`
`
`
`
`Note : Control / Sect transistors have a single insulator - traditional
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Storage nodes have a stacked gate structure , typically with a floating gate and control gate comprising the stack .
`
`
`
`
`
`MOS transistor .
`
`Greenthread Ex. 2064, p. 9 of 17
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`

`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 7 of 10
`
`US 11,121,222 B2
`
`GATE
`
`P +
`
`nepitaxial drift region
`
`
`graded ) .
`
`( n - dopant concentration is
`
`substrate b Collector
`Pot
`
`
`N + buffer layer
`
`
`
`FIGURE 4 A dopant - concentration grinded drift region in a IGBT
`
`
`
`
`
`Greenthread Ex. 2064, p. 10 of 17
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`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 8 of 10
`
`US 11,121,222 B2
`
`P well
`
`n well
`
`w
`
`
`
`Active devices
`
`
`
`Graded dopant n layer
`
`P well
`
`w
`
`WANAWAAMURU
`
`www P substrate
`
`AYAM
`
`
`
`
`
`FIGURE 5A A CMOS Substrate for digital , mixed , signal , and senors IC's
`
`
`
`
`
`Greenthread Ex. 2064, p. 11 of 17
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`

`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 9 of 10
`
`US 11,121,222 B2
`
`HALAL
`
`P substrate
`
`
`
`
`
`FIGURE 5B CMOS Substrate for a DRAM or image sensor , with one embodiment of the invention
`
`
`
`
`
`
`
`
`
`Storage Capacitor or sensor element
`
`ni
`
`
`
`Access Transistor
`
`1111
`
`
`
`
`
`
`
`Graded dopant region to pull minority carriers from surface
`
`
`
`
`
`
`
`Greenthread Ex. 2064, p. 12 of 17
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`U.S. Patent
`
`Sep. 14 , 2021
`
`Sheet 10 of 10
`
`US 11,121,222 B2
`
`Control / Select Transistor
`
`N *
`
`w ***
`
`: . * *
`
`?
`
`Storage
`
`Control / Sect Transistor
`
`
`Graded dopant
`
`
`
`
`
`
`
`
`
`
`region Accelerates carriers towards surface during programming
`
`P substrate
`
`
`
`
`
`FIGURE 5C CMOS Substrate for a NAND flash device to improve programming times
`
`
`
`
`
`
`
`Greenthread Ex. 2064, p. 13 of 17
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`US 11,121,222 B2
`
`5
`
`20
`
`1
`SEMICONDUCTOR DEVICES WITH
`GRADED DOPANT REGIONS
`
`2
`hole recombination as fast as possible in n - channel IGBT )
`necessitate different dopant gradients either in the same
`layer at different positions , or at the interfaces of similar or
`dissimilar layers .
`CROSS - REFERENCE TO RELATED
`Retrograde wells have been attempted , with little success ,
`APPLICATIONS
`to help improve soft error immunity in SRAMs and visual
`quality in imaging circuits . FIG . 3A shows a typical CMOS
`This application is a Continuation of U.S. patent appli-
`VLSI device employing a twin well substrate , on which
`cation Ser . No. 16 / 717,950 , filed Dec. 17 , 2019 , which this
`active devices are subsequently fabricated . FIGS . 3B , 3C ,
`a Continuation of U.S. patent application Ser . No. 15/590 ,
`282 , filed May 9 , 2017 , which is a Continuation of U.S. 10 and 3D illustrate device cross sections , as practiced today .
`patent application Ser . No. 14 / 931,636 , filed Nov. 3 , 2015 ,
`Retrograde and halo wells have also been attempted to
`which is Continuation of U.S. patent application Ser . No.
`improve refresh time in DRAMs ( dynamic random - access
`14
`, 584 , filed Oct. 16 , 2014 , which is a Continuation of
`memories ) , as well as , reducing dark current ( background
`U.S. patent application Ser . No. 13 / 854,319 filed Apr. 1 ,
`2013 , which is a Continuation of Ser . No. 11 / 622,496 , filed 15 noise ) and enhance RGB ( Red , Green , Blue ) color resolution
`in digital camera ICs . Most of these techniques either divert
`Jan. 12 , 2007 , which is a Divisional of U.S. patent applica
`the minority carriers away from the active regions of critical
`tion Ser . No. 10 / 934,915 , filed Sep. 3 , 2004. The disclosures
`charge storage nodes at the surface , or , increase minority
`of which are incorporated herein by reference in their
`carrier density locally as the particular application requires .
`entirety .
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`TECHNICAL FIELD
`For a more complete understanding of the present inven
`This present invention relates to all semiconductor
`tion , and the advantages thereof , reference is now made to
`devices and systems . Particularly it applies to diffused
`diodes , avalanche diodes , Schottky devices , power MOS 25 the following descriptions taken in conjunction with the
`transistors , JFET's , RF bipolar transistors , IGBTs ( Insulated
`accompanying drawings , in which :
`Gate Bipolar Transistors ) , varactors , digital VLSI , mixed
`FIG . 1 illustrates the relative doping profiles of emitter ,
`signal circuits and sensor devices including camera ICs
`base and collector for the two most popular bipolar junction
`employing CCD ( Charge Coupled Device ) as well as CMOS
`transistors : namely , uniform base ( “ A ” ) and graded base
`technologies .
`30 ( “ B ” ) ;
`FIG . 2 illustrates the cross section of a commercial IGBT
`with a uniform epitaxial drift region ( base ) ;
`BACKGROUND
`FIGS . 3A , 3B , 3C , and 3D illustrate cross sections of
`Bipolar Junction Transistors ( BJT ) are classified as minor-
`commonly used prior art CMOS silicon substrates ; FIG . 3A
`ity carrier devices because minority carriers are the principle 35 showing a typical prior art IC with two wells ( one n well in
`device conduction mechanism . However , majority carriers
`which p - channel transistors are subsequently fabricated and
`also play a small but finite role in modulating the conduc-
`one p well in which n - channel transistors are subsequently
`tivity in BJTs . Consequently , both carriers ( electrons and
`fabricated ) ; FIG . 3B showing a prior art EEPROM ( Elec
`holes ) play a role in the switching performance of BJTs . The
`tronically Erasable Programmable Read - Only Memory )
`maximum frequency of operation in BJTs is limited by the 40 memory cell having a tunnel insulator ; FIG . 3C showing a
`base transit time as well as the quick recombination of the
`prior art DRAM memory cell ; and FIG . 3D showing a prior
`majority carriers when the device is switched off ( prior to
`art NAND flash memory cell ;
`beginning the next cycle ) . The dominant carrier mechanism
`FIG . 4 illustrates the cross section of an IGBT , using one
`in BJTs is carrier diffusion . The carrier drift current com-
`embodiment of the invention described here , where the
`ponent is fairly small , especially in uniformly doped base 45 dopant is optimally graded in the epitaxial drift region ; and
`BJTs . Efforts have been made in graded base transistors to
`FIGS . 5A , 5B , and 5C illustrate the cross sections of a
`create an aiding drift field to enhance the diffusing minority
`CMOS silicon substrate with two wells and an underlying
`carrier's speed from emitter to collector . However , most
`layer using embodiments of the invention to improve per
`semiconductor devices , including various power MOSFETs
`formance in each application — VLSI logic , DRAM / image
`( traditional , DMOS , lateral , vertical and a host of other 50 IC , nonvolatile memory IC .
`configurations ) , IGBT's ( Insulated Gated Base Transistors ) ,
`still use a uniformly doped ‘ drift epitaxial region in the
`DETAILED DESCRIPTION
`base . FIG . 1 shows the relative doping concentration versus
`distance in a BJT . FIG . 2 shows the uniformly doped epi
`The relative doping concentrations of emitter and collec
`region in an IGBT . In contrast to BJTS , MOS devices are 55 tor regions varies from 1018 to 102 ° / cm " , whereas the base
`majority carrier devices for conduction . The conduction is
`region is 1014 to 1016 / cm3 depending on the desired char
`channel dominated . The channel can be a surface in one
`acteristics of the BJT . In graded base p - n - p transistors , the
`plane in planar devices . The surface can also be on the
`donor dopant concentration may be 10 to 100x at the
`sidewalls in a vertical device . Other device architectures to
`emitter - base junction , relative to the base - collector junction
`combine planar and vertical conductions are also possible . 60 ( 1x ) . The gradient can be linear , quasi linear , exponential or
`The maximum frequency of operation is dictated primarily
`complimentary error function . The relative slope of the
`by source - drain separation distance . Most MOS devices use
`donor concentration throughout the base creates a suitable
`a uniformly doped substrate ( or a well region ) . When a
`aiding drift electric field , to help the holes ( p - n - p transistor )
`MOSFET is optimally integrated with a BJT in a monolithic
`transverse from emitter to collector . Since the aiding drift
`fashion , an IGBT results . The IGBT inherits the advantages 65 electric field helps hole conduction , the current gain at a
`of both MOSFET and BJT . It also brings new challenges
`given frequency is enhanced , relative to a uniformly - doped
`because the required characteristics ( electron transit and
`( base ) BJT . The improvement in cut - off frequency ( or ,
`
`Greenthread Ex. 2064, p. 14 of 17
`Cirrus Logic, et al. v. Greenthread
`IPR2024-000016
`
`

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`US 11,121,222 B2
`
`35
`
`3
`4
`frequency at unity gain , fz ) can be as large as 2x - 5x . Similar
`towards the surface when programming of memory cells is
`performance improvements are also applicable to n - p - n
`executed . The graded dopant can also be used to fabricate
`superior Junction Field - Effect transistors where the " channel
`transistors .
`As illustrated in FIG . 4 , in one embodiment according to
`pinch - off ” is controlled by a graded channel instead of a
`the invention , a donor gradient is established from the 5 uniformly doped channel ( as practiced in the prior art ) .
`emitter - drift epitaxial base region junction of the punch
`One of ordinary skill and familiarity in the art will
`through IGBT , to the drift epitaxial base region nt buffer
`recognize that the concepts taught herein can be customized
`layer boundary ( electrons in this case are accelerated in their
`and tailored to a particular application in many advanta
`transit from emitter to collector ) . The “ average ” base resis
`geous ways . For instance , minority carriers can be channeled
`tance is optimized so that conductivity modulation and 10 to the surface to aid programming in nonvolatile memory
`lifetime ( for minority carriers ) in the base region are not
`devices ( NOR , NAND , multivalued - cell ) . Moreover , single
`compromised . By sweeping the carriers towards the nt
`well , and triple - well CMOS fabrication techniques can also
`buffer region a number of advantages are obtained . First , the
`be optimized to incorporate these embodiments individually
`toff as
`frequency of operation ( combination of ton and
`is
`known in the IGBT commercial nomenclature ) can be 15 and collectively . Any modifications of such embodiments
`( described here ) fall within the spirit and scope of the
`enhanced . Second , and maybe more importantly , during topy
`invention . Hence , they fall within the scope of the claims
`holes can be recombined much quicker at the nt buffer layer ,
`compared to the uniformly doped n'epitaxial drift region by
`described below .
`establishing a different dopant gradient near the nt buffer
`Although the invention has been described with reference
`layer . It should be noted that the drift region can also be a 20 to specific embodiments , these descriptions are not meant to
`non - epitaxial silicon substrate . Although epitaxy enhances
`be construed in a limiting sense . Various modifications of the
`lifetime , it is not mandatory . Different layers of dopant
`disclosed embodiments , as well as alternative embodiments
`regions can be transferred through wafer to wafer bonding
`of the invention will become apparent to persons skilled in
`( or other similar transfer mechanisms ) for eventual device
`the art upon reference to the description of the invention . It
`fabrication . The “ reverse recovery time ” for an IGBT is 25 should be appreciated by those skilled in the art that the
`significantly improved due to the optimized graded dopant
`conception and the specific embodiment disclosed may be
`in the so called “ drift region ” as well as at the interfaces of
`readily utilized as a basis for modifying or designing other
`the drift region . Graded dopants can also be implemented in
`structures for carrying out the same purposes of the present
`the nt buffer layer as well as other regions adjacent to the
`invention . It should also be realized by those skilled in the
`respective layers . Two important performance enhance- 30 art that such equivalent constructions do not depart from the
`ments are the result of dopant gradients . For example , in an
`spirit and scope of the invention as set forth in the appended
`n - channel IGBT , electrons can be swept from source to drain
`claims .
`rapidly , while at the same time holes can be recombined
`It is therefore , contemplated that the claims will cover any
`closer to the nt buffer layer . This can improve ton and toffin
`such modifications or embodiments that fall within the true
`the same device .
`scope of the invention .
`As illustrated in FIGS . 5A , 5B , and 5C , donor gradient is
`also of benefit to very large scale integrated circuits
`( VLSI ) —VLSI logic , DRAM , nonvolatile memory like
`NAND flash . Spurious minority carriers can be generated by
`clock switching in digital VLSI logic and memory ICs . 40
`These unwanted carriers can discharge dynamically - held
`“ actively held high ” nodes . In most cases , statically - held
`nodes ( with Vce ) cannot be affected . Degradation of refresh
`time in DRAMs is one of the results , because the capacitor
`holds charge dynamically . Similarly , degradation of CMOS 45
`digital images in digital imaging ICs is another result of the
`havoc caused by minority carriers . Pixel and color resolution
`can be significantly enhanced in imaging ICs with the
`embodiments described herein . Creating “ subterranean ”
`recombination centers underneath the wells ( gold doping , 50
`platinum doping ) as is done in some high - voltage diodes is
`not practical for VLSI circuits . Hence , a novel technique is
`described herein which creates a drift field to sweep these
`unwanted minority carriers from the active circuitry at the
`surface into the substrate in a monolithic die as quickly as 55
`possible . In a preferred embodiment , the subterranean
`n - layer has a graded donor concentration to sweep the
`minority carriers deep into the substrate . One or more of
`such layers can also be implemented through wafer to wafer
`bonding or similar “ transfer ” mechanisms . This n - layer can 60
`be a deeply - implanted layer . It can also be an epitaxial layer .
`As desired , the n well and p wells can also be graded or
`retrograded in dopants to sweep those carriers away from the
`surface as well . The graded dopant can also be implemented
`in surface channel MOS devices to accelerate majority 65
`carriers towards the drain . To decrease programming time in
`nonvolatile memory devices , carriers should be accelerated
`
`What is claimed is :
`1. A VLSI semiconductor device , comprising :
`a substrate of a first doping type at a first doping level
`having a surface ;
`a first active region disposed adjacent the surface with a
`second doping type opposite in conductivity to the first
`doping type and within which transistors can be
`formed ;
`a second active region separate from the first active region
`disposed adjacent to the first active region and within
`which transistors can be formed ;
`transistors formed in at least one of the first active region
`or second active region ;
`at least a portion of at least one of the first and second
`active regions having at least one graded dopant con
`centration to aid carrier movement from the first and
`second active regions towards an area of the substrate
`where there are no active regions ; and
`at least one well region adjacent to the first or second
`active region containing at least one graded dopant
`region , the graded dopant region to aid carrier move
`ment from the surface towards the area of the substrate
`where there are no active regions , wherein at least some
`of the transistors form digital logic of the VLSI semi
`conductor device .
`2. The VLSI semiconductor device of claim 1 , wherein
`the substrate is a p - type substrate .
`3. The VLSI semiconductor device of claim 1 , wherein
`the substrate has epitaxial silicon on top of a nonepitaxial
`substrate .
`
`Greenthread Ex. 2064, p. 15 of 17
`Cirrus Logic, et al. v. Greenthread
`IPR2024-000016
`
`

`

`US 11,121,222 B2
`
`30
`
`5
`6
`at least one well region adjacent to the first or second
`4. The VLSI semiconductor device of claim 1 , wherein
`active region containing at least one graded dopant
`the first active region and second active region contain
`region , the graded dopant region to aid carrier move
`digital logic formed by one of either p - channel and n - chan-
`nel devices .
`ment from the surface to the area of the substrate where
`there are no active regions , and wherein the graded
`5. The VLSI semiconductor device of claim 1 , wherein 5
`dopant concentration is linear , quasilinear , error func
`the first active region and second active region contain either
`tion , complementary error function , or any combina
`p - channel or n - channel devices in n - wells or p - wells ,
`respectively , and each well has at least one graded dopant .
`tion thereof .
`22. The VLSI semiconductor device of claim 21 , wherein
`6. The VLSI semiconductor