d
`
`United States Patent (19)
`Nishizawa et al.
`
`11
`45
`
`US005384476A
`
`Patent Number:
`Date of Patent:
`
`5,384,476
`Jan. 24, 1995
`
`54 SHORT CHANNEL MOSFET WITH BURIED
`ANTI-PUNCH THROUGH REGION
`75) Inventors:
`Jun-ichi Nishizawa; Tadahiro Ohmi,
`both of Sendai, Japan
`Zaidan Hojin Handotai Kenkyu
`Shinkokai, Sendai, Japan
`21 Appl. No.: 62,333
`22 Filed:
`Jun. 9, 1987
`
`73) Assignee:
`
`63
`
`Related U.S. Application Data
`Continuation of Ser. No. 179,782, Aug. 20, 1980, aban
`doned.
`Foreign Application Priority Data
`(30)
`Aug. 25, 1979 JP
`Japan................................ 54-108377
`Sep. 7, 1979 JP
`Japan ...
`........ 54-115491
`5ll Int. Cl. ........................................... H01, 27/108
`52 U.S.C. .................................... 257/345; 257/297;
`257/407
`58) Field of Search ........................ 257/407, 297, 345
`56
`References Cited
`U.S. PATENT DOCUMENTS
`3,673,471 6/1972 Klein et al. ........................... 357/59
`4,247,862 1/1981 Klein et al. .........
`357/23 C
`4,329,706 5/1982 Crowder et al. .................. 357/23 S
`4,334,235 6/1982 Nishizawa ............................. 357/41
`FOREIGN PATENT DOCUMENTS
`53-80172 7/1978 Japan ................................ 357/23 R
`53-84571 7/1978 Japan ................................ 357/23 R
`53-141585 12/1978 Japan ................................ 357/23 D
`
`OTHER PUBLICATIONS
`Konaka et al, "Suppression of Anomalous Drain Cur
`rent ... ', Japan. J. Appl. Physics, Suppl. 18-1, 1979,
`pp. 27-33.
`Nishiuchi et al, IEEE International Electron Dev.
`Meeting, Dec. 1978, Technical Digest pp. 26-29.
`Dennard, et al, IEEE.J. of Solid State Circuits, vol. SC
`9 No. 5, Oct. 1974, pp. 256-267.
`Tasch, Jr., etal, IEEE Trans. on Electron Dev. vol. ED
`25 No. 1, Jan. 1978, pp. 33-41 (not including p. 39).
`Primary Examiner-William D. Larkins
`Attorney, Agent, or Firm-Cushman, Darby & Cushman
`57
`ABSTRACT
`A semiconductor device having a source region, a drain
`region and a channel region which are formed in a
`surface portion of a semiconductor substrate, and a gate
`formed with a material having a relatively high built-in
`voltage relative to the source region. This semiconduc
`tor device may further include, in the semiconductor
`substrate to extend along the channel region, a highly
`doped region having a conductivity type opposite to
`that of the source region. This highly-closed region may
`have an impurity concentration gradient which is
`greater toward its portion facing the abovesaid surface
`of the substrate. These arrangements serve to prevent
`extinction of memory due to current leakage during
`absence of bias voltage which otherwise would develop
`in semiconductor devices having short-channel and thin
`gate oxide layer, and due to irradiation of alpha-particle
`onto the device.
`
`19 Claims, 18 Drawing Sheets
`
`
`
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`

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`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 2 of 18
`
`5,384,476
`
`
`
`Ol ( 6 8 1 9 9_t2_2_3|
`
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`
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`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 3 of 18
`
`5,384,476
`
`FIG. 6
`
`Id
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`to 10
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`g o
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`Jsub = 7 (S)-cm)
`xi = O5 (plm)
`L = I (plm)
`Leff = O5(plm)
`Ve = O(V)
`
`5
`
`4.
`3
`2
`DRAIN VOLTAGE VD
`FIG. 7
`
`Vsub
`T
`
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`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 4 of 18
`
`5,384,476
`
`FIG. 8
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`y
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`a
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`fsub= 7 (S)-cm)
`xi = 0.5 (plm)
`L = i (um)
`
`a
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`o EXPERMENT
`+ CALCULATE
`
`-
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`SUBSTRATE BIAS VOLTAGE Vsub
`
`FIG. 9
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`FIG. IO
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`X
`DISTANCE
`
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`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 5 of 18
`
`5,384,476
`
`O
`1.
`O
`O
`(f)
`
`FIG. / /
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`fsub= 7 (2-cm)
`xi = O5 (plm)
`L = I (pum)
`Leff = O5 (plm)
`
`O
`
`-
`
`-2
`-3
`-4
`SUBSTRATE BIAS VOLTAGE Visub
`
`-5
`
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`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 6 of 18
`
`5,384,476
`
`32
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`Greenthread Ex. 2060, p. 7 of 32
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`IPR2024-00016
`
`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 7 of 18
`
`5,384,476
`
`
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`Greenthread Ex. 2060, p. 8 of 32
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`IPR2024-00016
`
`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 8 of 18
`
`5,384,476
`
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`Greenthread Ex. 2060, p. 9 of 32
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`IPR2024-00016
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`

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`Greenthread Ex. 2060, p. 11 of 32
`Cirrus Logic, et al. v. Greenthread
`IPR2024-00016
`
`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 11 of 18
`
`5,384,476
`
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`Greenthread Ex. 2060, p. 12 of 32
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`IPR2024-00016
`
`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 12 of 18
`
`5,384,476
`
`5
`d
`d
`CHANNEL MPURITY CONCENTRATION NA(cm)
`
`
`
`Greenthread Ex. 2060, p. 13 of 32
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`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 13 of 18
`
`5,384,476
`
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`Greenthread Ex. 2060, p. 14 of 32
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`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 14 of 18
`
`5,384,476
`
`FIG. 3O
`
`FIG. 3/
`
`FIG. 32
`
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`Greenthread Ex. 2060, p. 15 of 32
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`IPR2024-00016
`
`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 15 of 18
`
`5,384,476
`
`
`
`XO SSO 9M3N3
`
`Greenthread Ex. 2060, p. 16 of 32
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`IPR2024-00016
`
`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 16 of 18
`
`5,384,476
`
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`Greenthread Ex. 2060, p. 17 of 32
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`IPR2024-00016
`
`

`

`U.S. Patent
`
`Jan. 24, 1995
`
`sheet 17 of 18
`
`5,384,476
`
`FIG. 36
`
`
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`
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`
`Greenthread Ex. 2060, p. 18 of 32
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`U.S. Patent
`
`Jan. 24, 1995
`
`Sheet 18 of 18
`
`5,384,476
`
`47
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`Greenthread Ex. 2060, p. 19 of 32
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`

`

`5
`
`10
`
`1.
`
`5,384,476
`2
`trode which is comprised of an in type polysilicon, and
`SHORT CHANNEL MOSFET WITH BURED
`which is formed by relying on a known usual process of
`ANTI-PUNCH THROUGH REGION
`manufacture. It should be understood that this in type
`polysilicon gate region may be substituted by a metal
`This is a continuation of application Ser. No. 179,782,
`gate region such as aluminum, molybdenum and tung
`filed Aug. 20, 1980, which was abandoned upon the
`sten. Numeral 15 represents a gate oxide film, 16 a field
`filing hereof.
`oxide film, and 17 a PSG film. Numerals 12a and 13a
`represent a source electrode and a drain electrode, re
`RELATED APPLICATIONS
`spectively, which are made of a metal such as alumi
`This application is related to the Nishizawa applica
`num. Numeral 18 represents a pi type region which
`tion Ser. No. 20,498, filed Mar. 14, 1979, Nishizawa etal
`serves as a channel-stopper region for inhibiting the
`application Ser. No. 167,343 filed Jul. 10, 1980, which is
`tendency of formation of a current channel between the
`a continuation of the abandoned parent application Ser.
`field oxide film 16 and p type substrate 11. It should be
`No. 867,298 filed Jan. 5, 1978 and the Nishizawa et al
`understood here that the gate oxide film 15 and like
`application Ser. No. 238,968 filed Feb. 27, 1981, which
`15
`films can locally contain a Si3N4 film. Also, it is usual to
`is a continuation of the abandoned parent application
`provide a passivation film on the surface of the device
`Ser. No. 32,219 filed Apr. 23, 1979.
`shown in FIG. 1.
`BACKGROUND OF THE INVENTION
`By using the MOS-FET having basically the arrange
`ment as shown in FIG. 1, there may be formed a
`FIELD OF THE INVENTION
`d-RAM cell, for example, the following two types of
`The present invention relates to a semiconductor
`arrangements. Instead of providing an electrode di
`device, and more particularly to a semiconductor de
`rectly on one of the two main electrode regions, for
`vice such as an insulation-gate transistor which allows a
`example, on the drain region 13 of this MOS-FET, there
`high packing density integration and effects a good
`may be provided thereon an insulating film made of
`holding of memory contents and which does not make
`25
`SiO2, and an electrode is provided via this insulating
`soft errors induced by alpha-particle irradiation. Also
`film. Alternatively, there may be provided an in type
`the invention concerns such semiconductor devices
`polysilicon layer on the drain region 13, and the surface
`serving as a semiconductor memory and a logic cir
`of this polysilicon layer is oxidized for a very small
`cuitry.
`distance to provide a thin oxide film (SiO2), and an
`A remarkable development is under way in the field
`30
`electrode is provided on this oxide film. The former
`of high packing density integration of semiconductor
`arrangement is such that a capacitor, i.e. a storage ca
`memories, especially in the field of dynamic random
`pacitor, is formed by the nt type region 13, the insulat
`access memory (hereinafter to be referred to as d-RAM)
`ing oxide film and the electrode 13a. The latter arrange
`which refreshes its memory contents at certain time
`ment is such that a capacitor or a storage capacitor is
`intervals. Recently, there have been placed on the mar
`35
`formed by the electrode 13a, the oxide film and then
`ket 64 kilo-bit d-RAMs, and development of 256 kilobit
`type polysilicon layer. Such arrangements each serves
`d-RAMs is under way. High packing density integra
`as a d-RAM cell comprising one transistor and one
`tion of d-RAMs whose circuit arrangement has gone to
`capacitor.
`such an extreme end as will not be simplified easily any
`Experimental samples are made for two kinds of sub
`further than the "one transistor-one capacitor' type is
`40
`strates and gate oxide films having two kinds of thick
`attained only by making the sizes of the respective
`nesses Tax, using the same manufacturing parameters
`structural components extremely fine. Such a trend of
`development has given rise to the tendency for progres
`excepting the channel length L (mask level). The mem
`sively shortening the distance between the source re
`ory retention characteristics of these samples are evalu
`gion and the drain region (hereinafter to be referred to
`ated, and the result is described hereinbelow. The
`45
`as the channel length) in insulation-gate transistors
`source region 12 and the drain region 13 are formed by
`ion-implantation of arsenic (As, implantation voltage:
`(hereinafter to be referred to as MOS transistors). How
`100 kV, dose: 1x1015 cm-2) to a depth of X of about
`ever, in case the channel length of such transistors is
`0.5 pum. Also, there is given a channel doping with
`reduced, there arises the inconvenience that, even when
`boron (B, implantation voltage: 30 kV, dose: 3X1011
`the gate potential of the transistor is zero-biased in order
`50
`cm2). The gate width is set at 100 pm for each sample,
`to render the transistor non-conductive, there flows a
`leakage current between the source region and the drain
`and the thickness Tox of gate oxide film is set at 500 A
`region so that the memory contents will become extin
`and 1000A, respectively, and the resistivity psu, of the
`guished in a very short period of time, and the device
`p type substrate 11 is set at about 7 (2cm and about 20
`will not operate to serve as a memory.
`G2cm, respectively.
`55
`In the currently practiced process of making LSI
`By the use of a circuit arrangement of the above-men
`devices using silicon, it is often the case to arrange a
`tioned d-RAM having a terminal of its storage capacitor
`MOS field effect transistor (hereinafter to be referred to
`Cs grounded as shown in FIG. 2, its memory retention
`as MOS-FET) which is a component of the LSI, in such
`characteristic is evaluated.
`way as mentioned in FIG. 1. In order to cause a high
`In FIG. 2, reference numeral 21 represents a word
`speed operation, this MOS-FET is formed to have an
`line, and 22 a bit line. Numeral 23 represents a MOS
`n-channel structure. In FIG. 1 which represents a prior
`FET T1, and 24 a storage capacitor C. To effect
`art device, a p type region 11 represents a substrate.
`"write-in', a write-in voltage V is applied to the bit
`Also, two main electrodes are provided in a symmetri
`line 22, while a voltage Vois applied to the word line
`cal pattern, so that an nt type region 12 represents, for
`21. In case this MOS-FETT is an n-channel type, these
`65
`example, a source region, and an nt type region 13
`voltages Vw and VG are positive voltages, respectively.
`represents, for example, a drain region. Numeral 14
`When a positive voltage V,is applied to the bit line 22,
`represents a gate region serving as a controlling elec
`it should be understood that when the MOS-FETT is
`
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`5
`
`10
`
`5,384,476
`3
`4.
`rendered conductive by the application of a positive
`other words, with respect to the sample shown in FIG.
`voltage Voto the word line 21, there flows a current to
`5, it should be understood that unless Letris 3.5 um or
`the storage capacitor Cs, and this storage capacitor Csis
`greater, the device will no longer operate as a d-RAM.
`charged to a value represented substantially by
`On the other hand, with the sample shown in FIG. 3, it
`Vw-Vth, wherein Vth represents a threshold voltage of
`will be understood that, if the substrate bias voltage
`the MOS-FETT1. In this state of the FET, electrons
`Vsubis set at -4V, the memory contents are held for a
`are allowed to flow out from the nt type drain region
`sufficient period of time, even if the effective channel
`13 which serves as an electrode of storage capacitor C.,
`length is reduced up to Leif E 1.5 pum. However, even in
`so that this region 13 is positively charged due to short
`this sample shown in FIG. 3, in case the effective chan
`age of electrons therein. Then, the voltage Vog of the
`nellength is reduced to Lef=0.5 pm, the device can no
`word line 21 is set back to zero, and thereafter the volt
`longer be used as a d-RAM. In the sample shown in
`age Vw of the bit line 22 is removed. Whereupon, the
`FIG. 4, even when Vsub= -4V, the memory contents
`write-in operation is completed. In the state that the
`holding time is noted to begin dropping when Leff= 1.5
`memory contents are being retained, there is no need to
`Im.
`apply an external voltage to any one of the terminals of
`As will be understood from the foregoing description
`15
`the memory cell having the circuit arrangement of FIG.
`of samples, in case the channel length is shortened for
`2. As stated above, in this memory content holding
`the purpose of improving the packing density, if the
`state, then type region 13 is short of electrons and is
`channel length is reduced to about L= 1 p.m (Lef=-
`charged positive, and this in type region 13 is reverse
`about 0.5um), the memory content holding time drops
`biased relative to the p type substrate 11. This storing
`sharply so that the device will no longer be operated as
`20
`mode is called an electron-depletion storing mode. Ac
`a d-RAM.
`cordingly, the contents of memory will be preserved for
`Next, explanation will be made of the reasons for the
`an extended period of time. The memory retention time
`phenomenon that, in case the channel length is reduced
`in the electron-depletion storing mode is always longer
`as shown in FIGS. 3 to 5, the memory contents become
`than that in the electron-accumulation storing mode
`extinguished sharply. A reduced length of channel gives
`25
`where the amount of excess electrons is stored in the
`rise to the effect of lowering, due to the effect provided
`nt type storage region.
`by the source and drain regions, the potential barrier
`Although the biasing of the p type substrate 11 of the
`which, in case the channel length is not shortened,
`MOS-FETT has not been described with respect to
`serves to prevent the flow of electrons across the source
`FIG. 2, in case there is the fear that the contents of
`region and the drain region. In a sample having a long
`30
`memory would become extinguished due to a sub-thre
`channel, the height of the potential barrier in the chan
`shold current attributable to a shortened length of the
`nel region is controlled almost solely by both the gate
`effective channel of the MOS-FETT, there is applied
`voltage VG and the substrate voltage Vsub. However, in
`a substrate bias voltage, which is a negative voltage in
`case the length of channel is reduced, the potential
`this example, to prevent such extinguishment of the
`barrier height will become controlled also by the source
`35
`memory contents.
`region potential and the drain region potential. In other
`The memory content holding characteristic is mea
`words, a static induction effect which is noted in a static
`sured in the manner as stated above. Such characteristic
`induction transistor (SIT) begins to appear in the device
`for three different samples is shown in FIGS. 3, 4 and 5,
`having a substantially reduced length of channel, so that
`respectively. These data are observed in a d-RAM cell
`a current will become allowed to flow across the source
`operating at room temperature. The applied voltages
`and the drain regions even without an application of a
`are: Vog=5V, and V=5 V. The memory holding time
`gate voltage. Such current will hereunder be called an
`means a period of time starting from the time at which
`SIT current or a sub-threshold current. In FIG. 6 will
`the word line voltage is returned to zero up to the time
`be shown the relationship between the drain current Id
`when the voltage stored in the storage capacitor Cs has
`and the drain voltage V (a voltage relative to the
`45
`dropped to about. The memory holding time is plotted
`source voltage when the latter is zero) for the sample
`as a function of the effective channel length Lef. This
`shown in FIG. 3 but wherein the channel length L at
`Leif should be noted to be shorter by about 0.5 um as
`mask level is 1 p.m (Lef=0.5 um). The vertical axis
`compared with the channel length at mask level. In
`represents the drain current Id, and the horizontal axis
`FIG. 3, marks (1), (2), (3) and (4) correspond to the
`represents the drain voltage V. FIG. 6 shows the fact
`50
`substrate bias voltage of 0 V, -1 V, -2 V and -4V,
`that, even in case the gate voltage Vog=0, there flows a
`respectively. FIG.3 shows the result of thesapple with
`current Id across the source and drain regions. It is
`its gate oxide film has a thickness Tox=1000A and the
`needless to say that, when the naagnitude of the negative
`resistivity of the p type substrate is psub=7 Ocm.FIG.
`substrate bias voltage Vsubis augmented, the drain cur
`4 is the result of a sample wherein Tox=500 A and
`rent Idwill become smaller. That is, even when the gate
`55
`psub=7 (2cm. FIG. 5 shows the result of a sample
`voltage is set at VG=0, there will begin to flow a cur
`wherein Tox=500 A, and psub=20 Ocm. In all of these
`rent across the source and drain regions when a certain
`samples, the depths of then type source region and the
`amount of voltage is applied therebetween.
`nt type drain region are invariably 0.5 pm, and the
`In a d-RAM which is in the state that a voltage
`doping amounts of the channels by implantation of
`Vn=Vw-Vthis written in the storage capacitor Csand
`60
`boron (B) are identical such as 5-7x1016 cm-3. In
`is stored therein, it should be understood that the volt
`case Lef is long, the memory holding time in each of
`age Vn is being applied across the source and drain
`these samples is long, being about 100 seconds. How
`regions. Accordingly, there naturally flows such drain
`ever, for a shorter Leif, the holding time sharply be
`current Id as that shown in FIG. 6, and thereby the
`comes shorter. In the sample of FIG. 5 in which Leiris
`stored voltage decreases progressively. The process of
`2.5um, the result of observation is such that even by the
`reduction of the stored voltage due to the current flow
`application of a substrate bias voltage Vsub, the memory
`ing across the source and drain regions can be analyzed
`holding time lasts no longer than about 100 usec. In
`easily. Since the device may be expressed in an equiva
`
`Greenthread Ex. 2060, p. 21 of 32
`Cirrus Logic, et al. v. Greenthread
`IPR2024-00016
`
`

`

`5,384,476
`5
`6
`lent circuit as shown in FIG. 7, the voltage stored in the
`wherein:
`storage capacitor Cs will attenuate by the current which
`Vo represents a voltage applied to the gate oxide film
`flows through the MOS-FET T1. By designating the
`15;
`voltage of the storage capacitor Cs as V, the process of
`Vs represents a voltage applied to the p type sub
`attenuation of the voltage can be expressed by the fol
`strate;
`lowing formula:
`NA represents an impurity concentration of the
`p type substrate 11; and
`q represents a unit charge.
`From Formulas (4) and (5), the width W of the deple
`O
`tion layer in the p type substrate 11 and the voltage Vo
`which is applied to the gate oxide film are obtained as
`
`-c-d-
`dt = d.
`
`5
`
`(1)
`
`whereint represents time.
`As will be understood from FIG. 6, the subthreshold
`current Id varies substantially exponentially relative to
`the voltage of the storage capacitor. That is, the sub
`threshold current can be expressed by Id=loe,
`15
`wherein Io and a can vary depending on the substrate
`bias Vsub. The abovementioned Formula (1) under an
`initial condition Vo=Vn can be solved as follows:
`
`l,---.
`
`20
`
`(2)
`
`W.
`T.
`
`5)
`(-, ...(i)}
`
`NAge T.
`
`(6)
`
`(7)
`
`The time required for V to become 1/r of the initial
`voltage V will be:
`
`25
`
`Also, the intensities Eo and Es of electric fields in the
`gate oxide film 15 and in the p type region 11 are ex
`pressed as:
`
`r =
`
`own.
`(e. r - e-am).
`
`(3)
`
`30
`The value obtained from calculation on the basis of
`r=2, and the value obtained from actual measurement
`are shown in FIG. 8. In FIG. 8, the memory-holding
`time is plotted as a function of the substrate bias voltage.
`In this Figure, marko represents the value of measure
`35
`ment, and mark -- represents the value of calculation. It
`will be noted that these two kinds of values are substan
`tially in agreement with each other. More particularly,
`the attenuation of the stored voltage for a device having
`a reduced channel length is brought about by the sub
`threshold current flowing across the source and the
`drain regions. Next, comparison is made between FIG.
`3 and FIG. 4. It will be noted that the memory-holding
`characteristic for a reduced channel device is poor with
`the sample shown in FIG. 4. In other words, the smaller
`45
`the thickness To of the gate oxide film becomes, the
`more the memory-holding characteristic degradates.
`This relationship will be described briefly as follows.
`Referring back to FIG. 1, the gate region 14 of the
`50
`n-channel MOS-FET is formed most frequently with an
`nt type polysilicon. A sectional construction taken in
`one-dimensional direction from the gate region 14
`toward the p type substrate 11 is shown in FIG. 9. The
`thickness of the p type substrate 11 is indicated by d.
`55
`The gate oxide film 15 has a dielectric constant e2 and
`the p type substrate 11 has a dielectric constant e1. The
`potential profile when a reverse bias voltage Va (includ
`ing a built-in potential Vb) is applied across the p type
`substrate 11 and the in type gate electrode 14 is ex
`pressed by the formula:
`
`V = 0 + V,
`
`and
`
`-- v6 - NagW. V. = ... W.
`6.
`N
`Tox
`2e
`
`(4)
`
`5
`
`(5)
`
`(8)
`
`(9)
`
`-age 1 + \ 1 + 2. ...) }
`
`- e22
`
`el
`
`Tox
`
`2
`
`and
`
`NaaTox
`s = e2
`
`W.
`e2
`-1 + V 1 + e T.
`
`2
`
`W - x
`7
`
`-(y).
`
`2e 1 V
`NAq
`
`and represents the width of the depletion layer when
`the voltage Va is applied solely to the p type substrate
`11.
`The potential distribution within the p type substrate
`11 is shown in FIG. 10 where the thickness Tox of the
`gate oxide film is varied. This Figure represents the
`result when the gate potential is maintained at the same
`level of the source potential. The vertical axis repre
`sents the potential, and the horizontal axis represents
`the distance from the gate oxide film 15 up to the p type
`substrate 11. The Figure shows the state in which only
`a built-in potential Vibiis applied, when the substrate bias
`voltage Vsub=0. It should be noted here that Vbi repre
`sents a built-in potential at the junction of the nt type
`region and the p type region. The symbol 0 given at the
`vertical axis represents a source potential. When
`T0, the potential profile takes the curve as indicated
`by G1), and the potential at the interface of the p type
`region is rendered to a same level as that of the source
`potential. As Toxincreases, the potential at the interface
`of the oxide film will increase as indicated by (2). When
`Toso, i.e. when the oxide film has a substantially
`largethickness, the potential curve will assume constant
`patterns as shown by broken lines. Conversely, as Tox
`
`Greenthread Ex. 2060, p. 22 of 32
`Cirrus Logic, et al. v. Greenthread
`IPR2024-00016
`
`

`

`10
`
`5
`
`5,384,476
`7
`8
`decreases, the interface potential approaches the poten
`FIGS. 3 to 5 are charts for explaining the dependency
`tial of the source region. This means that electrons are
`characteristic of memory holding time upon effective
`allowed to enter easily into this lowered potential re
`channel length of the MOS-FET of FIG. 1.
`gion from either the source region or the drain region,
`FIG. 6 is a chart for explaining the dependency char
`so that a current is thus allowed to flow.
`acteristic of drain current upon drain voltage.
`The attempt to develop a short channel structure
`FIG. 7 is a circuit diagram for analyzing memory
`necessitates a further reduction of the thickness of the
`holding characteristics.
`gate oxide film. As a result, the tendency that the sur
`FIG. 8 is a chart for explaining the dependency char
`face potential drops and that accordingly the current is
`acteristic of memory holding time upon substrate bias
`allowed to flow easily will become more conspicuous.
`voltage.
`Also, as the channel length is shortened further, the
`FIG. 9 is a diagrammatic illustration of a sectional
`storage capacitance Cs becomes smaller. At the same
`structure in one dimensional direction as taken from the
`time therewith, the write-in voltage V for writing-in
`gate region to the p type substrate of the MOS-FET
`the memory cell will decrease also. Since the electric
`shown in FIG. 1.
`charge Q which is.stored in the storage capacitor under
`FIG. 10 is a chart showing the potential profile
`the written-in state is given by CVn, the value
`within the p type substrate at a location just below the
`Q=CVn also naturally decreases as the length of the
`gate oxide film in case of n polysilicon gate.
`channel decreases. In case the storage capacitor C is
`FIG. 11 is a chart showing the potential profile
`formed with SiO2 of 300A into 10 um square in size, the
`within the p type substrate at a location just below the
`storage capacitance Cs will be about 0.12 pF. The stored
`gate oxide film in case the gate region is formed with a
`electric charge when Vn of 5V is stored on this Cs will
`p type polysilicon.
`be: Q=CVn = 6x10-13C, which represents about
`FIG. 12 is a chart for explaining the dependency
`3X10°in number of the electrons stored or in number of
`characteristic of memory holding time upon substrate
`shortage of electrons.
`bias voltage of an embodiment of the present invention.
`However, the energy of alpha-particles which are
`FIGS. 13 to 18 are diagrammatic sectional views,
`25
`irradiated from the ceramic package or the like is said to
`showing the structures of d-RAM cell according to
`be of the order of 5 MeV. When a single alpha-particle
`embodiments of the present invention.
`is irradiated within a semiconductor body, there will be
`FIG. 19 is a diagrammatic explanatory sectional view
`produced about one million pairs of electrons and holes.
`of a model device for analyzing potential profile.
`This single alpha-particle which is irradiated constitutes
`FIG.20 is a chart for explaining the boundary condi
`30
`an amount sufficient for cancelling out almost all of the
`tion of the potential profile in the channel region of the
`electric charge which has been stored in the storage
`model shown in FIG. 19.
`capacitor. In other words, even where other holding
`FIGS. 21 and 22 are charts for explaining the depen
`conditions are perfect, the electric charge which is
`dency characteristics of potential barrier height upon
`being stored in the storage capacitor will become extin
`normalized channel lengths.
`35
`guished by the irradiation of only a single alpha-parti
`FIG. 23 is a chart for explaining the dependency
`cle.
`characteristic of normalized channel length upon drain
`voltage for giving a constant potential barrier height
`Adbm.
`FIG. 24 is a chart for explaining the dependency
`characteristic of normalized channel length upon sub
`strate bias, for giving a constant potential barrier height
`Adm
`FIG. 25 is a chart for explaining the dependency
`characteristic of drain current upon drain voltage for
`various normalized channel lengths.
`FIG. 26 is a chart for explaining the dependency
`characteristic of potential barrier height upon channel
`impurity concentration for various normalized channel
`lengths.
`FIGS. 27 to 29 are diagrammatic sectional views,
`showing the structures of d-RAM cells according to
`embodiments of the present invention.
`FIGS. 30 to 32 are circuit diagrams of inverters em
`ploying the MOS transistors according to the present
`invention.
`FIG. 33 is a chart for showing energy loss of alpha
`particle.
`FIG. 34 is a chart for explaining the dependency
`characteristic of the density of electron-hole pairs
`which are excited by alpha particle upon the distance of
`entry of this alpha particle.
`FIG. 35 is a diagrammatic sectional view, showing
`the structure of a d-RAM cell according to a further
`embodiment of the present invention.
`FIG. 36 is a chart for explaining the dependency
`characteristic of the density of electron-hole pairs
`which are excited by alpha particle up to a depth of 1
`
`SUMMARY OF THE INVENTION
`It is, therefore, a primary object of the present inven
`tion to provide a semiconductor device whose memory
`retention characteristic will not degradate even where
`the channel length of this device is shortened.
`Another object of the present invention is to provide
`a semiconductor device of the type d