Case IPR2023-01333
`Patent No. 10,049,080
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
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`MERCEDES-BENZ USA, LLC,
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`Petitioner,
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`v.
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`DAEDALUS PRIME LLC,
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`Patent Owner.
`_________________________________
`Case No.: IPR2023-01333
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`U.S. Patent No. 10,049,080
`___________________
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`DECLARATION OF MICHAEL C. BROGIOLI, PH.D.
`IN SUPPORT OF PATENT OWNER’S RESPONSE
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`MB USA v. Daedalus Prime
`IPR 2023-01333
`Daedalus Ex. 2006
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`Patent No. 10,049,080
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`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`___________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`___________________
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`MERCEDES-BENZ USA, LLC,
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`Petitioner,
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`v.
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`DAEDALUS PRIME LLC,
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`Patent Owner.
`_________________________________
`Case No.: IPR2023-01333
`
`U.S. Patent No. 10,049,080
`___________________
`
`
`DECLARATION OF MICHAEL C. BROGIOLI, PH.D.
`IN SUPPORT OF PATENT OWNER’S RESPONSE
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`MB USA v. Daedalus Prime
`IPR 2023-01333
`Daedalus Ex. 2006
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`TABLE OF CONTENTS
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`INTRODUCTION .................................................................................... - 1 -
`I.
`QUALIFICATIONS ................................................................................. - 2 -
`II.
`III. LEGAL STANDARDS ............................................................................ - 7 -
`IV. A PERSON OF ORDINARY SKILL IN THE ART (“POSITA”) ........ - 10 -
`V. OVERVIEW OF THE ’080 PATENT ................................................... - 11 -
`A.
`Background .................................................................................. - 11 -
`B.
`The ’080 Patent ............................................................................ - 13 -
`C.
`The Challenged Claims ................................................................ - 16 -
`D.
`Claim Construction ...................................................................... - 18 -
`VI. THE CHALLENGES BASED ON SUTARDJA DO NOT
`DEMONSTRATE OBVIOUSNESS OF THE INDEPENDENT
`CLAIMS ................................................................................................. - 19 -
`A. Overview of Sutardja ’748 ........................................................... - 19 -
`B.
`Overview of Sutardja ’785 ........................................................... - 20 -
`C.
`In Sutardja, a Core Switching Module Transitions the System
`Between HP and LP Modes ......................................................... - 21 -
`In Sutardja, the Core Switching Module is Software ................... - 21 -
`Hypervisors in Sutardja ................................................................ - 22 -
`Inconsistencies in the Petition ...................................................... - 23 -
`Sutardja Does Not Teach or Suggest an Operating System
`that Controls Power Management Hardware ............................... - 24 -
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`D.
`E.
`F.
`G.
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`VII. THE CHALLENGES BASED ON MATHIESON-SUTARDJA DO
`NOT DEMONSTRATE OBVIOUSNESS OF THE
`INDEPENDENT CLAIMS .................................................................... - 26 -
`A. Overview of Mathieson ................................................................ - 26 -
`In Mathieson, Transfer Between Cores is Transparent to the
`B.
`Operating System ......................................................................... - 29 -
`C. Mathieson’s Fig. 6 Does Not Demonstrate a Second Plurality
`of Cores Consuming Less Power for a Same Applied Supply
`Voltage ......................................................................................... - 31 -
`The Fuses Referenced in Mathieson are Storage Elements ......... - 32 -
`D.
`E. Mathieson is Explaining a Difference in Power Consumption
`Based on Operating Frequency .................................................... - 33 -
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`I, Michael C. Brogioli, declare as follows:
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`I.
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`Introduction
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`1.
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`I have been retained on behalf of Patent Owner, Daedalus Prime LLC
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`(“Daedalus”), to provide my opinions in connection with this proceeding. In doing
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`so, I have been asked to provide my independent review, analysis, and insights
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`regarding the technology involved in U.S. Patent No 10,049,080 (“the ’080
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`patent”) and how it compares with the art asserted in the petition challenging the
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`patentability of its claims. In this Declaration, I set forth the independent opinions
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`that I have reached and the basis for those opinions using the information currently
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`available to me.
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`2.
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`I am being compensated for my work in this matter at my standard
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`hourly rate for consulting services. My compensation is not dependent on the
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`outcome of the case and does not affect the substance of my statements in this
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`Declaration. I have no financial interest in the matter or the patents at issue.
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`3.
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`I have reviewed the specification and the claims of the ’080 patent. I
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`am familiar with the technology involved therein, having worked in the field for
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`over 20+ years.
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`4.
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`To prepare this Declaration, I have considered the petition and the
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`references cited therein, including the declaration of Dr. Horst, the ’080 patent, my
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`own experience and knowledge, and the documents cited herein. I provide my
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`testimony from the perspective of a person of ordinary skill in the art at the time of
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`the invention. I was at least a person of ordinary skill in the art at the time of the
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`invention. I am familiar with the knowledge and skill level of these people at the
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`time of the invention because I was involved in the industry at the time and had
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`frequent interactions with such people at the relevant time. I have also been asked
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`to construe the claims of the ’080 patent, applying the plain and ordinary meaning
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`of the terms thereof from the perspective of a person of ordinary skill in the art in
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`light of the specification and other intrinsic evidence.
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`II. Qualifications
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`5.
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`Below is a summary of my education and experience. My curriculum
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`vitae, included as Appendix A hereto, records my education, experience, and
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`publications in greater detail.
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`6.
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`I am currently an Adjunct Professor of Electrical and Computer
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`engineering at Rice University in Houston, Texas, and Managing Director of
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`Polymathic Consulting in Austin, Texas. I received my Bachelor of Electrical
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`Engineering from Rensselaer Polytechnic Institute in 1999, my Master of Science
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`in Electrical and Computer Engineering from Rice University in 2003, and my
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`Doctorate of Electrical and Computer Engineering from Rice University in 2007.
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`7. While at Rice University, I developed various computer architecture
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`designs for embedded and high-performance systems, including multi-core and
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`low power systems. For example, from 1999 to 2003, I worked in the area of low-
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`power computing, specifically focusing on dynamic power management and
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`performance of configurable computing and memory systems. From 2002 to 2004,
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`I developed Spinach, a computer architecture design and modeling toolset, which
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`models system components common to all programmable computing
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`environments, including memory systems, multi-core microprocessor systems, and
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`related hardware components. From 2004 to 2009, I developed Spinach DSP-
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`FPGA, a modular and composable simulator design infrastructure for
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`programmable and reconfigurable embedded SOC architectures specifically
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`targeting mobile, low-power, and embedded and portable computing devices.
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`From 2005 to 2009, I developed and published a retargetable compiler
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`infrastructure and hardware design exploration toolkit for systems microprocessor
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`design, which facilitated the design space exploration of microprocessors and
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`multi-core processor designs. Many of these tools have been used at United States
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`universities in the area of electrical and computer engineering research.
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`8.
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`In the late 1990s, I was a hardware and software developer at
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`Vicarious Visions in New York, developing third-party titles for Nintendo’s
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`handheld consoles, in addition to various hardware interfaces and
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`hardware/software optimizations related low power portable computing devices.
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`During my career, I have served as Chief Technology Officer, advisory board, and
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`board of directors’ member, often in co-founding roles.
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`9.
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`From June 2006 to August 2007, I worked as the Technical Co-
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`Founder of Method Seven LLC in Boston, MA, working with high-performance
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`software and hardware systems architecture. I am currently a co-founder, co-
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`inventor, and Chief Technology Officer of Network Native, an Internet of Things
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`technology company as well as others that are detailed on my CV (Appendix A).
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`10.
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`I have held the position of Adjunct Professor at Rice University since
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`2009 and the position of Managing Director at Polymathic Consulting since 2011.
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`At Rice University, I instruct graduate-level curriculum in the areas of computer
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`architecture, hardware and software systems. I also advise on university research
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`and various design initiatives. At Polymathic Consulting, I work with a range of
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`technologists from early-stage start-ups to Fortune 500 companies on similar
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`technologies.
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`11. From 2008 to 2009, I was Senior Engineer working in high-
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`performance compiler designs and next-generation multi-core microprocessors and
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`architectures at Freescale Semiconductor in Austin, TX. From November 2009 to
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`October 2011, I was Chief Architect, Senior Member Technical Staff, at Freescale
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`Semiconductor in Austin, TX (formerly Motorola), responsible for management of
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`technology, engineering roadmaps, design lead on software infrastructure, and
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`next-generation multi-core microprocessor architectures. During my tenure at
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`Freescale Semiconductor, I was in charge of system developer tools for processor
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`design, both in the hardware and software spaces. These included tools used for
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`the programming of processors, simulation and design of processors, and related
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`technologies.
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`12.
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`I have previously worked for Texas Instruments’ Advanced
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`Architecture and Chip Technology division in Houston, Texas, in the areas of
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`high-performance mobile and embedded systems design at the hardware and
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`systems software level, specifically around heterogeneous computing, high-speed
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`bus, and interconnect technologies. I also have worked at Intel Corporation’s
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`Microprocessor Research Labs in the areas of computer architecture and compiler
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`technologies.
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`13.
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`I am recognized as an expert in the field of computer architecture,
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`computer hardware and computer software systems as they relate to the subject
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`matter at hand. I am a member of the Institute of Electrical and Electronics
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`Engineers (IEEE) and Association for Computing Machinery (ACM) and have
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`been a Program Committee member for the IEEE and ACM Design Automation
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`Conference since 2011, and have previously held the role of Program Chair of
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`Design Automation Conference in the area of Embedded Computing. I have also
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`been a reviewer and contributor to a number of IEEE and ACM technical
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`conferences during the course of my career.
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`14. Over the past 20 plus years, I have authored numerous peer-reviewed
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`publications, as well as engineering books in the area of computer hardware and
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`software design. Many of these incorporate technologies specific to the subject
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`matter at hand. These publications are disclosed in my curriculum vitae, attached
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`as Appendix A. I have previously served as an engineering consultant and
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`testifying witness on matters related to, and including, microprocessors and multi-
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`core technology as well as various aspects of power management hardware and
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`software, etc. My curriculum vitae contains more information on my background
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`and experience, as well as the cases in which I have served as an expert witness
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`over at least the past four years.
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`15.
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`I am also a named inventor on the following United States patents and
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`patent applications: U.S. Pat. Nos. 11,526,180; 11,354,757; 11,340,877; U.S. Pat.
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`Appl. No. 17/060,025 (U.S. Publication No. 2021/0099522); and U.S. Pat. Appl.
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`No. 15/110,643 (U.S. Publication No. 2016/0328993). More information regarding
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`the patent applications for which I am a named inventor can be found in my
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`curriculum vitae, attached as Appendix A.
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`III. Legal Standards
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`16.
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`I have been informed by counsel of general principles concerning
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`patent law and the analysis of whether a patent claim is invalid. Below I set forth
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`my understanding of the legal principles that may be relevant to my opinions in
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`this Declaration.
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`17.
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`I understand that a party challenging a patent’s patentability in an IPR
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`proceeding bears the burden of proof by a preponderance of evidence. I also
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`understand that the anticipation of a claim requires that a single prior art reference
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`discloses (explicitly or inherently) every element required by the claim; that is, the
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`single reference must teach all of the features or limitation of the claim.
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`18.
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`I have been informed and understand that, under U.S. patent law, a
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`patent may not issue “if the differences between the subject matter sought to be
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`patented and the prior art are such that the subject matter as a whole would have
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`been obvious at the time the invention was made to a person having ordinary skill
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`in the art to which said subject matter pertains.” This has typically been referred to
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`as the obviousness inquiry. I have been informed and understand that the
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`obviousness inquiry requires that the claimed invention be considered as a whole
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`and that in determining the differences between the prior art and the claims, the
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`question is not whether the differences themselves would have been obvious, but
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`whether the claimed invention as a whole would have been obvious.
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`19.
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`I have been informed and understand that obviousness is a question of
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`law based on underlying factual determinations, including: (1) the scope and
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`content of prior art; (2) differences between prior art and claims; (3) the level of
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`ordinary skill in the art; and (4) objective indicia of non-obviousness.
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`20.
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`I have been informed and understand that a party asserting that a
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`patent is obvious must demonstrate that a skilled artisan would have had reason to
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`combine the teaching of the asserted prior art references to achieve the claimed
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`invention, and that the skilled artisan would have had a reasonable expectation of
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`success in doing so. I have been informed and understand that reasonable
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`expectation of success is assessed as of the date of the invention described in the
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`patent. That the inventors were ultimately successful is irrelevant to whether one of
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`ordinary skill in the art, at the time the invention was made, would have reasonably
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`expected success. Any finding to the contrary represents impermissible use of
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`hindsight— using the inventors’ success as evidence that the success would have
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`been expected.
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`21.
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`I have been informed that, as part of determining the scope and
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`content of the prior art, it may be appropriate to consider whether there is evidence
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`of a “teaching, suggestion, or motivation” to combine the prior art teachings in the
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`prior art, the nature of the problem or the knowledge of a person having ordinary
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`skill in the art. The question is not simply whether the prior art teaches the
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`particular element of the invention. Knowledge of the goal does not render its
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`achievement obvious.
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`22.
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`I have been informed that one indicator of non-obviousness is when
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`prior art “teaches away” from combining certain known elements. A prior art
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`reference teaches away from the patent’s particular combination if it leads in a
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`different direction or discourages that combination, recommends steps that would
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`not likely lead to the patent’s result, or otherwise indicates that a seemingly
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`inoperative device would be produced. If the prior art indicated that the invention
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`would not have worked for its intended purpose or otherwise taught away from the
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`invention, the invention is not obvious.
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`23.
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`I have been informed that a patent that is composed of several
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`elements is not made obvious merely because each of those elements was
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`independently known in the prior art. Rather, the useful inquiry is whether there
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`was a reason that would have prompted a person having ordinary skill in the art to
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`combine the elements in the manner of the new invention. Thus, the challenger
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`must show that at the time of the invention a person of ordinary skill in the art
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`would have been motivated to combine the references, not just that the references
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`could have been combined.
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`24.
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`I have been informed that one must remain vigilant of the distortion
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`caused by hindsight bias and must be cautious of arguments reliant upon ex post
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`reasoning. The selective hindsight combination of references that show various
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`elements of the claim generally does not suffice to establish obviousness.
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`IV. A person of ordinary skill in the art (“POSITA”)
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`25.
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`In its Institution Decision, the Board assessed MB USA’s proposed
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`level of ordinary skill in the art as “consistent with the prior art.” That proposed
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`level of ordinary skill in the art is: a person with “a bachelor’s degree in electrical
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`engineering, computer science, computer engineering, material science, physics,
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`applied physics, or a related field” who would have had “at least two years of
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`experience in the research, design, development, or testing of electronic circuits or
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`components or software for controlling electronic circuits or components, or the
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`equivalent, with additional education substituting for experience and vice versa.” I
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`have been asked to apply a somewhat modified version of MB USA’s definition of
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`a person of ordinary skill in the art, limiting that individual’s work experience to
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`two years in the designated field (that is, not “at least” two years expertise, which
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`may encompass significantly more than that), so as not to include persons who
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`might exceed the level of ordinary skill in the art for purposes of this declaration.
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`26. At the time of the invention recited in the ’080 patent, I met and
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`exceeded this definition of a POSITA.
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`V. Overview of the ’080 Patent
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`A. Background
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`27. The ’080 patent is entitled “Asymmetric Performance Multicore
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`Architecture With Same Instructions Set Architecture.” EX1001 at p. 1 (54). The
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`‘080 patent purports to solve certain perceived issues in power processor
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`management. Rather than simply making adjustments to operating frequency
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`and/or voltage or employing low power states when a processor’s core is inactive,
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`the ’080 patent describes the use of different types of processor cores that consume
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`different amounts of power and offer different performance capabilities (for a
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`given operating frequency and/or voltage), yet which support the same instruction
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`set in order to manage power consumption of the processor. Id. at 3:50-62.
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`28. Multi-core processors are those that combine a plurality of processor
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`cores on a single semiconductor die. Id. at 1:22-25. The different processor cores
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`are the functional units that read and execute instructions contained in a computer
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`program. The presence of multiple cores on a single die means a multi-core
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`processor can execute multiple such instructions simultaneously.
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`29. The amount of power consumed by a processor is strongly correlated
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`with its performance capabilities. Id. at 2:26-29. Generally, decreasing processing
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`performance of a system will correspond to a power savings and vice-versa; hence,
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`processor power management techniques often involve scaling up performance as
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`a processor’s workload increases, and scaling down performance as that workload
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`decreases. Id. at 2:22-27. Such scaling of processing performance (and
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`concomitant power consumption) with workload was often done by enabling or
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`disabling entire processor cores by raising or lowering their supply voltages and
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`operating frequencies (and thereby their power consumption) in response to system
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`workload. Id. at 2:30-34.
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`30. The ’080 patent notes that such solutions have limitations. For
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`example, merely adjusting the operating frequency (also called “clock”) and/or
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`voltage at which a core operates to adjust its power consumption/processing
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`capability balance presents core management difficulties. See, e.g., EX2004 (U.S.
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`Patent No. 8,892,931 to Kruglick) at 1:31–37 (“Attempts to apply [Dynamic
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`Voltage and Frequency Scaling] to individual cores within a multicore processor
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`may encounter a number of difficulties as the number of cores increases.”);
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`EX2005 (U.S. Patent No. 9,086,883 to Thomson) at 1:42-56 (“Conventional
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`[Dynamic Clock and Voltage Scaling] solutions [for multi-core processors] exhibit
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`a number of performance problems, and implementing an effective DCVS method
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`… for each core … is an important and challenging design criterion.”).
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`31. Other approaches to power management, such as the use of low-
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`power states, also have drawbacks. For example, it can take time (and energy) to
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`wake a processor from a low power state. See EX1033 at 1:26-33 (“One approach
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`to reducing power in a computing platform when there is relatively little activity, is
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`to place the processor in a low-power state. However, placing a processor in a low-
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`power state or returning a processor from a low-power state may require a non-
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`trivial amount of time. Therefore, it may or may not be worth the time required to
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`place a processor in a low-power state or to return the processor from a low-power
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`state.”).
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`B.
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`The ’080 Patent
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`32. The power management techniques described in the ’080 patent do
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`not rely solely on adjustments to operating frequency and/or voltage or employing
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`low power states when a core is inactive. Instead, as mentioned above, in the ’080
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`patent different types of processor cores that consume different amounts of power
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`and offer different performance capabilities (for a given operating frequency and/or
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`voltage), yet which support the same instruction set, are used in a single processor.
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`EX1001 at 3:50-62. The different types of processor cores employ different power
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`consumption design features, such as different transistor technologies. These
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`different processor cores are considered at the design stage of the processor, and
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`different technology libraries are used when the different cores of the processor are
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`fabricated. Id. at 3:63 – 4:9. Consequently, while the different types of processor
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`cores can each execute the same instructions, “low power” cores will “exhibit
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`inherently lower power consumption (and processing performance) than the higher
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`power core(s),” even when the low power core is operated at the same clock
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`frequency as a higher power core. Id. at 3:53 – 4:16.
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`33. Because the different types of processor cores employ different power
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`consumption design features, they consume different amounts of power and offer
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`different performance capabilities. Hence, the different cores are referred to as
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`“asymmetric” cores. Id. at 1:17-20. The use of asymmetric cores in the ’080 patent
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`allows a single processor to “scale up [it]s processing performance … as the
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`system’s workload increases, and scale down [it]s processing performance … as
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`the system’s workload decreases,”’ just as prior multicore processors did, but
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`because processors designed according to the teachings of the ’080 patent
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`incorporate inherently low power cores, those processors are able to “achieve an
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`even lower power consumption in the lower/lowest performance/power states.” Id.
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`at 2:19-29, 3:50-62, 4:20-46.
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`34. One power management strategy presented in the ’080 patent is
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`described with reference to the patent’s FIG. 6, reproduced below. At 601, a multi-
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`core processor with multiple high power cores and at least one low power core is
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`operating. Id. at 4:47–59. As demand on the processor decreases, the various high
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`power cores are disabled one at a time, until all are disabled. Id. at 4:54 – 5:6. If all
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`of the high power cores are disabled and the demand on the processor continues to
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`drop, then the low power cores are disabled one by one until only one low power
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`core remains enabled and the processor’s lowest power state is reached. Id. at
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`5:25–35. During this process, before a core (high power or low power) is disabled,
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`its individual operating frequency and/or supply voltage, or the operating
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`frequencies and/or supply voltages of some or all of the enabled cores, may be
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`reduced in response to the drop in demand. And, if only one low power core is
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`operating, its operating frequency and/or supply voltage may similarly be reduced
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`until the lowest power consumption state is reached. Id. at 5:7-24, 28-49.
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`MB USA v. Daedalus Prime
`IPR 2023-01333
`Daedalus Ex. 2006
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`C. The Challenged Claims
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`35. The petition challenges various ones of the claims of the ’080 patent
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`under different theories, as represented in the following table:
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`Claims Challenged
`1–4, 7–12, 15–20, 23, 24
`5, 6, 13, 14, 21, 22
`7, 15, 23
`1–4, 7–12, 15–20, 23, 24
`5, 6, 13, 14, 21, 22
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`35 U.S.C. § References
`103
`“Sutardja”
`103
`Sutardja, Rychlik1
`103
`Sutardja, Carmack2
`103
`Mathieson,3 Sutardja
`103
`Mathieson, Sutardja, Rychlik
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`Pet. at 5-6.
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`36.
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`I understand that for the challenges based on “Sutardja,” MB USA has
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`considered the combined teachings of Sutardja US PGPUB 2008/0288748 A1
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`(referred to as Sutardja ’748) and Sutardja US PGPUB 2008/0288748 A1 (referred
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`to as Sutardja ’785) because the former incorporates by reference the latter. Pet. at
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`5 n.2. I adopt a similar approach in my analysis. Likewise, I understand MB USA
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`1 US PGPUB 2011/0145615 A1.
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`2 US PGPUB 2009/0309243 A1.
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`3 US PGPUB 2011/0213950 A1.
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`MB USA v. Daedalus Prime
`IPR 2023-01333
`Daedalus Ex. 2006
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`considers Mathieson to incorporate by reference the entire disclosure of Carmack.
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`Id. at 5 n.5. Therefore, I do likewise for purposes of this declaration.
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`37.
`
`Independent claim 1 of the ’080 patent recites:
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`A multi-core processor comprising:
`
`a first plurality of cores and a second plurality of cores
`
`that support a same instruction set, wherein the second
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`plurality of cores consume less power, for a same applied
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`operating frequency and supply voltage, than the first plurality
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`of cores; and
`
`power management hardware to, from a state where the
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`first plurality of cores and the second plurality of cores are
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`enabled, disable all of the first plurality of cores for a drop in
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`demand below a threshold without disabling any of the second
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`plurality of cores, wherein an operating system to execute on
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`the multi-core processor is to monitor a demand for the multi-
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`core processor and control the power management hardware
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`based on the demand.
`
`EX1001 at 7:56 – 8:3.
`
`38.
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`Independent claim 9 recites a method that includes operating a multi-
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`core processor such that a first plurality of cores and a second plurality of cores
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`IPR 2023-01333
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`Daedalus Ex. 2006
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`execute a same instruction set, wherein the second plurality of cores consume less
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`power, for a same applied operating frequency and supply voltage, than the first
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`plurality of cores; and disabling with power management hardware, from a state
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`where the first plurality of cores and the second plurality of cores are enabled, all
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`of the first plurality of cores for a drop in demand below a threshold without
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`disabling any of the second plurality of cores, wherein an operating system
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`executing on the multi-core processor monitors a demand for the multi-core
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`processor and controls the power management hardware based on the demand. Id.
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`at 8:38-53. Independent claim 17 recites a non-transitory machine-readable
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`medium containing program code that, when processed by a machine, causes a
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`method as recited in claim 9 to be performed. Id. at 9:24-41.
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`D. Claim Construction
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`39.
`
`I understand that when reviewing the patentability of a claim, the
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`analysis requires that the claim must first be construed. As mentioned above, I
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`have been asked to construe the claims of the ’080 patent by applying the plain and
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`ordinary meaning of the terms thereof from the perspective of a person of ordinary
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`skill in the art in light of the specification and other intrinsic evidence.
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`40. Each of the independent claims of the ’080 patent recites the term
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`“operating system.” In particular, the claims recite an operating system that
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`executes on a multi-core processor to monitor demand for the multi-core processor
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`IPR 2023-01333
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`and control power management hardware based on the demand. EX1001 at 7:66 –
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`8:3 (claim 1); 8:49-53 (claim 9); 9:37-41 (claim 17). The specification of the ’080
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`patent provides examples of “operating systems,” including Apple’s MacOS,
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`Microsoft’s Windows, UNIX, and others. Id. at 7:31-35. Therefore, I conclude that
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`a person of ordinary skill in the art would understand that the term “operating
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`system” is used in the ’080 patent in its conventional sense. Specifically, in the
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`context of the ’080 patent a person of ordinary skill in the art would understand an
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`”operating system” to be, “The software that controls the allocation and usage of
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`hardware resources such as memory, central processing unit (CPU) time, disk
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`space, and peripheral devices.” Ex. 2007 at 378 (Microsoft Computer Dictionary).
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`VI. The Challenges Based on Sutardja Do Not Demonstrate Obviousness of
`the Independent Claims
`
`A. Overview of Sutardja ’748
`
`41.
`
` US PGPUB 2008/0288747 A1 (“Sutardja ’748”) (EX1007) describes
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`“core morphing,” a process in which “cores [of a multi-core processor] are
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`dynamically enabled (i.e., activated) or disabled (i.e., deactivated) based on the
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`system load.” EX1007 at [0218]. When one core is active, other cores may be
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`disabled (i.e., deactivated), for example, by being put in a standby mode or
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`completely shut down, to save power. Id.
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`IPR 2023-01333
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`42.
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`In particular, Sutardja ’748 describes core morphing in the case of a
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`processing system having a low-speed, low-power (LP) core and a high-speed,
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`high-power (HP) core. Id. at [0219] et seq. In the HP mode, the HP core is in the
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`active state and processes threads. The LP core may also operate during the HP
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`mode. In other words, the LP core may be in the active state during all or part of
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`the HP mode. Id. at [0223]. “When applications demand still higher performance
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`than that provided by one HP core, multiple HP cores may be used.” Id. at [0219].
`
`B. Overview of Sutardja ’785
`
`43.
`
` US PGPUB 2007/0083785 A1 (Sutardja ’785) (EX1008) describes a
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`system on chip (“SOC”) that includes two processors, each of which has active and
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`inactive states. EX1008 at [0009]. One processor (the “second” processor)
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`consumes less power when operating in its active state than the other processor
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`(the “first” processor) when operating in its active state. Id. The SOC also includes
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`a control module that communicates with the two processors and selectively
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`transfers threads from the first processor to the second processor and selects the
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`inactive state of the first processor. Id. In programming, a “thread” is “a process
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`that is part of a larger process or program.” EX2007 at 518.
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`MB USA v. Daedalus Prime
`IPR 2023-01333
`Daedalus Ex. 2006
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`C.
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`In Sutardja, a Co
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