`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`MERCEDES-BENZ USA, LLC,
`Petitioner
`v.
`
`DAEDALUS PRIME LLC
`Patent Owner
`
`Case (to be assigned)
`U.S. Patent No. 10,049,080
`
`
`
`
`
`
`
`
`
` PETITION FOR
`INTER PARTES REVIEW OF U.S. PATENT NO. 10,049,080
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. §§42.100 et seq.
`
`
` Filed on behalf of Petitioners:
`Celine Jimenez Crowson (Reg. No. 40,357)
`Joseph Raffetto (Reg. No. 66,218)
`Scott Hughes (Reg. No. 68,385)
`Ryan Stephenson (Reg. No. 76,608)
` Nicholas Rotz (Reg. No. 75,959)
` HOGAN LOVELLS US LLP
`
`
`555 13th Street N.W.
`
` Washington, D.C. 20004
`
` Telephone: 202.637.5600
`
` Facsimile: 202.637.5710
`
`
`
`
`
`
`
`
`Helen Trac (Reg. No. 62,250)
`HOGAN LOVELLS US LLP
`Four Embarcadero, #3500
`San Francisco, CA 94111
`Telephone: 415-374-2300
`Facsimile: 415-374-2399
`
`
`
`
`
`
`
`
`
`
`
`
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`
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`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`TABLE OF CONTENTS
`
`Page
`
`INTRODUCTION ........................................................................................... 1
`I.
`II. MANDATORY NOTICES UNDER 37 C.F.R. §42.8 .................................... 1
`III. GROUNDS FOR STANDING (37 c.F.R. §42.104(A)) .................................. 4
`IV. NOTICE OF FEES PAID ................................................................................ 4
`V.
`PRECISE RELIEF REQUESTED (37 C.F.R. §42.104(B)) ........................... 4
`VI. THE CHALLENGED PATENT ..................................................................... 6
`VII. Prosecution History ......................................................................................... 8
`VIII. THERE IS NO BASIS FOR DISCRETIONARY DENIAL........................... 9
`A.
`Advanced Bionics Part I ........................................................................ 9
`B.
`Advanced Bionics Part II ..................................................................... 12
`C. Mathieson and Sutardja Render Claims 1, 4, 7-9, 12, 15-17, 20, and
`23-24 Unpatentable ............................................................................. 13
`IX. LEVEL OF ORDINARY SKILL IN THE ART ........................................... 14
`X.
`PRIORITY DATE ......................................................................................... 15
`XI. CLAIM CONSTRUCTION .......................................................................... 15
`XII. BRIEF DESCRIPTION OF THE APPLIED PRIOR ART REFERENCES 16
`A. Mathieson (Ex-1005) ........................................................................... 16
`B.
`Carmack (Ex-1006) ............................................................................. 18
`C.
`Sutardja (Ex-1007, Ex-1008) .............................................................. 19
`D.
`Rychlik (Ex-1009) ............................................................................... 20
`XIII. DETAILED EXPLANATION OF THE UNPATENABILITY GROUNDS
` ....................................................................................................................... 21
`A. Ground 1: Claims 1-4, 7-12, 15-20, 23-24 Are Rendered Obvious By
`Sutardja (Ex-1007, Incorporating Ex-1008) ....................................... 21
`1.
`Independent Claim 1 ................................................................. 22
`a.
`Element 1[preamble]: A multi-core processor
`comprising: ..................................................................... 22
`Element 1[a][i]: a first plurality of cores and a second
`plurality of cores that support a same instruction set, .... 22
`
`b.
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`c.
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`d.
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Element 1[a][ii]: wherein the second plurality of cores
`consume less power, for a same applied operating
`frequency and supply voltage, than the first plurality of
`cores; and ........................................................................ 26
`Element 1[b][i]: power management hardware to, from a
`state where the first plurality of cores and the second
`plurality of cores are enabled, disable all of the first
`plurality of cores for a drop in demand below a threshold
`without disabling any of the second plurality of cores, .. 27
`Element 1[b][ii]: wherein an operating system to execute
`on the multi-core processor is to monitor a demand for
`the multi-core processor and control the power
`management hardware based on the demand. ................ 34
`Dependent Claim 2: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates that
`have narrower logic gate driver transistors than corresponding
`logic gates of the first plurality of cores. .................................. 35
`Dependent Claim 3: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates that
`consume less power than corresponding logic gates of the first
`plurality of cores. ...................................................................... 37
`Dependent Claim 4: The multi-core processor of claim 1,
`wherein the second plurality of cores each have a maximum
`operating frequency that is less than a maximum operating
`frequency of the first plurality of cores. ................................... 37
`Dependent Claim 7: The multi-core processor of claim 1,
`wherein the first plurality of cores are at a maximum operating
`frequency in the state. ............................................................... 38
`Dependent Claim 8: The multi-core processor of claim 1,
`wherein ...................................................................................... 39
`a.
`Element 8[a]: the power management hardware is to
`enable all of the first plurality of cores for an increase in
`demand above the threshold without disabling any of the
`second plurality of cores, ................................................ 39
`Element 8[b]: wherein an operating system is to monitor
`a demand for the multi-core processor and control the
`power management hardware based on the demand. ..... 42
`
`e.
`
`b.
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`2.
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`3.
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`4.
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`5.
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`6.
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`7.
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`8.
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`9.
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`c.
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`d.
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`e.
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`f.
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Independent Claims 9 and 17:................................................... 43
`a.
`Element 9[preamble]: A method comprising: ................ 43
`b.
`Element 17[preamble]: A non-transitory machine
`readable medium containing program code that when
`processed by a machine causes a method to be
`performed, the method comprising: ............................... 43
`Elements 9[a][i] and 17[a][i]: operating a multi-core
`processor such that a first plurality of cores and a second
`plurality of cores execute a same instruction set, ........... 43
`Elements 9[a][ii] and 17[a][ii]: wherein the second
`plurality of cores consume less power, for a same applied
`operating frequency and supply voltage, than the first
`plurality of cores; and ..................................................... 43
`Elements 9[b][i] and 17[b][i]: disabling with power
`management hardware, from a state where the first
`plurality of cores and the second plurality of cores are
`enabled, all of the first plurality of cores for a drop in
`demand below a threshold without disabling any of the
`second plurality of cores, ................................................ 43
`Element 9[b][ii] and 17[b][ii]: wherein an operating
`system executing on the multi-core processor monitors a
`demand for the multi-core processor and controls the
`power management hardware based on the demand. ..... 44
`Dependent Claims 10 and 18: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating of the second plurality of cores comprises
`driving logic gates that have narrower logic gate driver
`transistors than corresponding logic gates of the first plurality
`of cores. ..................................................................................... 44
`Dependent Claims 11 and 19: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating of the second plurality of cores comprises
`driving logic gates that consume less power than corresponding
`logic gates of the first plurality of cores. .................................. 44
`10. Dependent Claims 12 and 20: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating comprises operating the second plurality
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`of cores at a maximum operating frequency that is less than a
`maximum operating frequency of the first plurality of cores. .. 44
`11. Dependent Claims 15 and 23: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating comprises operating the first plurality of
`cores at a maximum operating frequency in the state. .............. 45
`12. Dependent Claims 16 and 24: The [method of claim
`9/nontransitory machine readable medium of claim 17], further
`comprising ................................................................................. 45
`a.
`Elements 16[a] and 24[a]: enabling, with the power
`management hardware, all of the first plurality of cores
`for an increase in demand above the threshold without
`disabling any of the second plurality of cores, ............... 45
`Elements 16[b] and 24[b]: wherein an operating system
`is to monitor a demand for the multi-core processor and
`control the power management hardware based on the
`demand. ........................................................................... 45
`Ground 2: Claims 5-6, 13-14, and 21-22 Are Rendered Obvious By
`Sutardja/Rychlik .................................................................................. 45
`1.
`Dependent Claims 5, 13, and 21: .............................................. 45
`a.
`Elements 5[a], 13[a], 21[a]: The [multi-core processor of
`claim 1/method of claim 9/non-transitory machine
`readable medium of claim 17], [wherein the power
`management hardware is to disable/further comprising
`disabling, with the power management hardware,] an
`additional core of the second plurality of cores for each
`continued drop in demand below a next lower threshold
`until one core of the second plurality of cores remains
`enabled, and .................................................................... 45
`Elements 5[b], 13[b], 21[b]: [lower/lowering] an
`operating frequency or a supply voltage of the one core
`of the second plurality of cores as demand drops below a
`next lower threshold. ...................................................... 49
`Dependent Claims 6, 14, 22: [The multi-core processor of claim
`5/method of claim 13/The non-transitory machine readable
`medium of claim 21], [wherein the power management
`hardware is to raise/further comprising raising, with the power
`
`b.
`
`b.
`
`B.
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`2.
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`management hardware,] a supply voltage or an operating
`frequency of said one core in response to higher demand. ....... 51
`C. Ground 3: Claims 7, 15, and 23 Are Rendered Obvious By
`Sutardja/Carmack ................................................................................ 51
`1.
`Dependent Claims 7, 15, 23: The [multi-core processor of claim
`1/method of claim 9/non-transitory machine readable medium
`of claim 17], wherein [the operating comprises operating] the
`first plurality of cores [are] at a maximum operating frequency
`in the state. ................................................................................ 51
`D. Ground 4: Claims 1-4, 7-12, 15-20, and 23-24 Are Rendered Obvious
`By Mathieson/Sutardja ........................................................................ 53
`1.
`A POSITA would have been motivated to combine Mathieson
`with Sutardja ............................................................................. 53
`Independent Claim 1 ................................................................. 53
`a.
`Element 1[preamble]: A multi-core processor
`comprising: ..................................................................... 53
`Element 1[a][i]: a first plurality of cores and a second
`plurality of cores that support a same instruction set, .... 55
`Element 1[a][ii]: wherein the second plurality of cores
`consume less power, for a same applied operating
`frequency and supply voltage, than the first plurality of
`cores; and ........................................................................ 58
`Element 1[b][i]: power management hardware to, from a
`state where the first plurality of cores and the second
`plurality of cores are enabled, disable all of the first
`plurality of cores for a drop in demand below a threshold
`without disabling any of the second plurality of cores, .. 59
`Element 1[b][ii]: wherein an operating system to execute
`on the multi-core processor is to monitor a demand for
`the multi-core processor and control the power
`management hardware based on the demand. ................ 65
`Dependent Claim 2: The multi-core processor of claim 1,
`wherein the second plurality of cores comprise logic gates that
`have narrower logic gate driver transistors than corresponding
`logic gates of the first plurality of cores. .................................. 67
`Dependent Claim 3: The multi-core processor of claim 1,
`
`2.
`
`3.
`
`4.
`
`b.
`
`c.
`
`d.
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`e.
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`5.
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`6.
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`7.
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`8.
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`b.
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`wherein the second plurality of cores comprise logic gates that
`consume less power than corresponding logic gates of the first
`plurality of cores. ...................................................................... 70
`Dependent Claim 4: The multi-core processor of claim 1,
`wherein the second plurality of cores each have a maximum
`operating frequency that is less than a maximum operating
`frequency of the first plurality of cores. ................................... 71
`Dependent Claim 7: The multi-core processor of claim 1,
`wherein the first plurality of cores are at a maximum operating
`frequency in the state. ............................................................... 73
`Dependent Claim 8: The multi-core processor of claim 1,
`wherein ...................................................................................... 74
`a.
`Element 8[a]: the power management hardware is to
`enable all of the first plurality of cores for an increase in
`demand above the threshold without disabling any of the
`second plurality of cores, ................................................ 74
`Element 8[b]: wherein an operating system is to monitor
`a demand for the multi-core processor and control the
`power management hardware based on the demand. ..... 78
`Independent Claims 9 and 17:................................................... 79
`a.
`Element 9[preamble]: A method comprising: ................ 79
`b.
`Element 17[preamble]: A non-transitory machine
`readable medium containing program code that when
`processed by a machine causes a method to be
`performed, the method comprising: ............................... 79
`Elements 9[a][i] and 17[a][i]: operating a multi-core
`processor such that a first plurality of cores and a second
`plurality of cores execute a same instruction set, ........... 79
`Elements 9[a][ii] and 17[a][ii]: wherein the second
`plurality of cores consume less power, for a same applied
`operating frequency and supply voltage, than the first
`plurality of cores; and ..................................................... 79
`Elements 9[b][i] and 17[b][i]: disabling with power
`management hardware, from a state where the first
`plurality of cores and the second plurality of cores are
`enabled, all of the first plurality of cores for a drop in
`
`c.
`
`d.
`
`e.
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`f.
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`9.
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`demand below a threshold without disabling any of the
`second plurality of cores, ................................................ 80
`Element 9[b][ii] and 17[b][ii]: wherein an operating
`system executing on the multi-core processor monitors a
`demand for the multi-core processor and controls the
`power management hardware based on the demand. ..... 80
`Dependent Claims 10 and 18: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating of the second plurality of cores comprises
`driving logic gates that have narrower logic gate driver
`transistors than corresponding logic gates of the first plurality
`of cores. ..................................................................................... 80
`10. Dependent Claims 11 and 19: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating of the second plurality of cores comprises
`driving logic gates that consume less power than corresponding
`logic gates of the first plurality of cores. .................................. 80
`11. Dependent Claims 12 and 20: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating comprises operating the second plurality
`of cores at a maximum operating frequency that is less than a
`maximum operating frequency of the first plurality of cores. .. 81
`12. Dependent Claims 15 and 23: The [method of claim
`9/nontransitory machine readable medium of claim 17],
`wherein the operating comprises operating the first plurality of
`cores at a maximum operating frequency in the state. .............. 81
`13. Dependent Claims 16 and 24: The [method of claim
`9/nontransitory machine readable medium of claim 17], further
`comprising ................................................................................. 81
`a.
`Elements 16[a] and 24[a]: enabling, with the power
`management hardware, all of the first plurality of cores
`for an increase in demand above the threshold without
`disabling any of the second plurality of cores, ............... 81
`Elements 16[b] and 24[b]: wherein an operating system
`is to monitor a demand for the multi-core processor and
`control the power management hardware based on the
`demand. ........................................................................... 81
`
`b.
`
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`E.
`
`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Ground 5: Claims 5-6, 13-14, and 21-22 Are Rendered Obvious By
`Mathieson/Sutardja/Rychlik ................................................................ 81
`1.
`Dependent Claims 5, 13, and 21: .............................................. 82
`a.
`Elements 5[a], 13[a], 21[a] ............................................. 82
`b.
`Elements 5[b], 13[b], 21[b] ............................................ 83
`Dependent Claims 6, 14, 22 ...................................................... 83
`2.
`XIV. CONCLUSION .............................................................................................. 83
`
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`
`
`LIST OF EXHIBITS1
`
`Ex-1001
`
`U.S. Patent No. 10,049,080 to George et al. (“the ’080 Patent”)
`
`Ex-1002
`
`Declaration of Dr. Trevor Mudge submitted in IPR2023-00567
`
`Ex-1003
`
`Curriculum Vitae of Dr. Trevor Mudge
`
`Ex-1004
`
`Ex-1005
`
`Prosecution History of the ’080 Patent (Application No.
`15/431,527)
`
`U.S. Patent Pub. No. 2011/0213950 to Mathieson et al.
`(“Mathieson”)
`
`Ex-1006
`
`U.S. Patent Pub. No. 2009/0309243 to Carmack et al. (“Carmack”)
`
`Ex-1007
`
`U.S. Patent Pub. No. 2008/0288748 to Sutardja et al. (“Sutardja
`’748”)
`
`Ex-1008
`
`U.S. Patent Pub. No. 2007/0083785 to Sutardja (“Sutardja ’785”)
`
`Ex-1009
`
`U.S. Patent Pub. No. 2011/0145615 to Rychlik et al. (“Rychlik”)
`
`Ex-1010
`
`Prosecution History of U.S. Patent No. 9,569,278 (“the ’278
`Patent”)
`
`Ex-1011
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1012
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1013
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1014
`
`INTENTIONALLY LEFT BLANK
`
`
`1 Four-digit pin citations that begin with 0 are to the branded numbers added by
`
`Mercedes in the bottom right corner of the exhibits. All other pin citations are to
`
`original page, column, paragraph, or line numbers.
`
`
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`Ex-1015
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1016
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1017
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1018
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1019
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1020
`
`Claim Mapping Table
`
`Ex-1021
`
`INTENTIONALLY LEFT BLANK
`
`Ex-1022
`
`U.S. Patent Pub. No. 2006/0095807 to Grochowski
`(“Grochowski”)
`
`Ex-1023
`
`U.S. Patent Pub. No. 2012/0317568 to Aasheim (“Aasheim”)
`
`Ex-1024
`
`Ex-1025
`
`Jeffrey C. Mogul et al., Operating Systems and Asymmetric Single-
`ISA CMPs: The Potential for Saving Energy, Hewlett-Packard
`Development Company, L.P. (2007)
`
`Juan Carlos Saez et al., Operating System Support for Mitigating
`Software Scalability Bottlenecks on Asymmetric Multicore
`Processors, ACM 978-1-4503-004-5/10/05 (2010)
`
`Ex-1026
`
`U.S. Patent No. 7,093,147 to Farkas et al. (“Farkas”)
`
`Ex-1027
`
`Ex-1028
`
`Ex-1029
`
`Ex-1030
`
`
`
`Charles Lefurgy et al., Energy Management for Commercial
`Servers, Computer 39 (Dec. 2003).
`
`Yushi Shen et al., Enabling the New Era of Cloud Computing:
`Data Security, Transfer, and Management (Information Science
`Reference 2014).
`
`Stefanos Kaxiras and Margaret Martonosi, Computer Architecture
`Techniques for Power-Efficiency, in Synthesis Lectures on
`Computer Architecture #4 (Morgan & Claypool 2008).
`
`Vasanth Venkatachalam and Michael Franz, Power Reduction
`Techniques For Microprocessor Systems, 37 ACM Computing
`Surveys 195 (2005).
`
`- ii -
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`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`Ex-1031
`
`Ex-1032
`
`Euiseong Seo et al., Energy Efficient Scheduling of Real-Time
`Tasks on Multicore Processors, 19 IEEE Transactions on Parallel
`and Distributed Systems 1540 (Nov. 2008).
`
`Rakesh Kumar et al., Single-ISA Heterogeneous Multi-Core
`Architectures: The Potential for Processor Power Reduction,
`Proceedings of the 36th International Symposium on
`Microarchitecture (MICRO-36 2003), IEEE Computer Society
`(2003).
`
`Ex-1033
`
`U.S. Patent No. 8,615,647 to Hum et al. (“Hum”)
`
`Ex-1034
`
`Declaration of Dr. Robert Horst
`
`Ex-1035
`
`Curriculum Vitae of Dr. Robert Horst
`
`
`
`
`
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`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`I.
`
`INTRODUCTION
`
`Mercedes-Benz USA, LLC. (“Mercedes”) requests inter partes review
`
`(“IPR”) of Claims 1-24 of U.S. Patent No. 10,049,080 (“the ’080 Patent”) (Ex-1001),
`
`currently assigned to Daedalus Prime LLC (“PO”).
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. §42.8
`
`REAL PARTY-IN-INTEREST: The real parties-in-interest are Petitioner
`
`Mercedes-Benz USA, LLC; Mercedes-Benz Intellectual Property GmbH & Co. KG;
`
`Mercedes-Benz Group AG; and Mercedes-Benz AG.
`
`RELATED MATTERS: The ’080 is the subject of the following civil actions:
`
`Daedalus Prime LLC v. Arrow Electronics, Inc et al., Case No. 1-22-cv-01107 (D.
`
`De), filed August 23, 2022; Daedalus Prime LLC v. Mazda Motor Corporation et
`
`al., Case No. 1-22-cv-01108 (D. De), filed August 23, 2022; Daedalus Prime LLC
`
`v. Mazda Motor Corporation et al., Case No. 1-22-cv-01109 (D. De), filed August
`
`23, 2022; and In the Matter of Certain Semiconductors and Devices and Products
`
`Containing the Same, Including Printed Circuit Boards, Automotive Parts, and
`
`Automobiles, Inv. No. 337-TA-1332 (U.S. International Trade Commission), filed
`
`August 23, 2022.
`
`The ’080 is further the subject of Qualcomm Inc. v. Daedalus Prime LLC,
`
`IPR2023-00567 (PTAB), filed February 14, 2023. That petition is currently pending
`
`as to Qualcomm Incorporated, and no institution decision has been made. That
`
`
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`petition has been terminated as to Petitioners Samsung Electronics Co., Ltd. and
`
`Samsung Electronics America, Inc. Petitioner is concurrently filing a Motion to Join
`
`IPR2023-00567 herewith, and requests the Board consider that motion if IPR2023-
`
`00567 is instituted.2
`
`LEAD AND BACKUP COUNSEL:
`
`Lead Counsel
`Celine J. Crowson (Reg. No. 40,357)
`celine.crowson@hogan.com
`
`Postal and Hand-Delivery Address
`Hogan Lovells US LLP
`555 13th Street N.W.
`Washington, D.C. 20004
`Telephone: 202.637.5600
`Facsimile: 202.637.5910
`
`Back-Up Counsel
`Joseph J. Raffetto (Reg. No. 66,218)
`joseph.raffetto@hoganlovells.com
`
`Postal and Hand-Delivery
`Address
`Hogan Lovells US LLP
`555 13th Street N.W.
`Washington, D.C. 20004
`Telephone: 202.637.5600
`Facsimile: 202.637.5910
`Scott Hughes (Reg. No. 68,385)
`scott.hughes@hoganlovells.com
`
`Postal and Hand-Delivery
`Address
`Hogan Lovells US LLP
`555 13th Street N.W.
`Washington, D.C. 20004
`Telephone: 202.637.5600
`Facsimile: 202.637.5910
`
`
`2 Should IPR2023-00567 be terminated prior to any institution decision, or otherwise
`
`not instituted for any reason, Petitioner submits its motion for joinder would be
`
`moot, and would request the Board consider this Petition on its own merits.
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`
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`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`Helen Y. Trac (Reg. No. 62,250)
`helen.trac@hoganlovells.com
`
`Postal and Hand-Delivery
`Address
`Hogan Lovells US LLP
`Four Embarcadero,
`# 3500
`San Francisco, CA 94111
`Tel.: 415.374.2300
`Fax: 415.374.2399
`Ryan Stephenson
`(Reg. No. 76,608)
`ryan.stephenson@hoganlovells.com
`
`Postal and Hand-Delivery Address:
`HOGAN LOVELLS US LLP
`555 13th Street, N.W.
`Washington, D.C. 20004
`Tel.: 202.637.5600
`Fax: 202.637.5910
`Nicholas Rotz
`(Reg. No. 75,959)
`nicholas.rotz@hoganlovells.com
`
`Postal and Hand-Delivery Address:
`HOGAN LOVELLS US LLP
`555 13th Street, N.W.
`Washington, D.C. 20004
`Tel.: 202.637.5600
`Fax: 202.637.5910
`
`
`
`SERVICE INFORMATION: Petitioner consents to electronic service by email
`
`at the following addresses:
`
`celine.crowson@hoganlovells.com
`
`joseph.raffetto@hoganlovells.com
`
`
`
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`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`scott.hughes@hoganlovells.com
`
`helen.trac@hoganlovells.com
`
`ryan.stephenson@hoganlovells.com
`
`nicholas.rotz@hoganlovells.com
`
`
`
`III. GROUNDS FOR STANDING (37 C.F.R. §42.104(A))
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`The undersigned and Petitioner certify that the ‘080 is available for inter
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`partes review. Petitioner is not barred or estopped from requesting this review.
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`IV. NOTICE OF FEES PAID
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`Fees are submitted herewith. If additional fees are due during the
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`proceeding, the undersigned authorizes the Office to charge them to Deposit
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`Account No. 50-1349.
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`V.
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`PRECISE RELIEF REQUESTED (37 C.F.R. §42.104(B))
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`Petitioner requests cancellation of Claims 1-24 under 35 U.S.C. §§103 on the
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`following grounds, supported by a declaration from Dr. Robert Horst.3 Ex-1034.
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`3 Petitioner retained Dr. Horst, who prepared a declaration adopting the opinions
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`set forth in EX1002, the declaration of Dr. Trevor Mudge submitted in IPR2023-
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`00567, as his own. EX1034,¶3. Petitioner has provided Dr. Horst’s declaration
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`(EX1034), and notes there are corresponding, identical opinions in Dr. Mudge’s
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`declaration. Citations in this petition are to Dr. Horst’s declaration.
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`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`Ground
`
`Summary
`
`1
`
`2
`
`3
`
`4
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`Claims 1-4, 7-12, 15-20, and 23-24 are rendered obvious by
`Sutardja4 alone (Ex-1007, incorporating Ex-1008)
`
`Claims 5-6, 13-14, and 21-22 are rendered obvious by Sutardja in
`view of Rychlik (“Sutardja/Rychlik”)
`
`Claims 7, 15, and 23 are rendered obvious by Sutardja in view of
`Carmack (“Sutardja/Carmack”)
`
`Claims 1-4, 7-12, 15-20, and 23-24 are rendered obvious by
`Mathieson5 (Ex-1005, incorporating Ex-1006) in view of Sutardja
`(“Mathieson/Sutardja”)
`
`
`4 For clarity, this ground relies on Sutardja ’748 (Ex-1007) incorporating by
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`reference Sutardja ’785 (Ex-1008), as a single reference obviousness ground,
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`referred to herein as the “combined Sutardja” or simply “Sutardja.” When
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`reference is made to a particular patent, Ex-1007 refers to Sutardja ’748, and Ex-
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`1008 refers to the incorporated document Sutardja ’785. To the extent that any
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`relied upon teaching is argued to have not been fully incorporated from Ex-1008
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`into Ex-1007, it would have been obvious to combine such feature/teaching from
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`Ex-1008 with Ex-1007, for the same reasons provided herein.
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`5 For clarity, Ground 4 relies on Mathieson (Ex-1005) incorporating by reference
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`Carmack (Ex-1006), referred to herein as simply “Mathieson.” To the extent that
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`any relied upon teaching is argued to have not been fully incorporated from Ex-
`
`
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`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`5
`
`Claims 5-6, 13-14, and 21-22 are rendered obvious by
`Mathieson/Sutardja in view of Rychlik
`(“Mathieson/Sutardja/Rychlik”)
`
`
`
`VI. THE CHALLENGED PATENT
`
`The ’080 Patent is directed to power management in a multi-core processor.
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`Ex-1001, 3:34-62. The ’080 Patent explains that “a number of different power
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`management schemes are incorporated into modern day computing systems.” Ex-
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`1001, 2:20-22. Prior art power management schemes include
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`“enabl[ing]/disabl[ing] entire cores and rais[ing]/lower[ing] their supply voltages
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`and operating frequencies in response to system workload,” as illustrated in Figure
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`2.6 Ex-1001, 2:30-33.
`
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`1006 into Ex-1005, it would have been obvious to combine such teaching from Ex-
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`1006 with Ex-1005, for the same reasons provided herein.
`
`6 All annotations and emphasis have been added, unless otherwise noted.
`- 6 -
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`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`
`
`
`The ‘080 Patent allegedly improves upon the prior art using “[s]ome basic
`
`concepts of electronic circuit power consumption,” including that “the speed of
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`operation of interconnected logic gates [] rises as the width of its driving transistors
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`[] increase,” as does the power consumed by those logic gates. Ex-1001, 2:43-52,
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`3:26-33. In particular, the ’080 Patent implements a multi-core processor in which
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`one or more cores are “designed to be lower performance and therefore consume
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`less power than other cores,” while nevertheless supporting the same instruction
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`set, purportedly to achieve greater power savings. Ex-1001, 3:50-62, 4:20-29.
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`But multi-core processors with both high-power and low-power cores, each
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`supporting the same instruction set, were well-known in the prior art. Ex-
`- 7 -
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`
`
`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`1034,¶¶40, 60-63. Indeed, as explained below, the ’080 Patent’s claims would have
`
`been obvious.
`
`VII. PROSECUTION HISTORY
`
`The ’080 Patent was filed February 13, 2017, as a continuation of
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`Application No. 13/335,257 (now U.S. 9,569,278), filed December 21, 2011.
`
`During prosecution, the Examiner rejected pending claims corresponding to
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`issued claims 1, 4-9, 12-17, and 20-24 over U.S. Patent Pub. No. 2006/0095807 to
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`Grochowski and pending claims corresponding to issued claims 2-3, 10-11, and
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`18-19 over Grochowski in view of U.S. Patent Pub. No. 2008/0263324 (Sutardja
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`’324). Ex-1004, 0067-0072. Applicant argued that Grochowski failed to teach all
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`of the limitations of the independent claims:
`
`
`
`
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`Ex-1004, 0056. Notably, Applicant did not dispute that Sutardja ’324 teaches the
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`
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`- 8 -
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`

`

`U.S. Patent No. 10,049,080
`Petition for Inter Partes Review
`transistor-related limitations of dependent Claims 2-3, 10-11, and 18-19. Ex-1004,
`
`0054-0057.
`
` As reflected in the file history, the purported novelty of the claims lay in the
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`power management hardware. However, as explained in the Grounds below, this
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`limitation (indeed all limitations of Claims 1-24) was well-known.
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`VIII. THERE IS NO BASIS FOR DISCRETIONARY DENIAL
`
`The Board should not deny institution under 35 U.S.C. §314(a). The only
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`non-PTO proceeding relating to the ’080 Patent with a scheduled hearing date is in
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`the ITC (the concurrent District court litigations are stayed pending the ITC
`
`proceeding), however, concurrent ITC proceedings are not a basis to
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`discretionarily deny IPR institution. See USPTO Memorandum by Katherine
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`Vidal, June 21, 2022, Interim Procedure For Discretionary Denials in AIA Post-
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`Grant Proceedings with Parallel District Court Litigation, at 5-7.
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`Nor should the Board deny institution under 35 U.S.C. §325(d), because
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`both parts of the Advanced Bionics, LLC v. Med-El Elektromedizinische Geräte
`
`GMBH framework weigh against denial. IPR2019-01469, Paper 6, at 8 (PTAB
`
`Feb. 13, 2