US010049080B2
`
`a2) United States Patent
`George etal.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 10,049,080 B2
`Aug. 14, 2018
`
`(54)
`
`ASYMMETRIC PERFORMANCE
`
`(56)
`
`References Cited
`
`MULTICORE ARCHITECTURE WITH SAME
`
`INSTRUCTION SET ARCHITECTURE
`
`U.S. PATENT DOCUMENTS
`
`(71)
`
`Applicant: Intel Corporation, Santa Clara, CA
`(US)
`
`(72)
`
`Inventors: Varghese George, Folsom, CA (US);
`
`7,992,020 Bl
`2006/0095807 Al*
`
`8/2011 Tuan etal.
`5/2006 Grochowsk1 ........... GO6F 1/206
`713/324
`2006/0279152 Al* 12/2006 Ha ow. ee, GO6F 1/3203
`310/114
`
`Petitioner Mercedes Ex-1001, 0001
`
`
`
`a2) United States Patent
`George etal.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 10,049,080 B2
`Aug. 14, 2018
`
`(54)
`
`ASYMMETRIC PERFORMANCE
`
`(56)
`
`References Cited
`
`MULTICORE ARCHITECTURE WITH SAME
`
`INSTRUCTION SET ARCHITECTURE
`
`U.S. PATENT DOCUMENTS
`
`(71)
`
`Applicant: Intel Corporation, Santa Clara, CA
`(US)
`
`(72)
`
`Inventors: Varghese George, Folsom, CA (US);
`
`7,992,020 Bl
`2006/0095807 Al*
`
`8/2011 Tuan etal.
`5/2006 Grochowsk1 ........... GO6F 1/206
`713/324
`2006/0279152 Al* 12/2006 Ha ow. ee, GO6F 1/3203
`310/114
`
`Petitioner Mercedes Ex-1001, 0001
`
`
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`US 10,049,080 B2
`Page 2
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`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`Non-Final Office Action from U.S. Appl. No. 13/335,257 dated May
`26, 2016, 10 pages.
`Notice of Allowance from U.S. Appl. No. 13/335,257 dated Sep. 27,
`2016, 6 pages.
`Second Office Action from foreign counterpart China Patent Appli-
`cation No. 201280063860, dated Jul. 21, 2016, 12 pages.
`Third Office Action from foreign counterpart China Patent Appli-
`12/2009 Munyalet al.
`2009/0307512 Al
`cation No. 201280063860, dated Dec. 15, 2016, 31 pages.
`12/2009 Boseet al.
`2009/0328055 Al
`Notice of Allowance from TW_counterpart Application No.
`2010/0058086 Al
`3/2010 Lee
`101147200, dated Sep. 29, 2014,
`1 page.
`2010/0083011 Al
`4/2010 Onouchi et al.
`Aruj, Ori. “Evolution: 20 years of switching Fabric”, Sep. 2008. EE
`2010/0131781 Al*
`5/2010 Memon............0... GO6F 1/3209
`Times. from_http://www.eetimes.com/document.Retrieved
`
`
`
`2009/0271646 Al* 10/2009 Talwar ou... GO6F 1/3203
`713/322
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`Petitioner Mercedes Ex-1001, 0002
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 1 of 8
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`US 10,049,080 B2
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`100_1
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`Petitioner Mercedes Ex-1001, 0003
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 2 of 8
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`US 10,049,080 B2
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`Petitioner Mercedes Ex-1001, 0004
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 3 of 8
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`US 10,049,080 B2
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`Petitioner Mercedes Ex-1001, 0005
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 4 of 8
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`US 10,049,080 B2
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`HIGH POWER
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`LOW POWER
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`Petitioner Mercedes Ex-1001, 0006
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 5 of 8
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`US 10,049,080 B2
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`Petitioner Mercedes Ex-1001, 0007
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 6 of $
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`Aug. 14, 2018
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`OINGLE LOW
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`Petitioner Mercedes Ex-1001, 0009
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`U.S. Patent
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`Aug. 14, 2018
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`Sheet 8 of 8
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`800
`|
`
`CREATE HIGH LEVEL
`BEHAVIOR DESCRIPTIONS
`
`PROCESSOR'S CORES
`
`Petitioner Mercedes Ex-1001, 0010
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`US 10,049,080 B2
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`1
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`ASYMMETRIC PERFORMANCE
`MULTICORE ARCHITECTURE WITH SAME
`INSTRUCTION SET ARCHITECTURE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`The present patent application is a continuation applica-
`tion claiming priority from U.S. patent application Ser. No.
`13/335,257, filed Dec. 22, 2011, and titled: “Asymmetric
`Performance Multicore Architecture with Same Instruction
`Set Architecture”, which is incorporated herein by reference
`
`2
`FIG. 1 shows a multicore processor and surrounding
`computer system (priorart);
`FIG. 2 shows a power managementstrategy (prior art);
`FIG. 3 shows a logic gate drive circuit;
`FIG. 4 shows multi core processor having high power and
`low power cores that support the same instruction set;
`FIG. 5 compares power consumption of a high power core
`and low powercore;
`FIG. 6 showsa first power management method;
`FIG. 7 shows a second power management method;
`FIG. 8 shows a design method.
`
`Petitioner Mercedes Ex-1001, 0011
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`US 10,049,080 B2
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`3
`driver circuit 310 observed in FIG. 3. Essentially, the higher
`the supply voltage, the stronger the source/sink currents will
`be.
`Further still, the rate at which the transistors will be able
`to apply/draw charge to/from the capacitor is a function of
`the size of the capacitance 303 of the line 304 being driven.
`Specifically, the transistors will apply/draw charge slower as
`the capacitance 304 increases and apply/draw charge faster
`as the capacitance 304 decreases. The capacitance 304 of the
`line is based on its physical dimensions. That 1s, the capaci-
`tance 304 increases the longer and wider the line, and by
`
`5
`
`10
`
`4
`higher level descriptions are synthesized into RIL netlists,
`however, for the subsequent synthesis from an RIL netlist
`into a transistor level netlist, different technology libraries
`are used for the low power core(s) than the high power
`core(s). As alluded to above, the drive transistors of logic
`gates associated with the libraries used for the low power
`core(s) have narrower respective widths than the “same”
`transistors of the “same” logic gates associated with the
`libraries used for the high powercores.
`By design of the multiprocessor, referring to FIG. 5, the
`lower power core(s) exhibit inherently lower power con-
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`Petitioner Mercedes Ex-1001, 0012
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`US 10,049,080 B2
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`5
`instance, as observedat inset 610, demand level 611 justifies
`enablement of the seven high power cores and both low
`power cores. As the demand continually drops to a next
`lower threshold 612, one of the high powercoresis disabled
`613 leaving six operable high power cores and two low
`powercores.
`Before the high power core is disabled, as a matter of
`designer choice, the core’s individual operating frequency,
`or the operating frequency of all (or some of) the enabled
`high powercores, or the operating frequency ofall (or some
`of) the enabled high power cores and the low power cores
`
`10
`
`6
`demand on the multi-processor continually increases. Even-
`tually, high power cores are enabled 703. Notably,
`the
`demand threshold needed to enable a next processor from an
`operating low power processor may correspond to a lower
`demand increment than the demand threshold needed to
`enable to a next processor from an operating high power
`processor.
`inset 710 shows the increase in demand 711
`That is,
`needed after a low powerprocessor is first enabled to trigger
`the enablement of a next processor in the face of increased
`demand. The increase in demand 712 needed after a high
`
`Petitioner Mercedes Ex-1001, 0013
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`US 10,049,080 B2
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`7
`disposed on a semiconductor chip (e.g., “logic circuitry”
`implemented with transistors) designed to execute instruc-
`tions such as a general-purpose processor and/or a special-
`purpose processor. Processes taught by the discussion above
`may also be performed by (in the alternative to a machine or
`in combination with a machine) electronic circuitry designed
`to perform the processes (or a portion thereof) without the
`execution of program code.
`It
`is believed that processes taught by the discussion
`above may also be described in source level program code
`in various object-orientated or non-object-orientated com-
`
`8
`to monitor a demand for the multi-core processor and
`control the power management hardware based on the
`demand.
`2. The multi-core processor of claim 1, wherein the
`second plurality of cores comprise logic gates that have
`narrower logic gate driver transistors than corresponding
`logic gates of the first plurality of cores.
`3. The multi-core processor of claim 1, wherein the
`second plurality of cores comprise logic gates that consume
`less power than corresponding logic gates of the first plu-
`rality of cores.
`
`5
`
`10
`
`Petitioner Mercedes Ex-1001, 0014
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`US 10,049,080 B2
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`9
`the second plurality of cores for each continued drop in
`demand below a next lower threshold until one core of the
`second plurality of cores remains enabled, and lowering an
`operating frequency or a supply voltage of the one core of
`the second plurality of cores as demand drops below a next
`lower threshold.
`14. The method of claim 13, further comprising raising,
`with the power management hardware, a supply voltage or
`an operating frequency of said one core in response to higher
`demand, wherein an operating system executing on the
`multi-core processor monitors a demand for the multi-core
`
`10
`18. The non-transitory machine readable medium of claim
`17, wherein the operating of the second plurality of cores
`comprises driving logic gates that have narrowerlogic gate
`driver transistors than corresponding logic gates ofthe first
`plurality of cores.
`19. The non-transitory machine readable medium of claim
`17, wherein the operating of the second plurality of cores
`comprises driving logic gates that consume less power than
`corresponding logic gates of the first plurality of cores.
`20. The non-transitory machine readable medium of claim
`17, wherein the operating comprises operating the second
`plurality of cores at a maximum operating frequencythat is
`
`Petitioner Mercedes Ex-1001, 0015
`
`
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