OPTICAL INTERCONNECTIONS IN MICROELECTRONICS
`OPTICAL INTERCONNECTIONS IN MICROELECTRONICS
`
`Joseph W. Goodman
`Joseph W. Goodman
`
`Department of Electrical Engineering
`Department of Electrical Engineering
`Stanford University
`Stanford University
`Stanford, California 94305
`Stanford, California
`94305
`
`Abstract
`Abstract
`
`As the complexity of microelectronic circuits increases, performance becomes more and
`As the complexity of microelectronic circuits increases, performance becomes
`more
`and
`more limited by interconnections.
`Continued scaling and packing lead to a dominance of
`more
`limited
`interconnections.
`Continued
`scaling and packing lead to a dominance of
`by
`interconnect delays over gate delays. This paper explores the potential of optical inter(cid:173)
`interconnect delays over gate delays.
`This paper explores the potential of
`optical
`inter-
`connections as a mean for alleviating such limitations. Various optical approaches to the
`connections
`mean for alleviating such limitations. Various optical approaches to the
`as
`a
`problem are discussed, including the use of guided waves (integrated optics and fiber
`problem are discussed, including the use
`guided
`waves
`(integrated
`optics
`and
`fiber
`of
`optics) and free space propagation (simple broadcast and imaging interconnections). The
`propagation (simple broadcast and imaging interconnections).
`free
`optics)
`space
`and
`The
`utility of optics is influenced by the nature of the algorithms that are being carried out
`utility of optics is influenced by the nature of the algorithms that are being
`out
`carried
`in computations.
`Certain algorithms make far greater demands on interconnections than do
`Certain
`algorithms make far greater demands on interconnections than do
`computations.
`in
`others. Clock distribution is a specific application where optics can make an immediate
`Clock distribution is a specific application where optics
`others.
`make
`can
`immediate
`an
`contribution.
`Data interconnections are more demanding, and require the development of
`interconnections
`more
`demanding, and require the development of
`Data
`contribution.
`are
`hybrid Si/GaAs devices and/or heteroepitaxial structures containing both Si and GaAs layers.
`hybrid Si /GaAs devices and /or heteroepitaxial structures containing both Si and GaAs layers.
`The possibilities for future developments in this area are discussed.
`The possibilities for future developments in this area are discussed.
`
`! Introduction
`I. Introduction
`
`In the field of computation, optics is currently best known for its role in analog sig(cid:173)
`In the field of computation, optics is currently best known for its role in analog sig-
`nal processing. Examples include acousto-optic spectrum analyzers, convolvers and correla(cid:173)
`processing.
`nal
`Examples include acousto -optic spectrum analyzers, convolvers and correla-
`tors [1], [2], and systems for forming images from synthetic-aperture radar data [3] ,
`[4] .
`tors [1], [2], and systems for forming images from synthetic- aperture radar data
`[4].
`[3],
`Analog approaches of this kind offer high processing speed, but low accuracy and limited
`kind offer high processing speed, but low accuracy and limited
`approaches
`Analog
`this
`of
`flexibility in terms of the variety of operations that can be performed. These shortcomings
`These shortcomings
`flexibility in terms of the variety of operations that can be performed.
`have lead to a search for applications of optics to digital [5], [6] and other types of
`for applications of optics to digital [5], [6] and other types of
`have
`search
`lead
`to
`a
`high-accuracy numerical computation [7], [8]. However, regardless of the outcome of the new
`However, regardless of the outcome of the new
`high- accuracy numerical computation [7], [8].
`thrusts towards digital-optical computation, it is virtually certain that the vast majority
`thrusts
`towards digital -optical computation, it is virtually certain that the vast majority
`of computation done in the world for many years to come will be performed by microelectronic
`of computation done in the world for many years to come will be performed by microelectronic
`chips.
`While current ideas in digital-optical computing have the potential to strongly
`digital -optical computing have the potential to strongly
`While
`current
`ideas
`chips.
`in
`impact special-purpose digital signal processing, they are very unlikely to invade a signi(cid:173)
`impact special- purpose digital signal processing, they are very unlikely to invade a
`signi-
`ficant fraction of the total computing market in the foreseeable future. It is therefore
`total computing market in the foreseeable future. It is therefore
`fraction
`ficant
`of
`the
`natural to inquire as to whether there exists another role for optics in digital computing,
`natural to inquire as to whether there exists another role for optics in digital
`computing,
`one that has the potential for greater impact on the overall computing market.
`one that has the potential for greater impact on the overall computing market.
`
`A digital computer or computational unit consists primarily of nonlinear devices (logic
`A digital computer or computational unit consists primarily of nonlinear devices (logic
`gates) in which input signals interact to produce output signals, and interconnections
`to produce output signals, and interconnections
`signals
`interact
`which
`input
`gates)
`in
`between such devices or groups of devices of various sizes and complexity.
`The nonlinear
`nonlinear
`between such devices or groups of devices of various sizes and
`The
`complexity.
`interactions required of individual computational elements are realized in optics only with
`required of individual computational elements are realized in optics only with
`interactions
`considerable difficulty. Various kinds of optical light valves have been utilized to real(cid:173)
`Various kinds of optical light valves have been utilized to
`considerable difficulty.
`real-
`ize a multitude of parallel nonlinear elements [9], [10], but the speeds at which such dev(cid:173)
`a multitude of parallel nonlinear elements [91, [10], but the speeds at which such dev-
`ize
`ices can operate are exceedingly slow by comparison with equivalent electronic elements.
`ices can operate are exceedingly slow by comparison with
`electronic
`equivalent
`elements.
`Recent discoveries in the area of optical bistability have generated new interest in con(cid:173)
`discoveries
`the area of optical bistability have generated new interest in con-
`Recent
`in
`structing optical logic gates that are even faster than their electronic counterparts, but
`structing optical logic gates that are even faster than their electronic
`counterparts,
`but
`currently the efficiency of such devices is low and the device concepts are too little
`efficiency
`devices
`currently
`is low and the device concepts are too little
`such
`of
`the
`explored to allow a full assessment of their potential. The construction of optical logic
`explored to allow a full assessment of their potential.
`The construction of
`logic
`optical
`gates with speeds, densities and efficiencies equaling or exceeding those of electronic
`densities
`efficiencies equaling or exceeding those of electronic
`speeds,
`with
`and
`gates
`gates remains problematical, although future progress is certainly possible.
`gates remains problematical, although future progress is certainly possible.
`
`While optics lags behind electronics in the realization of needed nonlinear elements,
`While optics lags behind electronics in the realization of needed
`nonlinear
`elements,
`nonetheless the horizon for electronics is not without clouds. It is generally realized and
`It is generally realized and
`nonetheless the horizon for electronics is not without clouds.
`agreed that the exponential growth of semiconductor chip capabilities can not continue inde(cid:173)
`agreed that the exponential growth of semiconductor chip capabilities can not continue inde-
`finitely, and indeed important limits are beginning to be felt already. These limits arise
`and indeed important limits are beginning to be felt already.
`These limits arise
`finitely,
`not from difficulties associated with the further reduction of gate areas and delays, but
`not from difficulties associated with the further reduction of gate areas
`delays,
`and
`but
`rather from the difficulties associated with interconnections as dimensions are further
`with interconnections as dimensions are further
`difficulties
`associated
`rather
`from
`the
`scaled down and chip areas continue to increase [11], [12]. Indeed, interconnection diffi(cid:173)
`scaled down and chip areas continue to increase [111, [12].
`Indeed, interconnection
`diffi-
`culties extend beyond the chip level, and have major impact at the board level as well [13].
`culties extend beyond the chip level, and have major impact at the board level as well [13].
`
`Given the above facts, it seems natural to inquire as to whether optics might offer
`offer
`Given the above facts, it seems natural to inquire as to
`might
`optics
`whether
`important capabilities in overcoming the interconnect problems associated with microelec(cid:173)
`overcoming the interconnect problems associated with microelec-
`capabilities
`important
`in
`tronic circuits and systems. Encouragement is offered by the fact that the very property of
`Encouragement is offered by the fact that the very property of
`tronic circuits and systems.
`optics that makes it difficult to realize nonlinear elements (it is difficult to make two
`it difficult to realize nonlinear elements (it is difficult to make two
`optics
`makes
`that
`
`/ SPIE Vol. 456 Optical Computing (1984)
`72 / SPIE Vol. 456 Optical Computing (1984)
`72
`
`Ex. 1022
`CISCO SYSTEMS, INC. / Page 1 of 14
`
`

`

`streams of photons interact) is precisely the property desired of an interconnect technol(cid:173)
`streams of photons interact) is precisely the property desired of an
`interconnect
`technol-
`ogy.
`However, at the chip level, optics is likely to be only one element of a hierarchy of
`However, at the chip level, optics is likely to be only one element of a hierarchy of
`ogy.
`interconnect technologies, with optical interconnection networks feeding more conventional
`interconnect technologies, with optical interconnection networks feeding
`more
`conventional .
`interconnect lines constructed from polycrystalline silicon, metal silicides, or metals.
`interconnect lines constructed from polycrystalline silicon, metal silicides, or metals.
`
`There exists an entire hierarchy of interconnect problems for which the implications of
`There exists an entire hierarchy of interconnect problems for which the implications of
`optics should be considered. At one extreme is the problem of machine-to-machine communica(cid:173)
`optics should be considered.
`At one extreme is the problem of machine -to- machine communica-
`tion (local area networks). Such problems are excluded from our consideration here, due to
`tion (local area networks). Such problems are excluded from our consideration here,
`due
`to
`the fact that so much work is already in progress by others. The next level is subsystem to
`the fact that so much work is already in progress by others.
`The next level is subsystem to
`subsystem communication within a single computer. Much less work has been done on optical
`subsystem communication within a single computer. Much less work has been
`done
`optical
`on
`approaches to this problem, but at least one example exists [14]. Again we exclude such
`but at least one example exists [14].
`approaches
`problem,
`Again we exclude such
`this
`to
`problems from consideration here, preferring to concentrate on communication problems at
`problems from consideration here, preferring to concentrate
`communication
`problems
`on
`at
`lower levels of machine structure. Board-to-board communication with optics can be thought
`levels of machine structure.
`Board -to -board communication with optics can be thought
`lower
`of as the problem of constructing an optical data bus within a machine. Some ideas pertinent
`of as the problem of constructing an optical data bus within a machine. Some ideas pertinent
`to this level of interconnection have been published (see, for example, Ref. [151), but
`interconnection
`have been published (see, for example, Ref. [151), but
`level
`this
`to
`of
`again we exclude these problems from consideration. Interconnection within a single board
`again we exclude these problems from consideration. Interconnection within
`single
`board
`a
`(dimensions of approximately 1 ft x 1 ft) is in the realm where our discussions are per(cid:173)
`approximately
`ft x 1 ft) is in the realm where our discussions are per-
`(dimensions
`of
`1
`tinent, as is likewise the problem of interconnection within a wafer (typical dimension 7.5
`tinent, as is likewise the problem of interconnection within a wafer (typical dimension
`7.5
`cm diameter) or within a single chip (typical dimensions 10 mm x 10 mm). Most of our dis(cid:173)
`or within a single chip (typical dimensions 10 mm x 10 mm).
`cm
`diameter)
`Most of our dis-
`cussions will refer to the chip-level problem, but many of the ideas can be extrapolated to
`cussions will refer to the chip -level problem, but many of the ideas can be extrapolated
`to
`the wafer and board levels. In addition, most of the discussion will assume that we are
`board
`In addition, most of the discussion will assume that we are
`wafer
`and
`levels.
`the
`dealing with common metal-oxide-semiconductor (MOS) integrated circuit technology.
`dealing with common metal -oxide -semiconductor (MOS) integrated circuit technology.
`
`The purpose of this paper is to stimulate further thought and research on optical
`The purpose of this paper is to stimulate
`further
`thought
`research
`optical
`and
`on
`interconnections.
`The ideas presented are rather preliminary and underdeveloped, but hope(cid:173)
`The ideas presented are rather preliminary and underdeveloped, but hope-
`interconnections.
`fully they have the potential to serve as a starting point for others in considering how
`fully they have the potential to serve as a starting point for
`others
`considering
`how
`in
`optics might play a more widespread role in computing of the future. Section II reviews the
`might play a more widespread role in computing of the future. Section II reviews the
`optics
`origins and nature of the electronic interconnect problem from the technological point-of-
`origins and nature of the electronic interconnect problem from the
`technological
`point -of-
`view. Section III briefly discusses the interaction between interconnections and algorithmic
`view. Section III briefly discusses the interaction between interconnections and algorithmic
`considerations, thus examining the algorithmic side of the motivation for optical intercon(cid:173)
`considerations, thus examining the algorithmic side of the motivation for optical
`intercon-
`nects. Section VI discusses the potential benefits that optics might bring to a solution to
`Section VI discusses the potential benefits that optics might bring to a solution to
`nects.
`these problems and outlines two fundamentally different optical approaches to interconnec(cid:173)
`these problems and outlines two fundamentally different optical approaches
`interconnec-
`to
`tions, the index-guided approach and the free-space propagation approach. Section V specifi(cid:173)
`tions, the index -guided approach and the free -space propagation approach. Section V specifi-
`cally addresses the problem of clock distribution, while Section VI deals with the problem
`cally addresses the problem of clock distribution, while Section VI deals with
`problem
`the
`of data distribution.
`Finally, Section VII discusses future developments needed if these
`distribution.
`Finally, Section VII discusses future developments needed if these
`data
`of
`ideas are to have practical impact.
`ideas are to have practical impact.
`
`II. The Interconnect Problem - Technological Motivation
`II. The Interconnect Problem - Technological Motivation
`
`The growth of integrated circuit complexity and capabilities experienced since the
`The growth of integrated circuit complexity
`capabilities
`and
`experienced
`since
`the
`birth of the industry has been achieved through a combination of scaling down the minimum
`birth
`industry has been achieved through a combination of scaling down the minimum
`the
`of
`feature size achievable, and a scaling up of the maximum chip size, both subject to the con(cid:173)
`feature size achievable, and a scaling up of the maximum chip size, both subject to the con-
`straint of reasonable yield.
`The scaling process has many beneficial effects, but also
`straint
`reasonable
`The
`scaling process has many beneficial effects, but also
`yield.
`of
`eventually causes difficulties if combined with packing, i.e. the addition of circuitry in
`eventually causes difficulties if combined with packing, i.e. the addition of
`circuitry
`in
`order to realize more complex chips in the same area of silicon that was used before scal(cid:173)
`order
`realize more complex chips in the same area of silicon that was used before scal-
`to
`ing. Here we briefly discuss the good and bad effects of scaling. A more detailed discus(cid:173)
`Here we briefly discuss the good and bad effects of scaling.
`A more detailed
`ing.
`discus-
`sion of the subject is found in Ref. [11] .
`sion of the subject is found in Ref. [11).
`
`Assume that all the dimensions, as well as the voltages and currents on the chip, are
`Assume that all the dimensions, as well as the voltages and currents on the chip,
`are
`scaled down by a factor c(
`(an c( greater than one implies that the sizes and levels are
`scaled
`down
`factor d
`by
`(an c( greater than one implies that the sizes and levels are
`a
`shrinking). Consider first the effects of scaling on device performance.
`Obviously, when
`shrinking).
`Consider first the effects of scaling on device performance.
`Obviously,
`when
`scaling down the linear dimensions of a transistor by c(, the number of transistors that can
`scaling
`down the linear dimensions of a transistor by 0, the number of transistors that can
`be placed on a chip of given size scales up as o( .
`In addition, the power dissipation per
`be placed on a chip of given size scales up as c( .
`In addition, the power
`dissipation
`per
`transistor decreases by a factor c(, due to the fact that both the threshold voltage and the
`transistor
`decreases by a factor 0, due to the fact that both the threshold voltage and the
`supply voltage are scaled down by c(. Finally, we note that the switching delay of a
`supply voltage are scaled down by c(.
`Finally,
`note
`switching
`we
`delay
`that
`the
`of
`a
`transistor is scaled down by c(, due to the fact that the channel length is decreased by that
`transistor is scaled down by 0, due to the fact that the channel length is decreased by that
`factor.
`factor.
`
`Scaling also affects the interconnections between devices. Figure 1 shows the effect
`Scaling also affects the interconnections between devices.
`Figure 1 shows
`effect
`the
`of scaling down a conductor by a factor c(. Since the cross-sectional area of the conductor
`scaling down a conductor by a factor d.
`of
`Since the cross -sectional area of the conductor
`is decreased by a factor c( , the resistance per unit length will increase by a similar fac(cid:173)
`is decreased by a factor c( , the resistance per unit length will increase by a similar
`fac-
`tor.
`If the length of the conductor is scaled down by o(, as simple scaling implies, then
`length of the conductor is scaled down by e(, as simple scaling implies, then
`tor.
`the
`If
`the net increase of resistance is proportional to c(.
`At the same time scaling implies
`the net increase of resistance is proportional to c(.
`At
`scaling
`same
`the
`time
`implies
`changes of the capacitance of the interconnection. Regarding the conductor as one plate of
`of the capacitance of the interconnection.
`changes
`Regarding the conductor as one plate of
`a parallel plate capacitor, scaling 2 down of both linear dimensions of the plate by c( implies
`a parallel plate capacitor, scaling2down of both linear dimensions of the plate by 0 implies
`a decrease of capacitance by c( .
`However, scaling also implies a decrease by c( of the
`decrease
`capacitance
`of
`by
`However, scaling also implies a decrease by c( of the
`a
`c(
`thickness of the oxide insulating layer separating the plates of the capacitor.
`Hence the
`thickness of the oxide insulating layer separating the plates of the capacitor.
`Hence
`the
`capacitance is inversely proportional to the first power of the scaling constant c(. We see
`capacitance
`inversely proportional to the first power of the scaling constant c(. We see
`is
`that the scaling up of resistance and the scaling down of capacitance exactly cancel, leav(cid:173)
`that the scaling up of resistance and the scaling down of capacitance exactly cancel,
`leav-
`ing the RC time constant unchanged.
`ing the RC time constant unchanged.
`
`.
`
`Since gate delays scale down with c( while interconnect delays remain independent of c(,
`Since gate delays scale down with c( while interconnect delays remain independent of
`d,
`
`SP /E Vol 456 Optical Computing (1984) /
`SPIE Vol. 456 Optical Computing (1984) / 73
`73
`
`Ex. 1022
`CISCO SYSTEMS, INC. / Page 2 of 14
`
`

`

`it is clear that eventually a point must be reached where interconnection delays dominate
`that eventually a point must be reached where interconnection delays dominate
`clear
`it
`is
`device delays. However, the situation is actually much worse than the above considerations
`device delays.
`However, the situation is actually much worse than the above
`considerations
`imply, due to the fact that packing usually accompanies scaling, and the lengths of the
`that packing usually accompanies scaling, and the lengths of the
`due
`imply,
`fact
`the
`to
`interconnects required do not scale down with c(. Rather, as the complexity of the circuit
`interconnects required do not scale down with c(.
`Rather, as the complexity of
`circuit
`the
`being realized increases, the distances over which the interconnections must be maintained
`realized
`increases, the distances over which the interconnections must be maintained
`being
`on a chip of fixed area st-ay roughly constant. Statistical considerations show [13] that a
`on a chip of fixed area stay roughly constant.
`Statistical considerations show [13] that
`a
`good approximation to the maximum length L x of the interconnection required is given
`good
`approximation
`maximum
`Lmax of the interconnection required is given
`length
`to
`the
`approximately by
`approximately by
`
`Lmax _ A 1/2
`Lmax =
`
`/2
`
`(1)
`
`where A represents the area of the chip. If the area of the chip stays roughly constant,
`where A represents the area of the chip.
`If the area of the chip
`roughly
`stays
`constant,
`then the maximum interconnect length stays roughly constant, interconnection resistance
`maximum
`interconnect
`stays roughly constant, interconnection resistance
`length
`then
`the
`scales up as c( , and interconnection capacitance stays constant^ yielding an overall scaling
`scales up as c( , and interconnection capacitance stays constant2 yielding an overall scaling
`of interconnect delay that increases in proportion to c( . Note that if chip size is
`interconnect
`proportion
`delay
`Note that if chip size is
`increases
`of
`that
`0 .
`to
`in
`increased, rather than remaining constant, the interconnection problem becomes further exa(cid:173)
`increased, rather than remaining constant, the interconnection problem becomes further
`exa-
`cerbated.
`As a consequence of these considerations, it has been estimated that by the late
`As a consequence of these considerations, it has been estimated that by the late
`cerbated.
`1980's, MOS chip speeds will be limited primarily by interconnect delays [11].
`1980's, MOS chip speeds will be limited primarily by interconnect delays [11].
`
`We refer to
`Another different aspect of scaling is of considerable importance here.
`Another different aspect of scaling is of considerable importance here.
`We
`refer
`to
`the effects of scaling and packing on the numbers of connections required from the outside
`of scaling and packing on the numbers of connections required from the outside
`effects
`the
`world to chips. As the number of elements in a single chip grows, the number of interconnec(cid:173)
`world to chips. As the number of elements in a single chip grows, the number of interconnec-
`tions required from that chip to other chips also increases. There is a well-known empiri(cid:173)
`required from that chip to other chips also increases.
`There is a well -known empiri-
`tions
`cal relation, known as Rent's rule, which specifies that the number of interconnections M
`M
`cal relation, known as Rent's rule, which specifies that the number
`interconnections
`of
`required for a chip consisting of N devices grows as approximately the 0.61 power of N, i.e.
`required for a chip consisting of N devices grows as approximately the 0.61 power of N, i.e.
`
`M ~ N 0 - 61
`N0.61
`M
`
`(2)
`(2)
`
`However, the perimeter of a chip, to which the connections must be made, grows as only the
`However, the perimeter of a chip, to which the connections must be made, grows as
`only
`the
`square root of area, or equivalently as the 0.5 power of N. The disparity caused by the
`The disparity caused by the
`or equivalently as the 0.5 power of N.
`square
`root
`of
`area,
`difference of these two exponents becomes more and more important as the number of devices
`difference of these two exponents becomes more and more important as the number
`devices
`of
`within a chip grows due to scaling and packing. It should be noted that Rentes rule applies
`within a chip grows due to scaling and packing.
`It should be noted that Rent's rule applies
`only to chips consisting of logic elements. Memory cells require fewer interconnections.
`require
`only to chips consisting of logic elements. Memory cells
`interconnections.
`fewer
`In addition, it is required that each chip be a small "random" subset of the entire logic
`is required that each chip be a small "random" subset of the entire logic
`addition,
`it
`In
`system [13].
`system [13].
`
`The predictions of Rent's rule can also be applied to collections of chips on a board
`The predictions of Rent's rule can also be applied to collections of chips on
`board
`a
`(providing the assumptions mentioned above are satisfied). At the chip level, some of the
`At the chip level, some of the
`assumptions mentioned above are satisfied).
`(providing
`the
`limitations implied by Rent's rule can be overcome by the use of metal bump technology for
`limitations implied by Rent's rule can be overcome by the use of metal bump
`technology
`for
`making interconnections possible from the interior of a chip, rather than just from the
`interior of a chip, rather than just from the
`making
`interconnections
`possible
`from
`the
`edges. Optical techniques may ultimately provide an alternate and more flexible means for
`means
`Optical techniques may ultimately provide an alternate and more flexible
`for
`edges.
`providing interconnections directly to the interior of a chip.
`providing interconnections directly to the interior of a chip.
`
`One additional and final implication of scaling should be mentioned. While current
`current
`While
`One additional and final implication of scaling
`mentioned.
`should
`be
`scales down inversely with d, the cross-sectional area through which that current must flow
`down inversely with 5, the cross -sectional area through which that current must flow
`scales
`scales down inversely with c( .
`The net result is that current density increases in propor(cid:173)
`propor-
`The net result is that current density increases in
`scales down inversely with c( .
`tion to c(.
`Such an increase leads to increasing effects of electremigration, by which is
`Such an increase leads to increasing effects of electromigration, by which is
`tion
`to
`0.
`meant the movement of conductor atoms under the influence of electron bombardment.
`The
`bombardment.
`electron
`meant the movement of conductor atoms under the
`influence
`The
`of
`ultimate effect of electromigration is the breaking of conductor lines and the failure of
`electromigration is the breaking of conductor lines and the failure of
`ultimate
`effect
`of
`the chip. The potential of optical interconnections as a means for alleviating electromi(cid:173)
`The potential of optical interconnections as a means for
`electromi-
`alleviating
`the chip.
`gration problems is of considerable interest here.
`gration problems is of considerable interest here.
`
`III. The Interconnect Problem - Algorithmic Motivation
`III. The Interconnect Problem - Algorithmic Motivation
`
`In Section II, some of the technological motivation for considering optical intercon(cid:173)
`intercon-
`optical
`In Section II, some of the technological motivation for considering
`nections was presented. In this section we discuss motivations that arise from algorithmic
`In this section we discuss motivations that arise from algorithmic
`nections
`was presented.
`considerations. We describe several classes of problems that place various degrees of bur(cid:173)
`We describe several classes of problems that place various degrees of
`bur-
`considerations.
`den on interconnections. Examples are drawn primarily from the fields of signal processing
`Examples are drawn primarily from the fields of signal processing
`on interconnections.
`den
`and image processing.
`and image processing.
`
`The first class of operations considered places the smallest burden on interconnec(cid:173)
`interconnec-
`burden
`The first class of operations considered places the
`on
`smallest
`tions.
`We refer to this class as point processing operations. Given a two dimensional
`Given a two dimensional
`class as point processing operations.
`We
`refer
`this
`to
`tions.
`array g(n,m) of data points to be processed and a two dimensional array of processors to
`processors
`array g(n,m) of data points to be processed and a two dimensional
`to
`array
`of
`perform these operations, the result of the processing is described by
`perform these operations, the result of the processing is described by
`
`g(n,m) = NL[f(n,m)]
`g(n,m) = NL[f (n,m) ]
`
`(3)
`(3)
`
`74 / SPIE Vol. 456 Optical Computing (1984)
`/ SPIE Vol. 456 Optical Computing (1984)
`74
`
`Ex. 1022
`CISCO SYSTEMS, INC. / Page 3 of 14
`
`

`

`where NL[] is a (generally nonlinear) function that transforms each value f (n f m) into a new
`where NL[] is a (generally nonlinear) function that transforms each value f(n,m) into a
`new
`value g(n,m), independent of the values of f(n r m) at indices other than (n f m) .
`Since each
`Since each
`independent of the values of f(n,m) at indices other than (n,m).
`value
`g(n,m),
`g(n,m) depends only on one corresponding f(n,m), no communications are required between pro(cid:173)
`g(n,m) depends only on one corresponding f(n,m), no communications are required between pro-
`cessors in the array. Because the interconnections are relatively simple for such problems,
`Because the interconnections are relatively simple for such problems,
`cessors in the array.
`it is likely that the only role for optics here might be in loading and unloading the data
`it is likely that the only role for optics here might be in loading and unloading
`data
`the
`to and from the processor array. If the processor array is a large one f the number of paral(cid:173)
`to and from the processor array. If the processor array is a large one, the number of paral-
`lel inputs and parallel outputs needed for maximum efficiency will be large ,
`implying a
`lel inputs and parallel outputs needed for maximum efficiency
`will
`large,
`implying
`be
`a
`large pin count for the processing chip. Relief can be found by integrating detectors with
`Relief can be found by integrating detectors with
`pin count for the processing chip.
`large
`each processor, thus providing a parallel set of optical input channels. To achieve similar
`each processor, thus providing a parallel set of optical input channels.
`To achieve similar
`relief for output data, the more difficult problem of integrating a source with each proces(cid:173)
`relief for output data, the more difficult problem of integrating a source with each proces-
`sor must be solved. Potential paths to solutions of this problem are discussed in later
`discussed
`sor must be solved.
`Potential paths to solutions of this problem
`are
`later
`in
`sections.
`sections.
`
`As a second level of interconnect difficulties, consider the problem of matrix-matrix
`As a second level of interconnect difficulties, consider the problem
`matrix -matrix
`of
`multiplication.
`Letting capital letters A,B, and C represent matrices, and lower-case
`multiplication.
`C represent matrices, and lower -case
`letters
`Letting
`capital
`and
`A,B,
`letters with subscripts represent particular elements of those matrices, we wish to consider
`letters with subscripts represent particular elements of those mat