`Platform FPGA
`User Guide
`
`UG012 (v2.4) June 30, 2003
`
`R
`
`Ex. 1011
`CISCO SYSTEMS, INC. / Page 1 of 535
`
`
`
`"Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.
`CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064, XC3090, XC4005, and XC5210 are
`registered trademarks of Xilinx, Inc.
`
`R
`
`The shadow X shown above is a trademark of Xilinx, Inc.
`ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator,
`CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and
`Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia,
`MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, RocketIO, SelectIO, SelectRAM, SelectRAM+,
`Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze,
`VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT-
`Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker,
`XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc.
`The Programmable Logic Company is a service mark of Xilinx, Inc.
`All other trademarks are the property of their respective owners.
`Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey
`any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any
`time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for
`the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or
`information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature,
`application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are
`responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with
`respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation
`is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices
`and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown
`or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to
`correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability
`for the accuracy or correctness of any engineering or software support or assistance provided to a user.
`Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without
`the written consent of the appropriate Xilinx officer is prohibited.
`The contents of this manual are owned and copyrighted by Xilinx. Copyright 1994-2003 Xilinx, Inc. All Rights Reserved. Except as stated
`herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form
`or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent
`of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and
`publicity, and communications regulations and statutes.
`
`Virtex-II Pro™ Platform FPGA User Guide
`
`www.xilinx.com
`1-800-255-7778
`
`UG012 (v2.4) June 30, 2003
`
`Ex. 1011
`CISCO SYSTEMS, INC. / Page 2 of 535
`
`
`
`Virtex-II Pro™ Platform FPGA User Guide
`UG012 (v2.4) June 30, 2003
`
`The following table shows the revision history for this document. All revision publications are electronic only (PDF)
`unless otherwise noted.
`
`Version
`
`Revision
`
`01/31/02
`
`10/14/02
`
`12/04/02
`
`01/23/03
`
`1.0
`
`2.0
`
`2.1
`
`2.2
`
`04/11/03
`
`2.3
`
`(Print Edition.) Initial Xilinx release.
`
`(Print Edition.) Updated and reprinted. New Virtex-II Pro family members and
`packages. Revised I/O support information.
`
`Added full support for 3.3V I/O standards PCI-X, LVTTL, and LVCMOS33.
`• Added wire-bond package FG676 for XC2VP20, 30, and 40. New package diagram
`(Figure 5-62) and pinout diagrams (Figure 5-11 through Figure 5-15). Revised
`Table 5-6.
`• Removed pinout diagrams and other references for XC2VP40FF1517.
`• Revised material in, and added Figure 4-4 to, section “Mixed Voltage Environments,”
`page 288.
`• Clariified explanation of banks 4/5 VCCO settings for configuration vs. operation in
`section “Special VCCO Requirements during Configuration and Readback,” page
`289.
`• Table 3-38, Table 3-39: Corrected package type FG672 to FF672, and added package
`type FG676.
`• Deleted (former) Table 3-3, Power-Up Timing Characteristics, and replaced it with a
`hyperlink to Data Sheet Module 3.
`• Deleted (former) Table 1-5, Multiplier Switching Characteristics, and replaced it with
`a hyperlink to Data Sheet Module 3.
`• Changed attribute CLOCK_FEEDBACK to CLK_FEEDBACK.
`• Clarifying text added to section “Phase Shift Enable - PSEN” in Chapter 3.
`• Additional implementation rule added to section “DCI in Virtex-II Pro Hardware” in
`Chapter 3.
`• Corrections made in command line, key file, and key file command line equivalent in
`section “Creating Keys” in Chapter 3.
`• Added device-specific parameters to step 15 of “Single Device Configuration
`Sequence” in Chapter 4.
`• Section “Data Loading” in Chapter 4: Corrected maximum frequency for SelectMAP
`configuration without BUSY handshaking to 5 MHz.
`• Table 4-8: Corrected maximum SelectMAP frequency (FCC_SelectMAP) to 50 MHz.
`• Appendix A, “BitGen and PROMGen Switches and Options”: Updated all command-
`line options to correlate with development tools and their documentation.
`• Table 3-59: Added numerous LVDS primitives to this table, including new differential
`termination primitives.
`• Added new section “LVDS Input HDL Examples.”
`• Changed Figure 3-120 to show internal rather than external differential input
`termination.
`• Various minor edits.
`
`UG012 (v2.4) June 30, 2003
`
`www.xilinx.com
`1-800-255-7778
`
`Virtex-II Pro™ Platform FPGA User Guide
`
`Ex. 1011
`CISCO SYSTEMS, INC. / Page 3 of 535
`
`
`
`Version
`
`06/30/03
`
`2.4
`
`Revision
`
`• Corrected Location Constraints syntax, multiple instances.
`• Added Figure 3-23, page 85 and associated explanatory text.
`• Added HDL code for resetting the DCM after configuration in section “External
`Feedback,” page 87.
`• Modified Banking Rules in section “DCI in Virtex-II Pro Hardware,” page 228.
`• Added reference to Answer Record 13012 in section “SSTL2_ I_DCI, SSTL2_II_DCI,”
`page 229.
`• Corrected command-line equivalent statements for bitstream encryption key files in
`section “Creating Keys,” page 260.
`• Added new section “Abort,” page 302, to section “Master SelectMAP Programming
`Mode”.
`• Corrected shading property of GND pin in symbol key, all diagrams, section “Pinout
`Diagrams,” page 355.
`• Numerous additional minor edits.
`
`Virtex-II Pro™ Platform FPGA User Guide
`
`www.xilinx.com
`1-800-255-7778
`
`UG012 (v2.4) June 30, 2003
`
`Ex. 1011
`CISCO SYSTEMS, INC. / Page 4 of 535
`
`
`
`Table of Contents
`
`Preface: About This Guide
`Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
`Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
`Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
`
`Chapter 1: Introduction to the Virtex-II Pro™ FPGA Family
`The Next Logical Revolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`Built for Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
`Legacy of Leadership. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
`Packets Everywhere . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`Bridge, Anyone? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`Simplifying Complexity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
`Time Is Money . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
`Flexibility Is Money. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
`Not Being Discrete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
`
`Chapter 2: Timing Models
`Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
`CLB / Slice Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
`General Slice Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
`Slice Distributed RAM Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . 27
`Slice SRL Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
`Block SelectRAM Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
`Embedded Multiplier Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
`IOB Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
`IOB Input Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
`IOB Output Timing Model and Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
`IOB 3-State Timing Model and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
`Pin-to-Pin Timing Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
`Global Clock Input to Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
`Global Clock Setup and Hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
`Digital Clock Manager Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
`Operating Frequency Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
`Input Clock Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
`Output Clock Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`Miscellaneous DCM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
`Additional Timing Models in Other Publications:
`PPC405 Processor Block and RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . 60
`
`Virtex-II Pro™ Platform FPGA User Guide
`UG012 (v2.4) June 30, 2003
`
`www.xilinx.com
`1-800-255-7778
`
`5
`
`Ex. 1011
`CISCO SYSTEMS, INC. / Page 5 of 535
`
`
`
`R
`
`IBM PPC405 Processor Block Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
`RocketIO Transceiver Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
`
`Chapter 3: Design Considerations
`Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
`RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Processor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
`Clock Distribution Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
`Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
`Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
`Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
`Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`Secondary Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
`Digital Clock Managers (DCMs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
`Clock De-Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
`Legacy Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
`Frequency Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
`Phase Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
`DCM Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
`Block SelectRAM™ Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
`Synchronous Dual-Port and Single-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
`Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
`Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
`VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
`Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
`Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
`Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
`Initialization in VHDL or Verilog Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
`Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
`Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
`VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
`Distributed SelectRAM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
`Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
`Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
`VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
`Ports Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
`Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
`Initialization in VHDL or Verilog Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
`Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
`Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
`VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
`Look-Up Tables as Shift Registers (SRLs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
`Shift Register Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
`
`6
`
`www.xilinx.com
`1-800-255-7778
`
`Virtex-II Pro™ Platform FPGA User Guide
`UG012 (v2.4) June 30, 2003
`
`Ex. 1011
`CISCO SYSTEMS, INC. / Page 6 of 535
`
`
`
`Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
`Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
`Initialization in VHDL and Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
`Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
`Attributes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
`Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
`Fully Synchronous Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
`Static-Length Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
`VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
`Large Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
`Virtex-II Pro CLB Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
`Wide-Input Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
`Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
`Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
`Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
`Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
`VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
`Sum of Products (SOP) Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
`Virtex-II Pro CLB Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
`VHDL Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
`Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
`VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
`Embedded Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
`Two’s-Complement Signed Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
`Library Primitives and Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
`Two Multipliers in a Single Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
`VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
`Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
`Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
`VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
`Single-Ended SelectIO™-Ultra Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
`Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
`Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
`Overview of Supported I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
`Library Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
`Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
`Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
`Digitally Controlled Impedance (DCI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
`Xilinx DCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
`Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
`DCI in Virtex-II Pro Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
`Double-Data-Rate (DDR) I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
`Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
`Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
`Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
`VHDL and Verilog Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
`
`Virtex-II Pro™ Platform FPGA User Guide
`UG012 (v2.4) June 30, 2003
`
`www.xilinx.com
`1-800-255-7778
`
`R
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`7
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`Ex. 1011
`CISCO SYSTEMS, INC. / Page 7 of 535
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`Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
`Initialization in VHDL or Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
`Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
`Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
`VHDL and Verilog Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
`LVDS I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
`Creating an LVDS Input/Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
`Creating an LVDS Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
`Creating an LVDS Output 3-State Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
`Creating a Bidirectional LVDS Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
`LDT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
`LDT Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
`LVPECL I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
`Creating an LVPECL Input/Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
`Creating an LVPECL Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
`Bitstream Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
`What DES Is . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
`How Triple DES is Different. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
`Classification and Export Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
`Creating Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
`Loading Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
`Loading Encrypted Bitstreams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
`VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
`CORE Generator System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
`The CORE Generator System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
`CORE Generator Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
`Core Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
`Xilinx IP Solutions and the IP Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
`CORE Generator Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
`Virtex-II Pro IP Cores Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
`
`Chapter 4: Configuration
`Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
`Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
`Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
`Configuration Process and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
`Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
`Mixed Voltage Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
`Configuration Solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
`System Advanced Configuration Environment (System ACE™) Series . . . . . . . . . . 289
`Configuration PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
`Flash PROMs With a CPLD Configuration Controller. . . . . . . . . . . . . . . . . . . . . . . . . 294
`Embedded Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
`PROM and System ACE Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
`Software Support and Data Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
`iMPACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
`Programming Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
`Boundary Scan Interconnect Testing for Virtex-II Pro Devices. . . . . . . . . . . . . . . . . . 297
`
`8
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`www.xilinx.com
`1-800-255-7778
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`Virtex-II Pro™ Platform FPGA User Guide
`UG012 (v2.4) June 30, 2003
`
`Ex. 1011
`CISCO SYSTEMS, INC. / Page 8 of 535
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`Master Serial Programming Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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