`
`
`0
`
`R
`
`Virtex-II Pro™ Platform FPGAs:
`Introduction and Overview
`
`DS083-1 (v2.4.1) March 24, 2003
`
`0
`
`0
`
`Advance Product Specification
`
`Summary of Virtex-II Pro Features
`•
`High-Performance Platform FPGA Solution, Including
`-
`Up to twenty-four RocketIO™ embedded
`multi-gigabit transceivers
`Up to four IBM® PowerPC® RISC processor blocks
`-
`Based on Virtex™-II Platform FPGA Technology
`-
`Flexible logic resources
`-
`SRAM-based in-system configuration
`-
`Active Interconnect technology
`
`(cid:127)
`
`Table 1: Virtex-II Pro FPGA Family Members
`
`SelectRAM™+ memory hierarchy
`-
`Dedicated 18-bit x 18-bit multiplier blocks
`-
`High-performance clock management circuitry
`-
`SelectI/O™-Ultra technology
`-
`XCITE Digitally Controlled Impedance (DCI) I/O
`-
`Virtex-II Pro family members and resources are shown in
`Table 1.
`
`RocketIO
`Transceiver
`Blocks
`
`PowerPC
`Processor
`Blocks
`
`4
`
`4
`
`8
`
`8
`
`0
`
`1
`
`1
`
`2
`
`Device
`
`XC2VP2
`
`XC2VP4
`
`XC2VP7
`
`XC2VP20
`
`CLB (1 = 4 slices =
`max 128 bits)
`
`Logic
`Cells(1)
`
`3,168
`
`6,768
`
`11,088
`
`20,880
`
`Slices
`
`1,408
`
`3,008
`
`4,928
`
`9,280
`
`Max Distr
`RAM (Kb)
`
`44
`
`94
`
`154
`
`290
`
`18 X 18 Bit
`Multiplier
`Blocks
`
`Block SelectRAM+
`
`18 Kb
`Blocks
`
`Max Block
`RAM (Kb)
`
`DCMs
`
`Maximum
`User
`I/O Pads
`
`12
`
`28
`
`44
`
`88
`
`12
`
`28
`
`44
`
`88
`
`216
`
`504
`
`792
`
`1,584
`
`4
`
`4
`
`4
`
`8
`
`8
`
`204
`
`348
`
`396
`
`564
`
`644
`
`XC2VP30
`
`XC2VP40
`
`XC2VP50
`
`8
`
`0(2) or 12
`
`0(2) or 16
`
`XC2VP70
`
`16 or 20
`
`0(2) or 20
`XC2VP100
`XC2VP125 0(2), 20, or 24
`
`2
`
`2
`
`2
`
`2
`
`2
`
`4
`
`30,816
`
`13,696
`
`43,632
`
`19,392
`
`53,136
`
`23,616
`
`74,448
`
`33,088
`
`99,216
`
`44,096
`
`125,136
`
`55,616
`
`428
`
`606
`
`738
`
`1,034
`
`1,378
`
`1,738
`
`136
`
`192
`
`232
`
`328
`
`444
`
`556
`
`136
`
`192
`
`232
`
`328
`
`444
`
`556
`
`2,448
`
`3,456
`
`4,176
`
`5,904
`
`7,992
`
`10,008
`
`8
`
`8
`
`8
`
`12
`
`12
`
`804
`
`852
`
`996
`
`1,164
`
`1,200
`
`Notes:
`1. Logic Cell = (1) 4-input LUT + (1)FF + Carry Logic
`2. These devices can be ordered in a configuration without RocketIO transceivers. See Table 3 for package configurations.
`
`RocketIO Transceiver Features
`(cid:127)
`Full-Duplex Serial Transceiver (SERDES) Capable of
`Baud Rates from 600 Mb/s to 3.125 Gb/s
`120 Gb/s Duplex Data Rate (24 Channels)
`(cid:127)
`(cid:127) Monolithic Clock Synthesis and Clock Recovery (CDR)
`(cid:127)
`Fibre Channel, 10G Fibre Channel, Gigabit Ethernet,
`10 Gb Attachment Unit Interface (XAUI), and
`Infiniband-Compliant Transceivers
`8-, 16-, or 32-bit Selectable Internal FPGA Interface
`8B /10B Encoder and Decoder (optional)
`
`(cid:127)
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`
`50Ω /75Ω on-chip Selectable Transmit and Receive
`Terminations
`Programmable Comma Detection
`Channel Bonding Support (from 2 to 24 Channels)
`Rate Matching via Insertion/Deletion Characters
`Four Levels of Selectable Pre-Emphasis
`Five Levels of Output Differential Voltage
`Per-Channel Internal Loopback Modes
`2.5V Transceiver Supply Voltage
`
`© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
`All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
`
`DS083-1 (v2.4.1) March 24, 2003
`Advance Product Specification
`
`www.xilinx.com
`1-800-255-7778
`
`1
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 1 of 406
`
`

`

`General Description
`
`R
`
`PowerPC RISC Block Features
`(cid:127)
`Embedded 300+ MHz Harvard Architecture Block
`(cid:127)
`Low Power Consumption: 0.9 mW/MHz
`(cid:127)
`Five-Stage Data Path Pipeline
`(cid:127)
`Hardware Multiply/Divide Unit
`(cid:127)
`Thirty-Two 32-bit General Purpose Registers
`(cid:127)
`16 KB Two-Way Set-Associative Instruction Cache
`(cid:127)
`16 KB Two-Way Set-Associative Data Cache
`(cid:127) Memory Management Unit (MMU)
`-
`64-entry unified Translation Look-aside Buffers (TLB)
`-
`Variable page sizes (1 KB to 16 MB)
`Dedicated On-Chip Memory (OCM) Interface
`Supports IBM CoreConnect™ Bus Architecture
`Debug and Trace Support
`Timer Facilities
`
`(cid:127)
`(cid:127)
`(cid:127)
`(cid:127)
`
`-
`
`-
`
`Virtex-II Pro Platform FPGA Technology
`(cid:127)
`SelectRAM+ Memory Hierarchy
`-
`Up to 10 Mb of True Dual-Port RAM in 18 Kb block
`SelectRAM+ resources
`Up to 1,738 Kb of distributed SelectRAM+
`resources
`High-performance interfaces to external memory
`-
`Arithmetic Functions
`-
`Dedicated 18-bit x 18-bit multiplier blocks
`-
`Fast look-ahead carry logic chains
`Flexible Logic Resources
`-
`Up to 111,232 internal registers/latches with Clock
`Enable
`Up to 111,232 look-up tables (LUTs) or cascadable
`variable (1 to 16 bits) shift registers
`- Wide multiplexers and wide-input function support
`-
`Horizontal cascade chain and Sum-of-Products
`support
`Internal 3-state busing
`-
`High-Performance Clock Management Circuitry
`-
`Up to twelve Digital Clock Manager (DCM) modules
`·
`Precise clock de-skew
`·
`Flexible frequency synthesis
`·
`High-resolution phase shifting
`16 global clock multiplexer buffers in all parts
`-
`Active Interconnect Technology
`-
`Fourth-generation segmented routing structure
`-
`Fast, predictable routing delay, independent of
`fanout
`Deep sub-micron noise immunity benefits
`-
`SelectIO™-Ultra Technology
`-
`Up to 1,200 user I/Os
`-
`Twenty-two single-ended standards and
`six differential standards
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`(cid:127)
`
`-
`
`-
`-
`-
`
`-
`
`·
`·
`
`Programmable LVCMOS sink/source current (2 mA
`to 24 mA) per I/O
`XCITE Digitally Controlled Impedance (DCI) I/O
`PCI/ PCI-X support (1)
`Differential signaling
`·
`840 Mb/s Low-Voltage Differential Signaling I/O
`(LVDS) with current mode drivers
`Bus LVDS I/O
`HyperTransport (LDT) I/O with current driver
`buffers
`Built-in DDR input and output registers
`·
`Proprietary high-performance SelectLink
`technology for communications between Xilinx
`devices
`·
`High-bandwidth data path
`·
`Double Data Rate (DDR) link
`· Web-based HDL generation methodology
`SRAM-Based In-System Configuration
`-
`Fast SelectMAP™ configuration
`-
`Triple Data Encryption Standard (DES) security
`option (bitstream encryption)
`IEEE 1532 support
`-
`Partial reconfiguration
`-
`Unlimited reprogrammability
`-
`Readback capability
`-
`Supported by Xilinx Foundation™ and Alliance
`Series™ Development Systems
`-
`Integrated VHDL and Verilog design flows
`-
`ChipScope™ Integrated Logic Analyzer
`0.13 µm Nine-Layer Copper Process with 90 nm
`High-Speed Transistors
`1.5V (VCCINT) core power supply, dedicated 2.5V
`VCCAUX auxiliary and VCCO I/O power supplies
`IEEE 1149.1 Compatible Boundary-Scan Logic Support
`Flip-Chip and Wire-Bond Ball Grid Array (BGA)
`Packages in Standard 1.00 mm Pitch
`(cid:127)
`Each Device 100% Factory Tested
`General Description
`The Virtex-II Pro family contains platform FPGAs for
`designs that are based on IP cores and customized mod-
`ules. The family incorporates multi-gigabit transceivers and
`PowerPC CPU blocks in Virtex-II Pro Series FPGA architec-
`ture. It empowers complete solutions for telecommunica-
`tion, wireless, networking, video, and DSP applications.
`The leading-edge 0.13 µm CMOS nine-layer copper pro-
`cess and Virtex-II Pro architecture are optimized for high
`performance designs in a wide range of densities. Combin-
`ing a wide variety of flexible features and IP cores, the
`Virtex-II Pro family enhances programmable logic design
`capabilities and is a powerful alternative to mask-pro-
`grammed gate arrays.
`
`1. Refer to XAPP653 for more information.
`
`2
`
`www.xilinx.com
`1-800-255-7778
`
`DS083-1 (v2.4.1) March 24, 2003
`Advance Product Specification
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 2 of 406
`
`

`

`R
`
`Virtex-II Pro™ Platform FPGAs: Introduction and Overview
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`Architecture
`Virtex-II Pro Array Overview
`Virtex-II Pro devices are user-programmable gate arrays
`with various configurable elements and embedded blocks
`optimized for high-density and high-performance system
`designs. Virtex-II Pro devices implement the following func-
`tionality:
`(cid:127)
`Embedded high-speed serial transceivers enable data
`bit rate up to 3.125 Gb/s per channel.
`Embedded IBM PowerPC 405 RISC processor blocks
`provide performance of 300+ MHz.
`SelectIO-Ultra blocks provide the interface between
`package pins and the internal configurable logic. Most
`popular and leading-edge I/O standards are supported
`by the programmable IOBs.
`Configurable Logic Blocks (CLBs) provide functional
`elements for combinatorial and synchronous logic,
`including basic storage elements. BUFTs (3-state
`buffers) associated with each CLB element drive
`dedicated segmentable horizontal routing resources.
`Block SelectRAM+ memory modules provide large
`18 Kb storage elements of True Dual-Port RAM.
`Embedded multiplier blocks are 18-bit x 18-bit
`dedicated multipliers.
`Digital Clock Manager (DCM) blocks provide
`self-calibrating, fully digital solutions for clock
`distribution delay compensation, clock multiplication
`and division, and coarse- and fine-grained clock phase
`shifting.
`A new generation of programmable routing resources called
`Active Interconnect Technology interconnects all of these
`elements. The general routing matrix (GRM) is an array of
`routing switches. Each programmable element is tied to a
`switch matrix, allowing multiple connections to the general
`routing matrix. The overall programmable interconnection is
`hierarchical and designed to support high-speed designs.
`All programmable elements,
`including
`the
`routing
`resources, are controlled by values stored in static memory
`cells. These values are loaded in the memory cells during
`configuration and can be reloaded to change the functions
`of the programmable elements.
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`Virtex-II Pro Features
`This section briefly describes Virtex-II Pro features. For
`more details, refer to Virtex-II Pro™ Platform FPGAs: Func-
`tional Description.
`RocketIO Multi-Gigabit Transceivers
`The RocketIO Multi-Gigabit Transceiver, based on Mind-
`speed’s SkyRail technology, is a flexible parallel-to-serial
`and serial-to-parallel embedded
`transceiver used
`for
`high-bandwidth
`interconnection between buses, back-
`planes, or other subsystems.
`
`Multiple user instantiations in an FPGA are possible, provid-
`ing up to 120 Gb/s of full-duplex raw data transfer. Each
`channel can be operated at a maximum data transfer rate of
`3.125 Gb/s.
`Each RocketIO transceiver implements:
`(cid:127)
`Serializer and deserializer (SERDES)
`(cid:127) Monolithic clock synthesis and clock recovery (CDR)
`(cid:127)
`Fibre Channel, 10G Fibre Channel, Gigabit Ethernet,
`XAUI, and Infiniband-compliant transceivers
`8-, 16-, or 32-bit selectable FPGA interface
`8B/10B encoder and decoder with bypassing option on
`each channel
`Channel bonding support (2 to 24 channels)
`-
`Elastic buffers for inter-chip deskewing and
`channel-to-channel alignment
`Receiver clock recovery tolerance of up to
`75 non-transitioning bits
`50Ω /75Ω on-chip selectable transmit and receive
`terminations
`Programmable comma detection
`(cid:127)
`Rate matching via insertion/deletion characters
`(cid:127)
`Automatic lock-to-reference function
`(cid:127)
`(cid:127) Optional transmit and receive data inversion
`(cid:127)
`Four levels of pre-emphasis support
`(cid:127)
`Per-channel serial and parallel transmitter-to-receiver
`internal loopback modes
`Cyclic Redundancy Check (CRC) support
`(cid:127)
`PowerPC 405 Processor Block
`The PPC405 RISC CPU can execute instructions at a sus-
`tained rate of one instruction per cycle. On-chip instruction
`and data cache reduce design complexity and improve sys-
`tem throughput.
`The PPC405 features include:
`(cid:127)
`PowerPC RISC CPU
`-
`Implements the PowerPC User Instruction Set
`Architecture (UISA) and extensions for embedded
`applications
`Thirty-two 32-bit general purpose registers (GPRs)
`Static branch prediction
`Five-stage pipeline with single-cycle execution of
`most instructions, including loads/stores
`Unaligned and aligned load/store support to cache,
`main memory, and on-chip memory
`Hardware multiply/divide for faster integer
`arithmetic (4-cycle multiply, 35-cycle divide)
`Enhanced string and multiple-word handling
`-
`Big/little endian operation support
`-
`Storage Control
`-
`Separate instruction and data cache units, both
`two-way set-associative and non-blocking
`
`(cid:127)
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`-
`-
`-
`
`-
`
`-
`
`DS083-1 (v2.4.1) March 24, 2003
`Advance Product Specification
`
`www.xilinx.com
`1-800-255-7778
`
`3
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 3 of 406
`
`

`

`Architecture
`
`R
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`Eight words (32 bytes) per cache line
`16 KB array Instruction Cache Unit (ICU), 16 KB
`array Data Cache Unit (DCU)
`- Operand forwarding during instruction cache line fill
`-
`Copy-back or write-through DCU strategy
`-
`Doubleword instruction fetch from cache improves
`branch latency
`Virtual mode memory management unit (MMU)
`-
`Translation of the 4 GB logical address space into
`physical addresses
`Software control of page replacement strategy
`Supports multiple simultaneous page sizes ranging
`from 1 KB to 16 MB
`(cid:127) OCM controllers provide dedicated interfaces between
`Block SelectRAM+ memory and processor block
`instruction and data paths for high-speed access
`PowerPC timer facilities
`-
`64-bit time base
`-
`Programmable interval timer (PIT)
`-
`Fixed interval timer (FIT)
`- Watchdog timer (WDT)
`Debug Support
`-
`Internal debug mode
`-
`External debug mode
`-
`Debug Wait mode
`-
`Real Time Trace debug mode
`-
`Enhanced debug support with logical operators
`-
`Instruction trace and trace-back support
`-
`Forward or backward trace
`(cid:127)
`Two hardware interrupt levels support
`(cid:127)
`Advanced power management support
`Input/Output Blocks (IOBs)
`IOBs are programmable and can be categorized as follows:
`(cid:127)
`Input block with an optional single data rate (SDR) or
`double data rate (DDR) register
`(cid:127) Output block with an optional SDR or DDR register and
`an optional 3-state buffer to be driven directly or
`through an SDR or DDR register
`Bidirectional block (any combination of input and output
`configurations)
`These registers are either edge-triggered D-type flip-flops
`or level-sensitive latches.
`IOBs support the following single-ended I/O standards:
`(cid:127)
`LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
`PCI-X compatible (133 MHz and 66 MHz) at 3.3V(1)
`(cid:127)
`PCI compliant (66 MHz and 33 MHz) at 3.3V(1)
`(cid:127)
`(cid:127) GTL and GTLP
`(cid:127)
`HSTL (1.5V and 1.8V, Class I, II, III, and IV)
`(cid:127)
`SSTL (1.8V and 2.5V, Class I and II)
`
`-
`-
`
`-
`-
`
`The DCI I/O feature automatically provides on-chip termina-
`tion for each single-ended I/O standard.
`The IOB elements also support the following differential sig-
`naling I/O standards:
`(cid:127)
`LVDS and Extended LVDS (2.5V)
`(cid:127)
`BLVDS (Bus LVDS)
`(cid:127)
`ULVDS
`(cid:127)
`LDT
`(cid:127)
`LVPECL (2.5V)
`Two adjacent pads are used for each differential pair. Two or
`four IOB blocks connect to one switch matrix to access the
`routing resources.
`Configurable Logic Blocks (CLBs)
`CLB resources include four slices and two 3-state buffers.
`Each slice is equivalent and contains:
`(cid:127)
`Two function generators (F & G)
`(cid:127)
`Two storage elements
`(cid:127)
`Arithmetic logic gates
`(cid:127)
`Large multiplexers
`(cid:127) Wide function capability
`(cid:127)
`Fast carry look-ahead chain
`(cid:127)
`Horizontal cascade chain (OR gate)
`The function generators F & G are configurable as 4-input
`look-up tables (LUTs), as 16-bit shift registers, or as 16-bit
`distributed SelectRAM+ memory.
`In addition,
`the
`two storage elements are either
`edge-triggered D-type flip-flops or level-sensitive latches.
`Each CLB has internal fast interconnect and connects to a
`switch matrix to access general routing resources.
`Block SelectRAM+ Memory
`The block SelectRAM+ memory resources are 18 Kb of
`True Dual-Port RAM, programmable from 16K x 1 bit to
`512 x 36 bit, in various depth and width configurations.
`Each port is totally synchronous and independent, offering
`three "read-during-write" modes. Block SelectRAM+ mem-
`ory is cascadable to implement large embedded storage
`blocks. Supported memory configurations for dual-port and
`single-port modes are shown in Table 2.
`
`Table 2: Dual-Port and Single-Port Configurations
`16K x 1 bit
`4K x 4 bits
`1K x 18 bits
`
`8K x 2 bits
`
`2K x 9 bits
`
`512 x 36 bits
`
`18 X 18 Bit Multipliers
`A multiplier block is associated with each SelectRAM+
`memory block. The multiplier block
`is a dedicated
`18 x 18-bit 2s complement signed multiplier, and is opti-
`mized for operations based on the block SelectRAM+ con-
`tent on one port. The 18 x 18 multiplier can be used
`independently of
`the block SelectRAM+
`resource.
`
`1. Refer to XAPP653 for more information.
`
`4
`
`www.xilinx.com
`1-800-255-7778
`
`DS083-1 (v2.4.1) March 24, 2003
`Advance Product Specification
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 4 of 406
`
`

`

`R
`
`Virtex-II Pro™ Platform FPGAs: Introduction and Overview
`
`Read/multiply/accumulate operations and DSP filter struc-
`tures are extremely efficient.
`Both the SelectRAM+ memory and the multiplier resource
`are connected to four switch matrices to access the general
`routing resources.
`Global Clocking
`The DCM and global clock multiplexer buffers provide a
`complete solution for designing high-speed clock schemes.
`Up to twelve DCM blocks are available. To generate
`deskewed internal or external clocks, each DCM can be
`used to eliminate clock distribution delay. The DCM also
`provides 90-, 180-, and 270-degree phase-shifted versions
`of its output clocks. Fine-grained phase shifting offers
`high-resolution phase adjustments in increments of 1/256 of
`the clock period. Very flexible frequency synthesis provides
`a clock output frequency equal to a fractional or integer mul-
`tiple of the input clock frequency. For exact timing parame-
`ters, see Virtex-II Pro™ Platform FPGAs: DC and Switching
`Characteristics.
`Virtex-II Pro devices have 16 global clock MUX buffers, with
`up to eight clock nets per quadrant. Each clock MUX buffer
`can select one of the two clock inputs and switch glitch-free
`from one clock to the other. Each DCM can send up to four
`of its clock outputs to global clock buffers on the same edge.
`Any global clock pin can drive any DCM on the same edge.
`Routing Resources
`The IOB, CLB, block SelectRAM+, multiplier, and DCM ele-
`ments all use the same interconnect scheme and the same
`access to the global routing matrix. Timing models are
`shared, greatly improving the predictability of the perfor-
`mance of high-speed designs.
`There are a total of 16 global clock lines, with eight available
`per quadrant. In addition, 24 vertical and horizontal long
`lines per row or column, as well as massive secondary and
`local
`routing
`resources, provide
`fast
`interconnect.
`Virtex-II Pro buffered interconnects are relatively unaffected
`by net fanout, and the interconnect layout is designed to
`minimize crosstalk.
`Horizontal and vertical routing resources for each row or
`column include:
`(cid:127)
`24 long lines
`(cid:127)
`120 hex lines
`(cid:127)
`40 double lines
`(cid:127)
`16 direct connect lines (total in all four directions)
`
`Boundary Scan
`Boundary-scan instructions and associated data registers
`support a standard methodology for accessing and config-
`uring Virtex-II Pro devices, complying with IEEE standards
`1149.1 and 1532. A system mode and a test mode are
`implemented. In system mode, a Virtex-II Pro device will
`continue to function while executing non-test bound-
`ary-scan instructions. In test mode, boundary-scan test
`instructions control the I/O pins for testing purposes. The
`Virtex-II Pro Test Access Port (TAP) supports BYPASS,
`PRELOAD, SAMPLE, IDCODE, and USERCODE non-test
`instructions. The EXTEST, INTEST, and HIGHZ test instruc-
`tions are also supported.
`Configuration
`Virtex-II Pro devices are configured by loading the bitstream
`into internal configuration memory using one of the follow-
`ing modes:
`(cid:127)
`Slave-serial mode
`(cid:127) Master-serial mode
`(cid:127)
`Slave SelectMAP mode
`(cid:127) Master SelectMAP mode
`(cid:127)
`Boundary-Scan mode (IEEE 1532)
`A Data Encryption Standard (DES) decryptor is available
`on-chip to secure the bitstreams. One or two triple-DES key
`sets can be used to optionally encrypt the configuration data.
`The Xilinx System Advanced Configuration Enviornment
`(System ACE) family offers high-capacity and flexible solu-
`tion for FPGA configuration as well as program/data storage
`for the processor. See DS080, System ACE CompactFlash
`Solution for more information.
`Readback and Integrated Logic Analyzer
`Configuration data stored in Virtex-II Pro configuration
`memory can be read back for verification. Along with the
`configuration data, the contents of all flip-flops/latches, dis-
`tributed SelectRAM+, and block SelectRAM+ memory
`resources can be read back. This capability is useful for
`real-time debugging.
`The Xilinx ChipScope Integrated Logic Analyzer (ILA) cores
`and Integrated Bus Analyzer (IBA) cores, along with the
`ChipScope Pro Analyzer software, provide a complete solu-
`tion for accessing and verifying user designs within
`Virtex-II Pro devices.
`
`DS083-1 (v2.4.1) March 24, 2003
`Advance Product Specification
`
`www.xilinx.com
`1-800-255-7778
`
`5
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 5 of 406
`
`

`

`IP Core and Reference Support
`
`R
`
`IP Core and Reference Support
`Intellectual Property is part of the Platform FPGA solution.
`In addition to the existing FPGA fabric cores, the list below
`shows some of the currently available hardware and soft-
`ware
`intellectual properties specially developed
`for
`Virtex-II Pro by Xilinx. Each IP core is modular, portable,
`Real-Time Operating System (RTOS) independent, and
`CoreConnect compatible for ease of design migration.
`Refer to www.xilinx.com/ipcenter for the latest and most
`complete list of cores.
`Hardware Cores
`(cid:127)
`Bus Infrastructure cores (arbiters, bridges, and more)
`(cid:127) Memory cores (DDR, Flash, and more)
`(cid:127)
`Peripheral cores (UART, IIC, and more)
`(cid:127)
`Networking cores (ATM, Ethernet, and more)
`Software Cores
`(cid:127)
`Boot code
`(cid:127)
`Test code
`(cid:127)
`Device drivers
`(cid:127)
`Protocol stacks
`(cid:127)
`RTOS integration
`(cid:127)
`Customized board support package
`
`Virtex-II Pro Device/Package
`Combinations and Maximum I/Os
`Offerings include ball grid array (BGA) packages with
`1.0 mm pitch. In addition to traditional wire-bond intercon-
`nects, flip-chip interconnect is used in some of the BGA
`offerings. The use of flip-chip interconnect offers more I/Os
`than are possible in wire-bond versions of the similar pack-
`ages. Flip-chip construction offers the combination of high
`pin count and excellent power dissipation.
`table
`The Virtex-II Pro device/package combination
`(Table 3) details the maximum number of user I/Os and
`RocketIO transceivers for each device and package using
`wire-bond or flip-chip technology.
`(cid:127)
`FG denotes Wirebond fine-pitch BGA (1.00 mm pitch).
`(cid:127)
`FF denotes FlipChip fine-pitch BGA (1.00 mm pitch).
`The FF1148 and FF1696 packages have no RocketIO
`transceivers bonded out. Extra SelectIO-Ultra resources
`occupy available pins in these packages, resulting in a
`higher user I/O count. FF1148 and FF1696 packages are
`available for the XC2VP40, XC2VP50, XC2VP100, and
`XC2VP125 devices only.
`The I/Os per package count includes all user I/Os except
`the 15 control pins (CCLK, DONE, M0, M1, M2, PROG_B,
`PWRDWN_B, TCK, TDI, TDO, TMS, HSWAP_EN, DXN,
`DXP, and RSVD), VBATT, and RocketIO transceiver pins.
`
`Table 3: Virtex-II Pro Device/Package Combinations and Maximum Number of Available I/Os
`
`Pitch
`(mm)
`
`Size
`(mm)
`
`Pkg
`
`Available User I/Os / Available RocketIO Transceivers
`
`XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 XC2VP125
`
`FG256
`
`1.00 17 x 17 140 / 4
`
`140 / 4
`
`FG456
`
`1.00 23 x 23 156 / 4
`
`248 / 4
`
`248 / 8
`
`FG676
`
`1.00 26 x 26
`
`404 / 8
`
`416 / 8
`
`416 / 8
`
`FF672
`
`1.00 27 x 27 204 / 4
`
`348 / 4
`
`396 / 8
`
`FF896
`
`1.00 31 x 31
`
`FF1152
`
`1.00 35 x 35
`
`FF1148
`
`1.00 35 x 35
`
`FF1517
`
`1.00 40 x 40
`
`FF1704
`
`1.00
`
`FF1696
`
`1.00
`
`42.5 x
`42.5
`
`42.5 x
`42.5
`
`396 / 8
`
`556 / 8
`
`556 / 8
`
`564 / 8
`
`644 / 8
`
`692 / 12
`
`692 / 16
`
`804 / 0(1) 812 / 0(1)
`
`852 / 16
`
`964 / 16
`
`996 / 20
`
`1,040 / 20
`
`1,040 / 20
`
`1,164 / 0(1) 1,200 / 0(1)
`
`Notes:
`1. The RocketIO transceivers in devices in the FF1148 and FF1696 packages are not bonded out to the package pins.
`2. Consult Xilinx for package options supporting 24 RocketIO transceivers.
`
`6
`
`www.xilinx.com
`1-800-255-7778
`
`DS083-1 (v2.4.1) March 24, 2003
`Advance Product Specification
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 6 of 406
`
`

`

`R
`
`Virtex-II Pro™ Platform FPGAs: Introduction and Overview
`
`Maximum Performance
`Maximum RocketIO transceiver and PowerPC processor block performance varies, depending on the package style and
`speed grade. See Table 4 for details. Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics contains the rest of
`the FPGA fabric performance parameters.
`
`Table 4: Maximum RocketIO Transceiver and Processor Block Performance
`Speed Grade
`
`RocketIO Transceiver Wirebond (FG)
`
`RocketIO Transceiver FlipChip (FF)
`
`PowerPC Processor Block
`
`-7
`
`2.5
`
`3.125
`
`400
`
`-6
`
`2.5
`
`3.125
`
`350
`
`-5
`
`2.0
`
`2.0
`
`300
`
`Units
`
`Gb/s
`
`Gb/s
`
`MHz
`
`Virtex-II Pro Ordering Information
`Virtex-II Pro ordering information is shown in Figure 1.
`
`Example: XC2VP7-7FG456C
`
`Device Type
`Speed Grade
`(-5, -6, -7)
`
`Temperature Range:
` C = Commercial (Tj = 0˚C to +85˚C)
` I = Industrial (Tj = -40˚C to +100˚C)
`
`Number of Pins
`
`Package Type
`
`DS083_02_052902
`
`Figure 1: Virtex-II Pro Ordering Information
`
`Revision History
`This section records the change history for this module of the data sheet.
`
`Date
`
`Version
`
`Revision
`
`01/31/02
`
`06/13/02
`
`09/03/02
`
`09/27/02
`
`11/20/02
`
`01/20/03
`
`1.0
`
`2.0
`
`2.1
`
`2.2
`
`2.3
`
`2.4
`
`03/24/03
`
`2.4.1
`
`Initial Xilinx release.
`
`New Virtex-II Pro family members. New timing parameters per speedsfile v1.62.
`
`Updates to Table 1 and Table 3. Processor Block information added to Table 4.
`
`In Table 1, correct max number of XC2VP30 I/Os to 644.
`
`Add bullet items for 3.3V I/O features.
`
`(cid:127)
`(cid:127)
`
`(cid:127)
`(cid:127)
`
`In Table 3, add FG676 package option for XC2VP20, XC2VP30, and XC2VP40.
`Remove FF1517 package option for XC2VP40.
`
`Correct number of single-ended I/O standards from 19 to 22.
`Correct minimum RocketIO serial speed from 622 Mbps to 600 Mbps.
`
`DS083-1 (v2.4.1) March 24, 2003
`Advance Product Specification
`
`www.xilinx.com
`1-800-255-7778
`
`7
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 7 of 406
`
`

`

`Virtex-II Pro Data Sheet
`
`R
`
`Virtex-II Pro Data Sheet
`The Virtex-II Pro Data Sheet contains the following modules:
`(cid:127)
`Virtex-II Pro™ Platform FPGAs: Introduction and
`Overview (Module 1)
`Virtex-II Pro™ Platform FPGAs: Functional Description
`(Module 2)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`Virtex-II Pro™ Platform FPGAs: DC and Switching
`Characteristics (Module 3)
`Virtex-II Pro™ Platform FPGAs: Pinout Information
`(Module 4)
`
`8
`
`www.xilinx.com
`1-800-255-7778
`
`DS083-1 (v2.4.1) March 24, 2003
`Advance Product Specification
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 8 of 406
`
`

`

`R
`
`0
`
`Virtex-II Pro™ Platform FPGAs:
`Functional Description
`
`DS083-2 (v2.7) June 2, 2003
`
`0
`
`0
`
`Advance Product Specification
`
`Processor Reference Guide and the PowerPC 405 Pro-
`cessor Block Reference Guide. For detailed RocketIO
`transceiver digital/ analog design considerations, refer to
`RocketIO Transceiver User Guide. For a detailed descrip-
`tion of the FPGA fabric (CLB, IOB, DCM, etc.), refer to the
`Virtex-II Pro Platform FPGA User Guide.
`All of the documents above, as well as a complete listing
`and description of Xilinx-developed Intellectual Property
`cores for Virtex-II Pro, are available on the Xilinx website at
`www.xilinx.com/virtex2pro.
`
`Virtex-II Pro Compared to Virtex-II Devices
`Virtex-II Pro devices are built on the Virtex-II FPGA archi-
`tecture. Most FPGA features are identical to Virtex-II
`devices. Differences are described below:
`(cid:127)
`The Virtex-II Pro FPGA family is the first to incorporate
`embedded PPC405 cores and RocketIO MGTs.
`VCCAUX, the auxiliary supply voltage, is 2.5V instead of
`3.3V as for Virtex-II devices. Advanced processing at
`0.13 µm has resulted in a smaller die, faster speed,
`and lower power consumption.
`Virtex-II Pro devices are neither bitstream-compatible nor
`pin-compatible with Virtex-II devices. However, Virtex-II
`designs can be compiled into Virtex-II Pro devices.
`SSTL3, AGP-2X/AGP, LVPECL_33, LVDS_33, and
`LVDSEXT_33 standards are not supported.
`The open-drain output pin TDO does not have an
`internal pullup resistor.
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`(cid:127)
`
`Table 1: Protocols Supported by RocketIO Transceiver
`Channels
`I/O Baud Rate
`Reference Clock
`(Lanes)
`(Gb/s)
`Rate (MHz)
`
`Protocol
`
`Virtex-II Pro Array Functional Description
`
`DCM
`
`RocketIO™
`Multi-Gigabit Transceiver
`
`Processor Block
`
`CLB
`
`CLB
`
`CLB
`
`CLB
`
`Configurable
`Logic
`
`Block SelectRAM
`
`Multipliers and
`
`DS083-1_01_010802
`
`SelectIO™-Ultra
`Figure 1: Virtex-II Pro Generic Architecture Overview
`This module describes the following Virtex-II Pro functional
`components, as shown in Figure 1:
`(cid:127)
`Embedded RocketIO™ Multi-Gigabit Transceiver (MGT)
`Processor block with embedded IBM® PowerPC™ 405
`(cid:127)
`RISC CPU core (PPC405) and integration circuitry.
`FPGA fabric based on Virtex-II architecture.
`(cid:127)
`For a description of PPC405 embedded core programming
`models and internal core operations, refer to the PowerPC
`
`Functional Description: RocketIO
`Multi-Gigabit Transceiver (MGT)
`This section summarizes the features of the RocketIO
`multi-gigabit transceiver. For an in-depth discussion of the
`RocketIO MGT, including digital and analog design consid-
`erations, refer to the RocketIO Transceiver User Guide.
`
`Overview
`The embedded RocketIO multi-gigabit transceiver is based
`on Mindspeed’s SkyRail™ technology. Up to twenty-four
`transceivers are available. The transceiver is designed to
`operate at any baud rate in the range of 622 Mb/s to
`3.125 Gb/s per channel. This includes specific baud rates
`used by various standards as listed in Table 1.
`
`1.06
`2.12
`3.1875 (1)
`1.25
`3.125
`2.5
`0.840 – 3.125
`up to 3.125
`
`53
`106
`159.375
`62.5
`156.25
`125
`42.00 – 156.25
`up to 156.25
`
`Fibre Channel
`
`1
`
`1
`4
`1, 4, 12
`1, 2, 3, 4, ...
`1, 2, 3, 4, ...
`
`Gigabit Ethernet
`10Gbit Ethernet
`Infiniband
`Aurora
`Custom Protocol
`Notes:
`1. Virtex-II Pro MGT can support the 10G Fibre Channel data rates of
`3.1875 Gb/s across 6" of standard FR-4 PCB and one connector
`(Molex 74441 or equivalent) with a bit error rate of 10-12 or better.
`
`© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
`All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
`
`DS083-2 (v2.7) June 2, 2003
`Advance Product Specification
`
`www.xilinx.com
`1-800-255-7778
`
`1
`
`Ex. 1010
`CISCO SYSTEMS, INC. / Page 9 of 406
`
`

`

`Functional Description: RocketIO Multi-Gigabit Transceiver (MGT)
`
`R
`
`The serial bit rate need not be configured in the transceiver,
`as the operating frequency is implied by the received data
`and reference clock applied.
`The RocketIO transceiver consists of the Physical Media
`Attachment (PMA) and Physical Coding Sublayer (PCS).
`The PMA contains the serializer and deserializer. The PCS
`contains the bypassable 8B/10B encoder/ decoder, elastic
`
`buffers, and Cyclic Redundancy Check (CRC) units. The
`encoder and decoder handle the 8B/10B coding scheme.
`The elastic buffers support the clock correction (rate match-
`ing) and channel bonding features. The CRC units perform
`CRC generation and checking.
`Figure 2 shows a high-level block diagram of the RocketIO
`transceiver and its FPGA interface signals.
`
`PACKAGE
`PINS
`
`MULTI-GIGABIT TRANSCEIVER CORE
`
`FPGA FABRIC
`
`POWERDOWN
`
`RXRECCLK
`RXPOLARITY
`RXREALIGN
`RXCOMMADET
`ENPCOMMAALIGN
`ENMCOMMAALIGN
`
`RXCHECKINGCRC
`RXCRCERR
`
`RXDATA[15:0]
`RXDATA[31:16]
`
`RXNOTINTABLE[3:0]
`RXDISPERR[3:0]
`RXCHARISK[3:0]
`RXCHARISCOMMA[3:0]
`RXRUNDISP[3:0]
`RXBUFSTATUS[1:0]
`ENCHANSYNC
`CHBONDDONE
`CHBONDI[3:0]
`CHBONDO[3:0]
`
`RXLOSSOFSYNC
`RXCLKCORCNT
`
`TXBUFERR
`TXFORCECRCERR
`TXDATA[15:0]
`TXDATA[31:16]
`
`TXBYPASS8B10B[3:0]
`TXCHARISK[3:0]
`TXCHARDISPMODE[3:0]
`TXCHARDISPVAL[3:0]
`
`TXKERR[3:0]
`TXRUNDISP[3:0]
`
`TXPOLARITY
`TXINHIBIT
`
`LOOPBACK[1:0]
`TXRESET
`RXRESET
`REFCLK
`REFCLK2
`REFCLKSEL
`BREFCLK
`BREFCLK2
`RXUSRCLK
`RXUSRCLK2
`TXUSRCLK
`TXUSRCLK2
`
`DS083-2_04_090402
`
`AVCCAUXRX
`
`2.5V RX
`
`Power Down
`
`VTRX
`
`Termination Supply RX
`
`CRC
`Check
`
`RX
`Elastic
`Buffer
`
`Channel Bonding
`and
`Clock Correction
`
`Deserializer
`
`Comma
`Detect
`Realign
`
`8B/10B
`Decoder
`
`Parallel Loopback Path
`
`Clock
`Manager
`
`Serial Loopback Path
`
`TX
`FIFO
`
`8B/10B
`Encoder
`
`CRC
`
`Serializer
`
`Output
`Polarity
`
`RXP
`RXN
`
`TXP
`TXN
`
`GNDA
`
`TX/RX GND
`
`AVCCAUXTX
`
`2.5V TX
`
`VTTX
`
`Termination Supply TX
`
`Figure 2: Ro