UNITED STATES PATENT AND TRADEMARKOFFICE
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`LG ELECTRONICS, INC.,
`Petitioner
`
`¥.
`
`ATI TECHNOLOGIES ULC,
`Patent Owner
`
`
`
`Case IPR2015-00325
`Patent 7,742,053
`
`
`
`DECLARATION OF INVENTOR LAURENT LEFEBVRE
`REGARDING THE INVENTION DATE OF U.S. PATENT NO.7,742,053
`
`Mail Step “Patent Board”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O, Box 1450
`Alexandna, VA 22313-1450
`
`ATI 2006
`
`LG v. ATI
`
`IPR2015-00325
`
`AMD1044_0256603
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`ATI Ex. 2103
`IPR2023-00922
`Page 1 of 61
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`ATI Ex. 2103
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`IPR2023-00922
`Page 1 of 61
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`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`LG ELECTRONICS, INC.,
`Petitioner
`
`¥.
`
`ATI TECHNOLOGIES ULC,
`Patent Owner
`
`
`
`Case IPR2015-00325
`Patent 7,742,053
`
`
`
`DECLARATION OF INVENTOR LAURENT LEFEBVRE
`REGARDING THE INVENTION DATE OF U.S. PATENT NO.7,742,053
`
`Mail Step “Patent Board”
`Patent Trial and Appeal Board
`U.S. Patent and Trademark Office
`P.O, Box 1450
`Alexandna, VA 22313-1450
`
`ATI 2006
`
`LG v. ATI
`
`IPR2015-00325
`
`AMD1044_0256603
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`ATI Ex. 2103
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`Table of Contents
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`BACKGROUND00. cece ccte ce ecne ce teccsaeeetaeeescseeeestaesenenteseniaees
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`beeteteees I
`
`CONCEPTION ooo ccccccceccccec cece ceseeseesteeeeceseeecsscstssniscrteieenesasisensessees
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`vevenseees 3
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`A.
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`B
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`C.—
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`D
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`R400 Architecture Proposal... cece cc cteeseeneeeeeeees
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`betetee 4
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`R400 Top Level Speetfieattonn.cece eeeere eee
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`beeceeeee 4
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`R400 Shader Processor... cece cece cece vtec eeeneeesneseee
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`beseeetees 6
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`R400 Sequencer Specification oo... ccc cette eee
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`becseeeee 6
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`I,
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`2.
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`R400 Sequencer Specification (Version 0.4): August
`24, QOD cece eeeree tere rte tee eesensecetiesnitessteeereaeenes
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`veteeeeees 7
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`R400 Sequencer Specification (Version 2.0): April 19,
`QOD? oie cee cece cee c eee ceneeeeeeeeeeeeeeeeeeeeceeceeceeeteeseeentenees
`
`ne 17
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`il.
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`DILIGENCE ooo. cece cee eee cceee ene ceneeeeseeetecseeseesereeseesneeseseeneessees
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`bees 19
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`A.—| Periodically Updated the R400 Sequencer Specification.........
`veces 20
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`B.
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`MyColleagues and I Continuously Developed and
`Debugged Emulation Code and RTL Code for the R400...........
`
`veseees 21
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`TESTING SHOWED THAT THE RTL IMPLEMENTATION
`WORKEDFOR ITS INTENDED PURPOSE |... cceeeeereeteeee
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`Leveeees 26
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`DILIGENCE CALENDAR ooo. cceceeceecc ete cece ce te cnet eeueeeeeeeseenaeeneees
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`levees 31
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`VI.
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`EXHIBITS ooo cece ceceeeceeeeeeeeeereeeeeeneeneeeeneenesecseectsetseeneetnuseeetsnreneess
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`Levees 37
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`-il-
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`I, Laurent Lefebvre, declare as follows:
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`I.
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`BACKGROUND
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`l.
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`I am a computer-graphics hardware architect at AMD Inc. | have been
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`designing computer-graphics processors for the past fifteen years. | specialize in
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`sequencers, shaders, 3D-computer graphics, and integrated-circuit design.
`
`2.
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`From September 2000 to November2006, | worked as an engineer
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`and hardware architect for ATI Technologies Inc. (“ATI”). It is my understanding
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`that ATT hired me to develop technologies for the R400, whichis a graphics
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`processor.
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`3.
`
`Unhke conventional graphics processors at the time, the R400 used a
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`unified shader for both pixel commands and vertex commands—two types of
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`commands required to produce an image. Conventional graphics processors had
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`separate shaders for pixel commands and vertex commands. But a unifted shader,
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`like the R400°s unified shader, enhances functionality and effictency by allowing
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`the same shader complex to be used for both pixel commands and vertex
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`commands.
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`4,
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`The R400 includes manydifferent functional blocks (e.g., the
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`sequencer, shader pipe, prumitive assembly, texture cache, texture pipe, raster
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`engine, display, etc.). See, e.g., Ex. 2053, p. 6. The PowerPoint slide titled Block
`
`-|-
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`Responsibility (reproduced below) shows the ATI office responsible for designing
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`each block.
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`Block Responsibility
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`fa.
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`5,
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`For the R400 project, | was responsible for the sequencerblock,
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`which 1s the block that manages the execution of pixel commands and vertex
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`commands for the untfied shader. In particular, | drafted the high-level
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`specification that describes the sequencer block's functionality, and | wrote
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`emulator code for the sequencer block. In addition, | was also co-responsible for
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`emulating the shader pipe block and the export block.
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`ae
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`6.
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`I am one of the named inventors of U.S. Patent No. 7,742,053 (“the
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`°053 patent”). The other named mventors are Steve Morein and Andy Gruber. We
`
`collectively conceived of the graphics-processing system claimed in the °033
`
`patent no later than August 24, 2001, while working on the R400. See infra Part IE.
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`A team of my colleagues and I, which totaled about one hundred engineers,
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`worked on the R400 nearly every business day from at least August 24, 2001 to
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`September 29, 2003. See infra Parts HI, V. No later than the third quarter of 2002,
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`we made a GPU in register-transfer-language (“RTL”) code that worked to process
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`a first triangle. See infra Part IV.
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`H. CONCEPTION
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`7.
`
`No later than August 24, 2001, Steve Morein, Andy Gruber, and I
`
`collectively conceived of the graphtcs-processing system imthe °053 patent. We
`
`each contributed different aspects to this system, Steve Morein came up with the
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`idea for a unified shader. This is shown, for example, in documents titled “R400
`
`Architecture Proposal” and “R400 Top Level Specification.” Ex. 2040, p. 1; Ex.
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`2041, p. 1. Andy Gruber was the lead for the shader processor. This is shown, for
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`example, in a documenttitled “Shader Processor.” Ex. 2042, p. 1. And I was the
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`lead for the sequencer block. This is shown, for example, in a documenttitled
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`“R400 Sequencer Specification.” /:.g., Ex. 2007, p.
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`|. | explain each of these
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`documents in turn below.
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`A. R400 Architecture Proposal
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`8.
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`Steve Morein authored the “R400 Architecture Proposal.” Ex. 2040,
`
`p. 1. In this proposai, the R400 includes a unified shader that performs both pixel
`
`operations and vertex operations. See id. at 9. The R400 also includes a unified
`
`processing pipe (1.¢., a single programmable pipeline for 2D video, 3D vertex, and
`
`3D pixel operations). See id. at 6 (“The most ambitious feature in this design is the
`
`“truly unified pipe’: a single programmablepipeline.”). With a single pipeline for
`
`both pixel commands and vertex commands, the graphics processor had higher
`
`color precision and the ability to support more registers, compared with a
`
`conventional graphics pipeline. See ic.
`
`B. R400 Top Level Specification
`
`9.
`
`Steve Morein also authored the “R400 Top Level Specification,”
`
`which sets forth the high-level architecture for the R400. Ex. 2041, p. I. As shown
`
`in this document, the R400 Top Level Specification includes a sequencer. Seee.g,
`
`id. at 27-28, 30. The sequencer managesthe instructions for the unified shader. See
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`id. at 11 (‘Before starting the processing .. . the rasterizer (which includes the
`
`sequencer for the shader prpeline) checks to make sure that there are enoughfree
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`registers in the pipeline for the pixel shader program.”), 27 (“The raster engine...
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`contains the sequencer for the shader pipe.”’).
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`10,
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`The R400 Top Level Specification includes a block diagram ofthe
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`sequencer’s control flow(reproduced below for reference).
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`
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`fa. at 30,
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`11.
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`This block diagram includes three arbitrators': (1) a “vertex/pixel
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`vector arbitrator” at the top of the diagram; (2) a “texture arbitrator” onthe left side
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`of the diagram; and (3) a “texture arbitrator” on the right side of the diagram. See
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`id. The “texture arbitrator” on the left side is mislabeled. This arbitrator should be
`
`labeled “ALUarbitrator” to correspond to the ALU reservationstations. I describe
`
`the control flowfor this block diagram in Part 11.D.1 of this declaration.
`
`C. R400 Shader Processor
`
`12.
`
`Andy Gruber authored the “Shader Processor,” which describes the
`
`shader archttecture, interfaces, partitioning, and timing of the shader. Ex, 2042, p.
`
`1. The shader processor, also called a pipeline, has sixteen pipes. See fd. at 5
`
`(“There will be four sets of four shader pipes.”). This pipeline processes a
`
`sequence of instructions in both texture clauses and ALU clauses. /d. at 8
`
`D. R400 Sequencer Specification
`
`13.
`
`1 authored the “R400 Sequencer Specificatton,” which1s the
`
`architectural specification for the R400 sequencer block. Ex. 2007, p. 1. There are
`
`
`
`' The term “arbitrator” is interchangeable with the term “arbiter.” See, ¢.¢.,
`
`Ex, 2023, p, 10 (identifying the control flow diagram as: “Figure 2; Reservation
`
`stations and arbiters’).
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`at least thirty three revisions of this specification. See Ex. 2039, pp. 4-5; Exs. 2007-
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`38. Each revision updates the specification.
`
`14.
`
`I developed two versions of the sequencer’s control flow. See Ex.
`
`2010; Ex, 2028. When I filed the patent application that led to the ’053 patent, |
`
`intended this patent application to cover both versions of the sequencer’s control
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`flow.
`
`15.
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`The first version, described in Version 0.4 of the R400 Sequencer
`
`Specification, was designed for sixteen vertex clauses and sixteen pixel clauses.
`
`See Ex. 2010, pp. 5, 14-15. ATI presented this version to Microsoft to see whether
`
`the R400 was compatible with the applicatton-programming interface (“API’) that
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`Microsoft was developing, called DX 10. Microsoft rejected this version because
`
`Microsoft’s API required a sequencerthat could process an unlimited numberof
`
`clauses. To be compatible with this requirement, | developed a second version of
`
`the sequencer control flow. This second version is described in Version 2.0 of the
`
`R400 Sequencer Specification. See Ex. 2028. I explain these versions in turn
`
`below.
`
`1, R400 Sequencer Specification (Version 0.4); August 24, 200]
`
`16.
`
`Version 0.4 of the R400 Sequencer Specification ts dated August 24,
`
`2001. See Ex. 2010, p. 3; see aéso Ex. 2043 (for the log entry on August 24, 2001).
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`This version includes the same sequencer-block diagram as the sequencer-block
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`diagram in the R400 Top Level Specification (reproduced again below for
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`convenience). Compare Ex. 2010, p. 5 with Ex. 2041, p. 30. Version 0.4 also
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`includes an example of the flow of pixels and vertices through the system. See Ex.
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`U dwn i
`m2 Em
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`LU rie 0
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`2010, pp. 3, 17-19.
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`Ex. 2010, p. 5.
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`17,
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`The sequencer has two sets of reservation stations, one for pixels and
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`one for vertices. /d. at 4, 5. A representation of the two sets of reservation stations
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`is shown below. Each set has eight ALU reservation stations and eight texture
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`reservation stations, /d. Each reservation station stores clauses. /d. These clauses
`
`contain a sequence of instructions./a! at 4 (“[the sequencer] .
`
`.
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`. executes all of the
`
`instructions in a clause”); see a/se Ex, 2042, p. 8 (“instructions in a clause will be
`
`executed sequentially”).
`
`Pixel Reservation Stations
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`Vertex Reservation Stations
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`18.
`
`Clauses flow downeach set of reservation stations. See Ex. 2010, pp.
`
`4, 5. Pixel clauses flow down the set of pixel reservation stations, and vertex
`
`clauses flow down the vertex reservation stations. See ia. Reservation stations
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`touch the arbiter, so the ALU arbiters and the texture arbiters can select clauses
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`traveling down the reservation stations. See id at 17 (“the control packet continues
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`Sie
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`to travel down the path of reservation stations until all clauses have been
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`executed’).
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`19.
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`The arbiter/arbitration logic has two levels of arbitration, collectively
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`shown in red on the figure below.
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`Vertex Clauses
`
`Pixel Clauses
`
`}
`festsaoe
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`m_>|
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`
`—
`
`“SEQ arbitrates between the Pixel FIFO and the Vertex FIFO”
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`20.
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`Thefirst level of arbitration is between ALU clauses and texture
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`clauses for both the vertex set of reservation stations and the pixel set of
`
`reservation stations. This first level of arbitration is represented by the ALU
`
`arbitrators and texture arbitrators labeled in the figure above. ALU arbitration logic
`
`«10+
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`chooses one of the eight potentially pending ALU clauses stored within the ALU
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`reservation stations. See fd. at 14-15. Texture arbitration logic chooses one of the
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`eight potentially pending texture clauses stored within the texture reservation
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`stations. See fel at 14.
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`21.
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`For the second level of arbitration, the arbitration logic selects
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`between the pixel and the vertex. See id. at 17 (2) (SEQ arbitrates between the
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`Pixel FIFO and the Vertex FIFO”), 18 (4) (SEQ arbitrates between Pixel FIFO
`
`and Vertex FIFO”). So, not only does the arbiter select which clauses to execute,
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`the arbiter also selects which order to execute pixels and vertices. Sve id. at 4 (“a
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`pixel can pass a vertex and a vertex can pass a pixel”).
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`Ko be
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`The ALU arbitration and the texture arbitration give priority to
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`reservation stations/clauses closer to the bottom of the pipeline. See ia. at 4. After
`
`this arbitration selects winning pixei and vertex clauses, the pixel/vertex arbitration
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`logic selects between the pixel and the vertex. /d at 17 (2}, 18 (4). Vertices
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`generally have priority. /d. at 17 (2). When a vertex is not pending or the register
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`files do not have open space for a vertex, the arbiter selects a pixel. /d. at 18 (4).
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`23.
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`Once arbitration logic selects the pixel/vertex clauses, the sequencer’ s
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`arbitration logic provides the clauses to a registerfile m the shader pipe. Seeid. at
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`pp. 17 (5) (SEQ constructs a control packet for the vector and sends it to the first
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`reservation station (the FIFO in front of texture state machine 0, or TSMO FIFO)
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`the control packet contains the state pomter, the tag to the position cache and a
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`register file base pomter.”), 17 (9) (“ASMOaccepts the control packet (after being
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`selected by the ASM arbiter) and gets the instructions for ALU clause 0 from the
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`global instruction store”).
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`24.
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`The shader pipe, as of Version 0.4 of the R400 Sequencer
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`Specification (reproduced belowfor reference), has four physical register file
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`memories per shaderpipeline. /d. at 10.
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`fed.
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`25.
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`Each register file is coupled to a bank of ALUs. See iaat 11. The
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`gray area of the Figure reproduced belowshowsthe logical viewof the four
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`register files within the shader pipe as software would see it. /@. The Figure also
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`- |a-
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`shows an ALUbank, a texture unit, an instruction store/cache, and a constant store.
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`See il
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`fed.
`
`26.
`
`In the Figure reproduced above, the sequencer block comprises the
`
`instruction store and the constant store, In a different representation, reproduced
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`below, the instruction store and the constant store are within the sequencer block.
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`«4.
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`Clause®= Ray
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`cst
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`Weeder
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`fa at 12.
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`27.
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`Later versions of the R400 Sequencer Specification showthe
`
`sequencer and the shader pipe within the R400 architecture. Sec, e.g, Ex. 2012, pp.
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`3, 5. The architecture in Version 0.6 of the R400 Sequencer Specificationis
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`reproduced below.
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`~ 15 ~
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`id. at 3.
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`28.
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`Following Version 0.6, the R400 architecture was kept in the R400
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`Sequencer Specification. See, e.2., Ex, 2039, p. 7. A version of the R400
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`Sequencer Specification dated May |, 2003 includes the R400 architecture
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`reproduced below. The general role of the sequencer within this architecture did
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`not change. And most inputs‘outputs to/from the sequencer stay consistent.
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`- 16-
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`a]
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`FETCH STATE
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`i
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`:
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`ALU BANK 1
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`mal
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`Tet6g]——____* +
`c
` ==|
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`|
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`13
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`Tar e
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`ie
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`ld.
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`2. R400 Sequencer Specification (Version 2.0): April 19, 2002
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`29,
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`The sequencer’s control flow changed in Version 2.0 of the R400
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`Sequencer Specification, See Ex. 2028, pp. 5, 6, 10. Version 2.0 is dated April 19,
`
`2002, See Ex, 2028, p. 5; see also Ex. 2044 (for the log entry on April 19, 2002).
`
`30, Again, the reason for the change was to meet the requirements of
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`Microsoft's API, called DX10. In particular, Microsoft wanted the sequencerto be
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`able to run shaders with an unlimited number of clauses/instructions. The first
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`version selected from sixteen vertex clauses and sixteen pixel clauses. See Ex,
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`2010, pp. 3, 14-15. To meet Microsoft's specifications, | changed the sequencer’s
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`control flow. The new control flow is shown below.
`
` (ripags Aa tote
`
`Ex. 2028, p. 10.
`
`31.
`
`In this version, there are two reservation stations, one reservation
`
`station for vertices (VTX RS) and one reservation station for pixels (PIX RS). See
`
`id, The texture threads and the ALUthreads are not separated. See ie. at 23
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`(“Without separate ‘texture clauses’ and “ALU clauses’ we need to know which
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`instructions to dispatch to the Texture Unit and which to the ALU unit.”); see alse
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`id. at 6 (using the term thread), Each reservation station stores threads at specified
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`-18-
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`locations with status bits indicating which engine 1s needed for execution. Sveid. at
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`25 (“A thread lives in a given location in the buffer during its entire life.”’), 26
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`(“Status Bits’ needed include: .. . [a] Texture/ALU engine [identifier]”).
`
`32.
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` Anarbiter, labeled as “ExecArbiter,” selects threads for an ALU
`
`engine and a texture engine. See id. at 25. The arbiter selects a thread based on
`
`FIFO. See id. at pp. 6 (The arbitrator will give priority to older threads.”), 25
`
`(“T]he buffer has FIFO qualities in that the threads leave in the order that they
`
`enter.”), The thread is then read out of a reservation station. See id. at 26. Once the
`
`texture engine or the ALU engine executes the thread, the respective engine returns
`
`the thread to the location from which the thread originated. See id. (“[The thread]
`
`is returned to the buffer (at the same place) withits status updated onceall possible
`
`sequential instructions have been executed.”).
`
`33.
`
`This version is present in later revisions of the Sequencer
`
`Specification. Sve, ¢.g., Ex. 2039, p. 9.
`
`Ht. DILIGENCE
`
`34.
`
`After conceiving of the destgn for the R400, my colleagues and I
`
`worked to implement it. This work is shownby at least two things: (1) I
`
`periodically updated the R400 Sequencer Specification: and (2) my colleagues and
`
`I continuously developed, tested, and debugged emulation code and RTL code tor
`
`-19-
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`the R400, including the other components that supported and interacted with the
`
`sequencer.
`
`A. I Periodically Updated the R400 SequencerSpecification
`
`35.
`
`During development, the architectural leads for each block wrote
`
`specifications to describe the structure and function ofthe blocks. See Ex. 2042, p.
`
`| (showing that specifications were used by destgners). I was the architectural lead
`
`for the sequencer block, so I developed the R400 Sequencer Specification.
`
`36.
`
` lupdated the R400 Sequencer Specification approximately every two
`
`to three weeks, See Ex. 2039, pp. 4-5 (outlining edits to the document). There are
`
`at least thirty three revisions of this document. See id; see also Exs, 2007-38. The
`
`revisions span from at least May 25, 2001 to August 29, 2003. See Ex. 2043, p. 2
`
`(first log entry May 25, 2001), Ex. 2044, p.
`
`| (last log entry August 29, 2003); Ex.
`
`2039, pp. 4-5 (showing 33 versions from May7, 2001 to May 1, 2003).
`
`37.
`
`Having multiple revisions during development is typical. Each
`
`revision showed progress during the previous week(s). During interim periods, the
`
`project team worked on outstanding tssues. See e.g, Ex. 2018, p. 35 (ending the
`
`document with a section labeled “Open Issues”).
`
`-?0-
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`B. MyColleagues and [ Continuously Developed and Debugged Emulation
`Code and RTL Code for the R400
`
`38.
`
`Inthe beginning of development, only a handful of engineers were
`
`assigned to the R400 project. But by late 2001 or early 2002, ATI assigned over
`
`one hundred project managers/designers to implement and test the R400. During
`
`these two years, many project managers/designers transitioned from other projects
`
`and were assigned to solely work on the R400 project. These project
`
`managers/designers, including me, diligently worked on the R400. In particular,
`
`we used the specifications to write emulation code and RTL code for the R400’s
`
`functional blocks. We then tested the R400’s functional blocks.
`
`39.
`
`Everyone assigned to the R400 project saved their work in a revision-
`
`control system, called Perforce. I understand that Perforce maintains metadata(1.e.,
`
`document logs and folder htstories), This metadata includes mnformation such as
`
`the date each file was revised and the user that made each revision.
`
`40.
`
`| understand that this metadata identifies the following users as the
`
`users that worked on the R400 destyn. These users worked from three of ATI's
`
`offices: (1) Marlboro, Massachusetts, USA; (2) Orlando, Florida, USA; and (3)
`
`Toronto, Ontario, Canada. See Ex. 2053, p. 6. T recall that periodic meetings
`
`occurred to coordinate efforts between the three offices.
`
`-?|-
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`a A
`
`2050, 2051, 2052
`Se fehodrat
`i
`2050, 2051
`:
`
`brianf
`
`=
`
`delifton
`
`2048, 2049, 2050,
`
`=
`
`MODI10440256626
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`ATI Ex. 2103
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`=e
`
`aashkar | aR
`
`oT
`
`2049, 2050, 2052
`
`2048, 2049, 2030,
`2051, 2052, 2107
`
`2030, 2051
`
`2049, 2050, 2052
`
`2050, 2052
`
`ze
`
`2049, 2050, 2052
`
`2050, 2031
`
`2050
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`
`2050, 2032
`
`2050, 2052
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`2050
`
`2048, 2052
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`2050, 2052
`
`2048, 2050, 2031,
`2052
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`
`2049, 2052
`
`pregs
`
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`
`2050
`
`2050, 2052
`
`2048, 2049, 2050
`
`2050, 2052
`
`2048, 2049, 2050,
`2051, 2032
`
`ATI Ex. 2103
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`
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`Address Prefix
`Address Prefix|Exhibits
`
`lchen
`
`2050
`
`llefebwr
`
`Iseiler
`
`markf
`
`marklee
`
`2048, 2050, 2051,
`2052
`
`2050
`
`2048, 2049, 2030,
`2051, 2032
`
`2048, 2030, 2051,
`2052
`
`2049, 2050, 2052
`
`2050
`
`2050, 2051, 2052
`
`2048, 2049, 2050,
`2052
`
`2048,2050,2052.
`
`
`
`moev
`
`2049, 2050
`
`mpersaud
`
`2050
`
`2050
`
`2050,2052
`
`mmantor
`
`2048, 2049, 2050,
`2052
`
`2048, 2049, 2050,
`2052
`
`mpersaud
`
`2050
`
`= 239 ~
`
`AMDI0440250627
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`Address Prefix
`Address Prefix|Exhibits
`
`_
`
`scamlin[eae
`
`semara
`
`2050
`
`
`
`2050
`
`=sae
`pale fata 2051, 2052 a|2050, 2051
`2049,2050,2052
`
`pmitchel
`
`2049, 2050, 2051,
`2052, 2107
`
`2050
`
`2050, 2051
`
`rbeaudin
`
`2048, 2050, 2051,
`2052
`
`2050, 2052
`
`tien
`
`2049, 2050, 2052
`
`tmartinape
`
`tshah
`
`vbhatia
`
`2050
`
`2048, 2050
`
`| 2049, 2050, 2052
`
`2052
`
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`
`2050
`
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`
`2050, 2051
`
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`
`2048, 2049, 2050,
`2051, 2052
`
`——
`
`yelang
`
`yvalcour
`
`2048, 2049, 2050,
`2052
`
`aches
`
`AMDI0440255628
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`41.
`
`In Part V, I analyze thts metadata. Myanalysis shows that at least one
`
`person on the R400 project team worked on the R400 design every non-holiday
`
`business day from August 24, 2001 (when we conceived ofthe invention) until
`
`September 29, 2003 (the effective filing date of the °053 patent). See infra Part V.
`
`42.
`
`This metadata is not exhaustive of all sequencer/shader-pipefiles that
`
`were edited during this timeframe. But this metadata shows work that was
`
`necessaryfor implementing the R400 design. Specifically, this metadata shows the
`
`design, development, and testing of the R400 sequencer and graphics blocks. Sez
`
`Exs. 2048, 2049. This metadata also shows work on the design and development of
`
`the R400 generally. See Exs. 2050, 2051, 2052, 2107. The design and development
`
`of the R400 was necessary to make progress on the sequencer block and the shader
`
`pipe block: we could not work on or test the sequencer block or the shader pipe
`
`block in tsolatton.
`
`43.
`
`This analysis is also consistent with my memoryof the work that we
`
`did on the R400. For me and many of the other project managers/designers, the
`
`R400 was the only project that most of us were assigned to—it was our full-time
`
`responsibility. That means, any time that we did work for AT] betweenlate 2001
`
`and the end of 2003, that work would have been on the R400.
`
`-245-
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`IV.
`
`TESTING SHOWED THAT THE RTL IMPLEMENTATION
`WORKED FOR ITS ENTENDED PURPOSE
`
`44, Weran many tests on the R400 durmg its development. Onetest in
`
`particular, the first triangle, showed that a snapshot of the emulation code and the
`
`RTL code worked for its intended purpose—t.e., performing conventional graphics
`
`processing using a unified shader.
`
`45.
`
`For the R400 project, block-level specifications, block-level diagrams,
`
`and interface descriptions provided overarching development concepts. Project
`
`managers/designers on the R400 team used these documents to develop C++ code
`
`(emulation code} and RTL code for the various blocks of the R400. This code was
`
`tested extensively during the development process. Tests could be run on both the
`
`emulation code and the RTL code, and these tests could be run on individual
`
`blocks or the entire graphics core.
`
`46.
`
`Circuit designers extensively use circuit simulation to test the GPU
`
`design. After the design has passed extensive testing, the chip design can be
`
`cleared for fabrication. Before sending out the design for fabrication, the RTL code
`
`is converted to a tape-out file, and that tape-outfile is sent to a fabrication facility
`
`for fabrication.
`
`47.
`
`A product such as the R400 must pass hundreds oftests before it is
`
`taped out. Many tests were directed to specific commercial specifications. Other
`
`-76-
`
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`
`tests were more generic, such as tests for validation and proofof concept. One
`
`generic test was the first tnangle.
`
`48.
`
`The first tnangle tested whether the RTL implementation of the GPU
`
`could process a Gouraud shaded tnangle. At this stage of development, this test
`
`involved manydifferent blocks—including the sequencer, the shader pipe, the
`
`shader export, the texture cache, and the texture pipe blocks.
`
`49.
`
`| recall the first triangle test being successful approximately mid-way
`
`through the R400 project. Consistent with my memory, the PowerPointslide
`
`reproduced below showsthatthe first triangle was reported during a meeting on
`
`August 30, 2002.
`
`ema meaty)
`
`aT
`
`AMOD10440256631
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`Ex, 2066, p. 2. According to this presentation, the first tnangle was completed on
`
`July 1, 2002. id., p. 6.
`
`50.
`
`For asuccessful first triangle, the sequencer block and the shader pipe
`
`block must work together to process both vertex commands and pixel commands.
`
`This 1s shown, for example, in the RTL code that arbitrates between vertices and
`
`pixels. An example of this arbitration as implemented in the RTL code is
`
`reproduced below.
`
`19
`
`20
`
`21
`
`22
`
`23
`
`case (tta_currentstate)
`
`TTAO:
`
`begin
`
`‘= ack ts connected to TB State Mem read enable, so have to
`
`‘) watt until the correct phase to ack
`
`aR a
`
`AMD104402560632
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`if( state_read_phase = arbtype_strap }
`
`if( vtx_winner_vid_q)
`
`! simply give verts the priority
`
`begin
`
`wix_winner_ack = HI;
`
`tta_next_state = TTAI;
`
`end
`
`else if( pix_winner_vid_q)
`
`begin
`
`pix_winner_ack = HI;
`
`tta_nextstate = TTA2:
`
`end
`
`2
`
`3 4
`
`5
`
`6
`
`7
`
`&
`
`o
`
`10
`
`11
`
`12
`
`13
`
`14
`
`Ex, 2074, 20:19-21:14,
`
`31.
`
`In this example code, the arbitration is implemented as a simple “if-
`
`else” statement in which vertices have prionty. According to this “if-else”
`
`statement, “if” a vertex is ready for execution, the sequencer selects the vertex;
`
`“else” (1.¢., otherwise) the sequencer selects the pixel. That is it. The first triangle
`
`touched both paths because the vertex processing worked for the “if” path and the
`
`pixel processing worked for the “else” path. Other levels of arbitration in the RTL
`
`- 79 -
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`
`code worked like this example, and these other levels of arbitration would have
`
`been touched by thefirst triangle. So, following thefirst triangle, we knewthe
`
`RTL code worked.
`
`52.
`
`Passing thefirst triangle test did not signal the end of the R400
`
`project; the R400 still had to pass manyother tests to be commerctalizable. After
`
`processing a first triangle, however, we knewthat we had an implementation of the
`
`R400 in RTL code that worked for its intended purpose—1.e., performing graphics
`
`processing using a unified shader.
`
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