Virtual ogic 2.7
`
`Software U ser’s Guide
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`
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`ai ¥}
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`Technical Publications
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`ATI Ex. 2076
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`Important Notice
`
`This documentts for informational and instructional purposes. IKOS Svstems. Inc. reserves the nght
`to make changes in the specifications and other information contained in this publication without
`prior notice, and the reader should. in all cases, consult IKOS Systems, Inc. to determine whether
`any changes have been made.
`
`The terms and conditions governing the sale and licensing of IKOS Svstems, Inc. products are set
`forth in the written contracts between IKOS Systems, Inc. and its customers. No representation or
`other affirmation of fact contained in this publication shall be deemed to be a warrant or give tise to
`anvliability to IKOS Systems. Inc. whatsoever.
`
`IKOS Systems, Inc. MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS
`MATERIAL, INCLUDING, BUT NOT LIMITED TO. THE IMPLIED WARRANTIES OF
`MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
`
`IKOS Svsicms, Inc. SHALL NOT BE LIABLE FOR ERRORS CONTAINED HEREIN OR FROM
`INCIDENTAL. INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER
`(INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO
`THIS PUBLICATION OR THE INFORMATION CONTAINEDIN IT. EVEN IF IKOS Svstcms,
`Inc. HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
`
`This document contains proprictary information. In addition, the software programs and hardware
`described in this document are confidential and proprictary products of IKOS Svstems. Inc. and its
`licensors. NO PART OF THIS DOCUMENT MAY BE REPRODUCED, STORED IN A
`RETRIEVAL SYSTEM OR TRANSMITTED IN ANY FORM OR BY ANY MEANS.
`ELECTRONIC. MECHANICAL. PHOTOCOPY. RECORDING OR OTHERWISE WITHOUT
`THE PRIOR WRITTEN CONSENT OF IKOSSvstems, Inc. Each licensed uscr is allowed to print
`up to 10 copies of this material for intracompanyuse only without infringing this copyright. Please
`contact [KOS Systems, Inc.. for permission to print additional copics.
`
`IKOS® is a registered trademark of IKOS Systems. Inc.
`VHDL Accelerator”is registered uademark of IKOS Systems. Inc.
`Vovager™ is registered trademark of IKOS Systems. Inc.
`SimLink'™ is a trademark of IKOS Systems.Inc,
`Gemini™ is a trademark of IKOS Systems. Inc.SimMatrix™ is a registered trademark of Precedence.Inc.
`Verilog-XL™is a registered trademark of Cadence Design Systems. Inc.
`Sun”is a registered trademark of Sun Microsystems.
`
`ALother brands or products are trademarks of their respective companics and should be treated as such.
`
`Copyright “1999 by IKOS Systems. Inc.
`
`All rights reserved.
`
`Written in the U.S. A.
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`
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`Table of Contents
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`Manuals [.
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`Index
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`i
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`i
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`Figures
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`[
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`ables
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`|
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`Back
`
`Table of Contents 2... ee ee ee ee he iti
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`List of Figures 2.0. 0 ee ee ee ee we we we ee XK
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`Listof Tables... 2... ee et te ee we ee te ee ts XXili
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`Introduction . 2.0. ee ee eee ee ee BS
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`Overview.
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`2
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`02 28
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`VirtuaLogic’s Technology Advantages
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`2
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`2 7. ee 88
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`VirtuaLogic Emulation System Components. 2...) we 28
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`Hardware.)ee 26
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`Logic Analyzer.
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`2.
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`2
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`2 2 ln Lo
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`Loe ee ee BF
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`Target Interfaces 2. 2 lt Lo. Coe ee BB
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`Target System2 88
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`Software
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`2
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`00) 2B
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`VirtuaLogic Compiler 2. ee ee BB
`Timing Resyathesis
`2 7 ee 2
`Interconnect Resynthesis
`2
`6 wwe BY
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`Backend Place and Rous Manager.) 2. 2 ee BD
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`0 8. ee
`2
`2
`Virtual Probe Analysis Tools
`Diagnostics2 BG
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`VirtuaLogic User's Guide
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`Manuals | index |<n|=>|[ i Figures _f ables | | Back
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`Software Flow.
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`2
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`2
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`0 2we BO
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`Using the Graphical User Interface (GUD... 2... -..---..-.---- 33
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`Environment Setup.
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`2 2.) 8B
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`Path Setup.
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`2
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`2 2 ee BB
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`Starting the Graphical Compiler Interface. 2 ee
`Problems
`2
`0
`2 21 ee BA
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`Invoking the VirtuaLogic Software.) A
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`Configurations = 2)| BB
`Configmame 6. ee BB
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`Starting evl on a Pre-existing Configuration
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`2 2... ee
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`2 2... 8
`2
`©
`Building a Sinele-ASIC Configuration,
`Software Executables
`2
`2
`2
`22 8B
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`Navigating the GVL Interface.
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`2
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`2 2)2 BF
`
`evl Window Lavout.
`Screen Elements 2.
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`2 7) BF
`2
`2 2)... Lo.
`tee ee BF
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`Dragand Drop 2 2.) ee BB
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`Multiple Selection,
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`©
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`2 2) BY
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`Scrolling Text Windows
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`2
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`0
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`22 88
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`Director, and File Browsers. 2 ee BY
`“P puttons, AG
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`Optional Test Fields.
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`2
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`2 2. ee AD
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`Common Parts ofthe Interface.
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`2
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`20.
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`Note Tab Bar.
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`2 ww ee AG
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`Multi-ASIC Button 2) 2) AD
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`Main Button Bar... . 2... ee A
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`2 2, Lo Coe A
`2
`2
`2
`VuirmalBrowser.
`Patho 2
`2 2 Lo.
`Lo. ee
`Modules
`2 2.
`2 2) 4B
`Nels. ee AB
`Terminals2) aD
`Find.0
`Search 2we FB
`Show Path 6. ee ee AB
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`iv
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`Additional Features
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`Regular Expression Syntax
`Ambiguits
`ee
`Reguiar Expression Example .
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`Clipboard .
`Clear
`Insert File .
`Write File .
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`47
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`48
`49
`49
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`30
`30
`50
`50
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`50
`Append File .
`Sl
`Dismiss
`Reload 2.we. SI
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`Undo.
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`2
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`02 ee SI
`
`Quit2 ee ee SM
`Errors Window .
`Sl
`OK
`.
`52
`
`Visii(next)
`Help .
`ShowLog .
`Save Errors
`
`File Browser .
`Path .
`Directorics
`Files .
`OK
`Filter
`Cancel.
`
`.
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`Optional Text Ficlds .
`
`52
`33
`53
`53
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`33
`54
`34
`34
`a4
`44
`34
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`54
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`Design Import... 0.2... ee ee ee ee ee ee ee
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`Overview.
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`2
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`00 BB
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`Netlist Import.
`Nethsts 0
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`2
`2
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`2 0) SB
`22 8G
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`6 2) ee ee BF
`Entering Pathnames
`2 2)... ee SF
`Nellists Requirements
`Notlist Defines =
`2 2) 2 Lo.
`Lo. Soe BR
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`2
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`Input Netlist Typo.
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`22 BB
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`Root Module.
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`2 2. 2 eG
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`Technology Mapping. 2...) 80
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`Technolopy 2. 0.) ee GT
`Bonded Out Cores.2 ee GM
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`Instance Removal Example
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`2 2. 2. ee 2B
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`Technology Files 20 (63
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`Memory Specification,
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`© 2.)ee BA
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`2. 2) 2) 65
`Memory Parameters.
`Memory Namo2 0G
`Coments File
`2 2. ee 06
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`2 2... 0G
`2
`Instance-Specific Contents File
`Write EnableScnse
`2 1 ee GF
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`Memories 20 6B
`ShowMemories oo.
`oo. BB
`
`Coe eee ee 6B
`Loe
`Defining Memories with Netlist Prototypes...
`Defining Memories without Netlist Prototypes
`6 we OY
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`Memon VOTerminals. 2.0 BY
`Ports.2 FD
`Voclors ee TM
`Sellar
`2
`22 ee ee TT
`
`Output Enabic Senseee
`
`AddMemon.
`
`2
`
`Delete Memory.
`
`0
`
`2
`
`0 2 ee FB
`
`0 ee FR
`
`2ee FD
`2
`Import Memory File.
`Clock Files
`2 0)2 FR
`
`2 2... ee FB
`2.
`Memory Files
`Trivecr Files2 ee FB
`Probe Files2 FB
`
`Check Memory. 2 7) oo.
`
`oo. Co FR
`
`Memory Example.2
`Adding thc Memory. 2. ee FA
`Adding the Port Information ©.)A
`Adding the Memory Parameters Information.
`2
`7 2.)
`
`Timing Specification © 2) ee 8
`Clock Domain 2 2). FP
`
`Building the Waveforms 2 FR
`Multiple Domains...) IG
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`DataSignals2) BO
`Feedthrough Signals 2.
`2. 2... ee. BI
`Feedthroughs and Verify Simulation 2
`2 2) 2) BB
`Rising2 8B
`Rising Edge Synchronous Inputs ee 8S
`Falling Edge Synchronous Inpuis
`5
`2 ww 8G
`Both Edge Synchronous Inpus 2.ee
`Rising Edge Synchronous Outputs© ee eB
`Falling Edge Synchronous Oulpuls. ee. 8
`Both Edge Synchronous Outputs
`6
`| ee 8D
`
`Lo. Se BT
`2 2 Lo.
`©
`Asvuchronous Inputs.
`Asynchronous Preset and Reset Sigmals we ee eG
`Asynchronous Dala Signals 2.)
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`Unconnected Inputs and Outputs.|
`Outpul Clocks enihe Target Svsiem 2. wwwe 98
`Inpuls Derived from Outputs 2 ee 8
`Bidircelional Signals ©2 OS
`
`2 0) 8S
`Design /O Terminals
`Insimictions2 OS
`
`Add Domain.
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`. 2... ae Co ee 9G
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`AddClock.
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`2
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`2 00 98
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`Add Clocked DataSignal.
`
`2 2.2 98
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`2 0) we ee 88
`Add Asynchronous DataSignal
`Import Timing2) 88
`Clock Files
`2
`0
`2
`2
`2 2 ee BF
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`2 2.ee OF
`Memory Files
`Trigger Files1
`Probe Files
`2
`2 7.) ee OF
`
`Verification 2... ee ee ee ee 99
`
`Overview28
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`5we), FOO
`Netlist Qualification Errors
`RunDROee LO
`
`Change the Design andRun DRO 2. ee LOT
`
`1we OB
`Error Messages.
`Source Code of Error/Warning Message . | Loe
`foe ee eee OD
`Net Waming Message Assessment. 2). eee eee LO
`
`Filter
`
`22 1B
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`May 11, 1999
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`. LOB
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`. LO9
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`. LO9
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`. L1G
`Jit
`. 112
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`J 112
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`Sort By .
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`Show Fields .
`
`Suppressions.
`
`Gen Virtualized Model
`
`Virtualized Simulation Model
`
`VSMLimitations .
`
`Preserving Design hicrarchy .
`
`Gencrating a VSM
`
`Sinulatinga VSM... 2...
`Step |: Simulate the Input Neilisi
`.
`Step 2: Prepare the Testbench
`Sicp 3: Resimulate the Modified Testhench.
`Step 4: Simulate the VSM_-
`
`Resolving Simulation Scenarios
`
`Initializing the design
`Timescale Issues
`
`Input Timing Issues .
`
`Clock Ordenng and Period Issues.
`Vector Capture.
`Example
`
`VSMSummary.
`
`Probing. 2.0. ee ee et ee es
`
`Overview .
`
`Probe Windows
`
`Probe Group Name .
`
`Probe Nets.
`
`Probe Groups
`Check
`
`Add Group.
`
`Delete Group.
`
`Write Virsim Configuration .
`
`Import Probes
`Clock Files
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`vill
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`2 6 ee ee ETB
`Memory Files
`TriggerFiles. ee ee LB
`Probe Files
`2
`2
`0we LY
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`100% Visibility2 HS
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`100%Visibility Cable 22 120
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`100%Visibility Benefits 2.
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`2
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`22 LO
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`100% Visibility Costs
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`2 2) ee 120
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`2 0. ee LT
`©
`100% Visibility Restrictions.
`Conditional Capture © oo.
`oo. Se LD
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`Number of LA Probe Cards2...
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`Compiler... . 2... ee ee 123
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`Intreduction.. 2). 12
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`Flow Chatt
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`2
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`2
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`0
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`27 12
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`Hardware Configuration,
`Emulation Platform =.
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`0 0. ee LE
`2
`2 2)2. 128
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`Maximum NumbecrofBoards
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`. 20...) ee. 128
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`Enable usc in Multi-ASIC.
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`2 2 ee. L2G
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`Compilation Files 2. 0... ee NB?
`Partition File.
`2
`0 0. 127
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`Placement File.
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`2 2. ee 2
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`Terminal Constraint File
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`2 2.) 0. 2?
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`06 ee e128
`Compiler Options
`Compiler Options Listed Alphabetically ©
`0
`2
`2 2 ee LB
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`Compiler Options Listed by Category.) ws ee A
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`2 2. «BB
`Capacity Control Areuments
`Mm.we ee LBB
`-Mmfanoul
`2
`2
`2ee ee. BA
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`2 0. eB
`2
`Partition Contro] Parameters.
`(Ue 2... Lo. Coe ee BT
`CUE, ee 15S
`PE ee, 188
`PUI.2 IBF
`
`2 2) 2.) ee ee BB
`Database File Suppression Switches
`swritevpd 2 2 ee BB
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`TIOVIC 2ke ee ee ew ey , EBB
`snosmD ee ee 188
`odbc BY
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`2 ee 1D
`2
`2
`Analysis/Transformation Control.
`OSG 22 ee. «BD
`-NoSvncQS 2we ee. TAD
`NFfi ge. 140
`“NAM ee LAT
`Net2 Lo. See eee A
`“TNH oo.
`oo. Se LS
`BO. 146
`Sr LAG
`-NOSfi.
`22 Lo
`toe ee ee. LAF
`NOXOT 2. oo.
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`2 2 ee 152
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`-TerscProbe2 ee ee LEY
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`-Dump 2.we ee LSD
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`©2).
`Arcuments Not Sct Manualit
`c-Libwe. 162
`DB. ee. LER
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`“NPB ee ee, 168
`Roth2 ee 168
`CIR 168
`Mem 2
`0 2. ee. 163
`-ProboIn
`2| ee. 164
`-ProbeWindows
`2 2) 2. ee. LF
`-ProbeCard2 ee LOAF
`-ProbeCore
`2
`8 | ee. 14
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`-ProbeMap oo.
`-ProbeDB ee Lo. Soe ee. LOR
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`Pod. 166
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`slarech ee. 166
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`clypdwe ee. 109
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`Auto-Start FPGA Compile.
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`2
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`2
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`2
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`0 2)2 LT
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`Froomevl 2.2 LGR
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`Fromthe vle Scnpt
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`Compiler Log .
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`Run Compiler
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`.
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`Incremental Probe Compile
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`Show Log.
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`Improved Emulation Performance
`
`No-Flows for Modeling .
`
`No-Flows to Compile a Design.
`
`2 0. 2 s.
`No-flows to huprove Emulation Speed
`Special No-flowSemantics for Bidirectional Top-Level I/Gs
`Visibility for Bidirectional IOs with No-Flows
`
`Using No-Flows
`No-Fliows on Buses
`
`Lone
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`No-Flows in Combinational Loops .
`No-Flowat Output of Latches
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`Net Tie-Offs .
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`Designs with Multiple Asynchronous Clocks.
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`Script Driven Activities .
`
`Script Driven Generation of Virtualized Model
`
`Script Driven Design Compilation
`
`Script Driven Place and Route -
`vie Commands .
`
`verifs
`compile
`pprma .
`all
`
`pprelean
`browse .
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`vprobe .
`rirsim .
`
`rvirsimlogic
`lar
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`VRC .
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`vic. browse_constants .
`Incerreet Net Value in the Circuit
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`179
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`. 180
`. 180
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`Design Removal During Sccond Dead Logic Elimination,
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`2 2... E85
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`© 2. 18
`Running Repeat Configurations
`Creating a New Configuration Database ©
`2 2.) ee. LRG
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`Suggestions for Repeat Configurations. 2.
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`6 6. ee ey LRG
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`Configuration Input Files.
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`2
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`2 2). EB
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`Multi-ASIC Designs... 0. et te et ee ee ee ee oe LBD
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`Overview.
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`20ee ERY
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`Multi-ASIC Setup =0 90
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`ASiC InstanceName...) EG
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`Configuration List2 TT
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`© 2. 2 ee EG
`Configuration Selection.
`Path 2 2. ee TT
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`Filter,2 ee ee IT
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`Directories,
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`2 2 ee EG
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`62 LS
`Configurations ©
`Delete ASICs. 2) GP
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`Pushinto ASIC.
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`2
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`2
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`72 ae Coe ee 192
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`Check ASICS)
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`7 0) ee E92
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`Gather ASICBits. ee LOD
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`Build ASICs2) 192
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`Interrupt.2 ee, 192
`Pause.
`2
`22 ee ee LYD
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`Muilti-ASICs Definition. 2... 2... to Coe ee ee 193
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`Multi-ASIC Flow.
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`2.
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`2
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`0
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`22 ee 193
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`Whento Use the Multi-ASIC Switch 2... . to Coe eee 19S
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`Constraints on IndividualASICS © 0)we
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`ASIC Configuration 2. 0). LDF
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`FPGA Compile... ee ee ee ee 197
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`Overview 20 L9F
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`Machine List... 2... 2 ee 198
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`Remote Machine Resourees. 2 ee LOS
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`AllKnown Hosts.
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`2 0.
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`2 2) 2) ee. BOO
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`Niceness 2.) 201
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`Place & Route Tasks 0 2) 20
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`Place& RouteLog. 2. 2.2 202
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`Run FPGA Place& Route.
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`2 2) ee 2002
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`Reset HostList.2) 208
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`Deleie Place & RouteData..2... 203
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`Interrupt.©.. 203
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`Stopping Place and Route Dunng Compilation =
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`2
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`Pause.2ee 2038
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`Show Log.
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`2
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`22 ee, 204
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`Run FPGA Compilation from the Command Line.
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`. 0. 2... oe
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`Task Management 200, BOF
`viaskk Commands
`. 2.) ee BOF
`add ww ee 204
`rOMOVG ee 205
`newlist
`2
`2 2 ee 208
`MEO ee 2OS
`statusee 208
`exit. 206
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`woe ee ee BOG
`qmit Loe
`help. ee. 208
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` 2OF
`0 2)
`Hung Jobs.
`viask Command. ©.) 2) ee BOF
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`Emulation.
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`. 0...ee 209
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`Overview 20 209
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`6 2 ee 21D
`Emulator and Logic Analyzer Setup.
`EmulatorHost
`. 2... 2). BIG
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`EmulatorBox 2. 2.
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`2 2) ee 21
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`Logic Amalyzer.ee ELT
`LA Probe Cards.
`2 2. 2) ee ATT
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`Virsim Host 2) ee TT
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`2 2 ee BT
`7
`2
`Sample Depth
`Probe Window 2 2). ee 212
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`Emulator Clock.
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`2 2 ee BY?
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`2 0. 2. ee 212
`EmulatorCommands .
`Connect to EmulatorHost.
`2
`2
`0 2) 21D
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`Conncet to Emulator Hardware,
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`2
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`2
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`7 2 218
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`Download Designand Memory
`Emulator VO Pods Enabled 2
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`2 0.we 2S
`2 2) 2 ee BMA
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`UserBitn.
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`2 2. e214
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`Functional Test.
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`2 2.) 2 ee BIS
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`Functional TestPurpose. 2.) ee 2B
`Vectors. ee 218
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`Reload Memory,
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`08 BNF
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`Upload Memory.we ee 2?
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`Poke Memory Value. 2)2 BW?
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`Interrupt.
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`2
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`22 ee aT
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`Logic Analyzer Commands...) 2.) BB
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`Connectto Logic Analyzer
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`2
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`2 2) ee BIB
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`Download Trigger.
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`2
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`2
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`2 | ee 2B
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`Record/Stop oo.
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`oo. Se BID
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`Upload Waveform Data 2.
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`2
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`2 De ee BID
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`7 2 ee 21D
`Logic Anahzer Window 2
`Waveform Traces 2 = oo oo BBO
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`Display Waveform |we 220
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`WirSim Hierarchy 2. 2) 22D
`VirSim Waveform.
`28. 220
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`WirSim Register,
`VirSim Source.
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`0 2 ee 22 T
`2
`2we 22
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`VirSim Logic.
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`©6 ee ee BB
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`EmulatorLog 2
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`2
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`0
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`0 2. 2B?
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`Design Emulation Speed
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`2. 2) 2B
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`Clock Relationships.
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`© 2) 2) 2B?
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`Multiple Domain Designs asa Single Domain.
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`.
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`2 0. 2... 28
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`Design Emulation Speed Example ©. ww. ee 2D
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`Resetting the Emulator Target System.
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`2
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`2 2) 2 ee
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`Amalysis. 6. 06 ce ee ee ee ee ee eee
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`Overview 20 BBP
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`Probe Windows 2) 2B
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`100% Wisibility
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`2
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`22 229
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`100% Visibility Dees Not Support Conditional Capture.
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`2 2.) 2. 28
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`Probe Upload and Display Methadology.
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`2 2... BI
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`Probe Groups
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`2 6.) 282
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`Logic Analysis Trigger. 7) 2B
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`Tngger Definition. ©)2 BBB
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`TnggerFSM Svntax.
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`2 2) ee BB
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`Trigger FSM Commands. 2...) . ee 2B
`tfigeer
`. ) ln Loe
`Coe ee ee BBA
`stale oo.
`oo. Se BBG
`clsestate2 BBP
`
`Entenng Tigger FSM 2 2). BBP
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`Tngacr FSM Dialog Boxes © 2. 2) BBB
`NewSlate.
`2 2 ee 2BB
`New Term | we 28D
`New Else 2
`02 BBD
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`Set Trigger Stale ee. BAD
`Open TrigeerFile 2
`2 2 ee. 2D
`Write Trigger File. 2, PAT
`Show Errors| ee aT
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`Examples 200 ee, BAD
`Example} 0.ee 2A
`Example? 2.
`2we BAD
`Example3
`2 22 ee 2AB
`Exampled
`2
`2
`2 2 ee 248
`Examples 2.
`0 we 2A
`Example6 2).we BAF
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`0.ee ee AAS
`Example 7
`Example S$ 2.
`|we 2S
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`Tripeer FSM Resources
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`2 0) ee BAS
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`Downloading a Logic Analyzer Trigger2. 2
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`Resetting the Emulator Target System 2
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`2
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`0 7) BAB
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`Using the Logic Analyzer with Functional Test.
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`= =. es 2
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`Syntax, Semantics, and Reference Library. .....0..006. 000008. 0251
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`Overview 2
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`00 BST
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`VirtuaLogic Structural Verilog Subset.
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`2
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`2
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`0 2.) BB
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`Venlog Identifiers.
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`2 2. ee 28D
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`2 2 ee BBD
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`Parameters.
`22, BR?
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`Example
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`0 22 233
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`Simple Assignments.
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`2
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`2
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`2 2.) BSS
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`Compiler Directives.
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`2 2) Lo.
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`toe ee BBS
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`Unsupported Verilog Constructs 6) 22
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`Memory Specification.
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`.
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`Textual swntax .
`MemoryAttributes
`Terminal Bindings
`Semantics .
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`Timing Specification .
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`Svntax
`Semantics .
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`Probe List Format.
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`Textual Syntax.
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`255
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`_ 255
`245
`255
`256
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`_ 257
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`257
`258
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`259
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`VirtuaLovic Reference Library... 2... 2. 7) . 26O
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`Trouble Shooting Guide. 2...ce 28
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`WhatToDo.
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`20 ee 263
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`Software Installation
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`2 2.
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`22 268
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`Design Import and Verification. ©.
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`2.
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`2 2.) 2A
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`2 ee BOD
`2 0.
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`Additional lmport and Verification Problems .
`Timescale Issues ee. BBY
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`Input TimingIssues 2...ee BID
`Clock Ordering Issues www ee AID
`Clock Period Issues 2) 2) Be
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`Design Compilation 2.
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`0
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`22 BPD
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`Partitioning= BFA
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`22 BFS
`Configuration Download 2 2.
`Emulation.
`©
`2 2. 2 ee BFE
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`Debug Activity.
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`2
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`0
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`2ee BFE
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`Virtual Swapping.
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`2 2... FF
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`Diagnosing the Problem...) .we BFF
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`Command Syntax2. TT
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`virtual-swap Command
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`2
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`0
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`2| FT
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`2 2) ee 2TB
`TypesofSwap.
`Column Swap 2...ee LIB
`Row Swap 2) en Loe
`woe ee ee ee BIB
`Board Swap 2. 2.) ) en Loe
`Coe ee ee ID
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`Noncompiling FPGAs.
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`.
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`2. 2...) ) ee BIG
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`Correcting Noncompiling FPGAs with -FPiSwitch 6 7.) De, aD
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`Correcting, Fitting Problems with -CUi Switch.
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`.
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`.
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`Lo. Doe ee . 2BO
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`PC Farm . 0... ce ee ee ee es 281
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`Overview 22 ee. 28
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`Hardware Requirements.
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`2. 2. 2. 2 ee 28
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`Software Requirements.
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`5
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`2
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`2 2.) BRT
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`PC Setup.
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`22 ee. BBB
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`Software Installation 2.
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`2
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`0
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`2
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`22 BR?
`
`2 2. 2B
`Obtaininga RSH Dacmon.
`RSHDaemon 2... ee, 2B
`Testthe RSH Daemon 2.) 1 ee BBB
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`OblainingaRSHDacmon. 2... ee, 284
`VMWY/Xilinx Software.2 BBA
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`©2 BBS
`VNC (optional).
`Obtaining VNC Software 2. 0) ee BRS
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`01 BBS
`Farm Usage 2
`From the Command Line. 2...) BBS
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`FromtheGUE...) 286
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`Maintenance Scripts
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`2...
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`0 2.). 28G
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`Avatar... 0 ee ee ee ee 287
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`Overview.
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`2
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`00 BRI
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`Using Avatar,2, 287
`In-Circuit Emulation 2
`6 2 ee es 2BF
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`Diagnosis and Tesi Mode
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`2
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`2 2 ee ee BBB
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`Configuration Directory Setup. BBB
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`Invoking gavt2 BRD
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`Copying Old Files. 2. 2)ee BBY
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`AvatarForm.
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`. 2...2 BEY
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`Using Avatar
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`2 0) BOD
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`Glossary. 2...ee ee ee 291
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`Index 2... ce ee ee ee ee te ee ee LOS
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`Figures
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`[
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`“Ables
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`Back
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`|<a{>|
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`List of Figures
`
`Manuals [.
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`Index
`
`[ contents |
`
`.
`
`[
`
`ables
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`|
`
`Back
`
`Figure |
`Figure 2
`Figure 3
`Figure 4
`Figure 5
`Figure 6
`Figure 7
`Figure 8
`Figure 9
`Figure 10
`Figure 11]
`Figure 12
`Figure 13
`Figure 14
`Figure 15
`Figure 16
`Figure 17
`Figure 18
`Figure 19
`Figure 20
`Figure 21
`Figure 22
`Figure 23
`Figure 24
`Figure 25
`Figure 26
`Figure 27
`Figure 28
`Figure 29
`
`System Components...2... 27
`VirtuaLogic Software Process Flow... 0.000. 0. ee eee 31
`Sereen Elements 2...2 38
`VirtualBrowser Window...0 ee 42
`Find Window.
`02 45
`Clipboard Window. 2. 2 0 ee 58
`Errors Window. 1) ee eB
`File Browser0.ee
`NetlistImport. 20 5G
`TechnologyMapping... 60
`Instance Removal...2. 62
`Memory Specification...0 ee 65
`RegFile Schematic.2. 74
`Timing Specification.© 76
`Unsupported Circuit when Clkl and Clk2 arein Different Domains... ... BO
`Rising Edge Synchronous Inputs 2... 0.000.000.2000. 200005, 835
`Falling Edge Synchronous Inputs... 2.2... 02 ee 86
`Both Edge Synchronous Inputs... 2.2.00. 02 87
`Rising Edge SynchronousOutputs... 88
`Falling Edge Synchronous Outputs... ee 89
`Both Edges Synchronous Outputs .........2..20.22.20...20.... 90
`Output Clack0 93
`Feedthrough...0. 94
`Verification. ©.2. Loo
`VSMVerification Process Steps... 0. ee 107
`Probing Window. 2...22 114
`Compiler Window.2 124
`Compiler Process Flow Chart...0 125
`No-flows to Break Multicycle Paths... 7 1 _.. 175
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`Figure 30
`Figure 31
`Figure 32
`Figure 33
`Figure 34
`Figure 35
`Figure 36
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`No-Flow Bidirectional /O Net.0. 176
`Multi-ASIC Window... 2... ee _.
`. 196
`FPGA Compile Window... BC _.
`. 198
`Emulation Window. 2.20 216
`One Clock with Even Duty Cycle 2022 _.
`. 224
`Two Clecks with Even Duty Cycle. || BC _. 225
`Analysis Window0.0 228
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`List of Tables
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`Manuals
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`§
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`index
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`Contents
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`Figures
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`[
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`|
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`Back
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`Table |
`Table 2
`Table 3
`Table 4
`Table 5
`Table 6
`Table 7
`Table 8
`Table 9
`Table 10
`Table 11
`
`VirtuaLogic Commands»... 36
`Compiler Options List Alphabetically 9.0. 128
`Compiler Options that can be Used Together 2.2 13]
`Configuration Input Files... 0 0 ee 187
`Unsupported Verilog Constructs. 62.254
`Compiler Options for Behavioral Code.2)254
`Keywords and Terminal-Binding Formats... .....0........0.,256
`Timing Specification Elements 2... .0...002000-.......0..258
`VirtuaLogic Reference Library
`. 0... ....202002.202200..0....260
`Avatar Configuration Directory 2.0.0288
`Avatar Form Elements... 0)De 289
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`[
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`
`
`Introduction
`
`{| <=] >|
`Back
`{
`Topics
`_| bis |
`Figures
`Contents
`Index
`Manuais
`
`
`Overview
`
`Emulation is a technology that creates a prototype of an Application Specific Integrated
`Circuit (ASIC) design in hardware. The prototype is generally built through partitioning the
`design into smaller pieces and then mapping or compiling the design onto a large array of
`Field Programmabie Gate Arrays (FPGAs) or custom chips. The prototype is a complete
`functional implementation of the design including all digital functions and memories.
`
`The ASICs can be tested under real world operating conditions rather than using an
`approximation of their operating environment. In-system emulators get their stimuli directly
`from the target system, unlike simulations, which require test programs, testbenches, and
`stimulus files. The advantages of emulation include full system integration and debugging
`before the ASIC design is finished and the device fabricated. This 15 especiallytrue of low
`level software, such as diagnostics and device drivers, which often require actual target
`systems for complete testing. The user can design and verify the ASICs, system hardware,
`and system software at the same time.
`
`VirtuaLogic’s Technology Advantages
`
`The VirtuaLogic Emulation System uses a unique patented technology called Virtual Wires.
`Virtual Wires provides significant improvements over previous technologies because it
`makes emulation less expensive and easier to use.
`
`Virtual Wires does not just map a design to the hardware, it actually compiles it for the
`specific hardware resources. ASIC designs do not map directly to FPGA and emulation
`custom chip architectures. Traditional emulation products execute a trivial translation
`process and mapthe design to the hardware, then attempt to tune the timing implementation
`
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`by inserting delays into the data path to compensate for hold time violations. Virtual Wires
`uses advanced synthesis technology to create a functionally identical design thatis targeted
`for the specific hardware of the VirtuaLogic emulator.
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`By compiling the design into a single high speed clock and pipelining signals through the
`machine using this clock, there is only one important delay, which ts the worst case path
`through a Xilinx chip. Ifthe VCLK period is longer than this path, then no setup and hold
`issues occur. As a result, the operating frequency of the design is immediately known at the
`completion of the configuration process.
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`Theuse of Virtual Wires provides time domain multiplexing of multiple signals onto a
`single FPGA pin or backplane pin. This eliminates the constraint of interconnect,greatly
`simplifying the hardware and software and decreasing the cost of the hardware.
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`Without the need for interconnect chips, the resulting hardware is more compact and fewer
`ICs translates to higher reliability. In addition to eliminating the interconnect chips, the time
`domain multiplexing is used on the backplane which eliminates the costly connectors and
`backplanes. The implementation does not have the added propagation delay of the
`interconnect chip and board delays, pctentially resulting in faster emulation speeds. By
`eliminating interconnect challenges, Virtual Wires provides increased visibility for
`debugging.
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`VirtuaLogic Emulation System Components
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`The VirmaLogic product consists of a reconfigurable hardware system, debug hardware, and
`interfacing hardware. The hardwareis driven by software tools used to implement and
`debug the ASIC design. The entire system is called the VirtuaLogic Emulation System.
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`Hardware
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`The VirtuaLogic Emulator is the primary hardware component. It is a configurable system
`that consists of a System Board, up to six Array Boards, an interface to a Logic Analyzer
`and an interface for the target system. When programmed with the user’s design, the
`VirtuaLogic Emulator becomes the chip prototype.
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`figure / on page 27 shows the major system components and the demonstrates the
`connections between them.
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`data and clock cables »
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`User’s target system
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`Sun Sparc Workstation ‘
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` *
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`IKOSVirtuaLogic Emulator
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`Figure | System Components
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`The emulator runs at a reduced speed relative to the final silicon due to the partitioning of
`the design across manychips. The resulting emulation frequency generally ranges between
`500 KHz and 2 MHz. The emulation frequency is dependent on the number oflogic levels in
`the design, the partitioning and implementation, and the size of the design. As a rule, most
`emulated designs run about 50 times slower thanthe final silicon.
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`Logic Analyzer
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`In order to debug the design while it is running in-circuit, an Hewlett Packard Logic
`Analyzeris used to trigger and capture data. The full event and triggering capability of the
`Logic Analyzer is supported. The Logic Analyzer must be connected on the Ethernet
`iM
`network with the Spare’**workstation and be assigned an unique IP address.
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`VirtuaLogic User's Guide
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`May 11, 1999
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`The Logic Analyzer is connected to each Array Board through the System Board. Each
`Array Board has the capability to multiplex up to 5000 signals to the System Baard,
`allowing a six Array Board configuration to have up to 30,000 signals available for
`triggenng.
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`Target Interfaces
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`The 512 I/O from each Array Module are connected through a data cable to the target. The
`data cables can connect directly to the target system, or package specific target interface
`adaptors are available for many common package types. The interface can be programmed
`to be 3.3V¥ CMOS, 5V CMOS, TTL, or LVTTL.
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`Target System
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`The target system 1s a custom system designed and built specifically for the application that
`is under emulation, An example is a standard Pentium PC which has been slowed down to
`operate between 500 KHz and 10 MHz. The useofthis PC as a part ofa target system can
`aid in the emulation of PC graphics cards, networking cards, or ather PC interfaces.
`Additional components such as a video frame grabber may also be used as a componentof
`the target system to assist with system slowdown.
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`Software
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`The VirtuaLogic Software consists of the following primary components:
`* VirtuaLogic Compiler
`« Backend Place and Route Manager
`* Virtual Probe Analysis Tools
`* Diagnostics
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`VirtuaLogic Compiler
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`The VirtuaLogic Compiler includes the graphical user interface, the design importer, and the
`resynthesis tools. In order to implement the design using the proprietary Virtual Wires
`technology, the design will be resynthesized to an implementation that is better suited to the
`reprogrammable hardware. This resynthesis provides interconnect and timing resynthesis,
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