AMD1044_00192068
`
`ATI Ex. 2065
`IPR2023-00922
`Page 1 of 57
`
`AMD1044_00192068
`
`ATI Ex. 2065
`IPR2023-00922
`Page 1 of 57
`
`
`
`ATI Ex. 2065
`IPR2023-00922
`Page 1 of 57
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`AMD1044_00192068
`
`ATI Ex. 2065
`IPR2023-00922
`Page 1 of 57
`
`
`
`start of module sc count
`
`-sc.uscperfmonqmnumquadslow,
`.sc.uscperfmonqmcoveredhl6é low,
`.sc.usc_perfmon_hiernum_quads low,
`.sc.usc_perfmon_det_num_quadslow,
`.sc.usc_perfmon_det_maskhOlow,
`.sc.us¢eperfmondetmaskhllow,
`
`4096
`256
`4096
`4096
`0
`0
`
`end of module se count --- 7 rr rr rr ocr rc cnr rr ncn crn rrr nc crcce
`start of module rb count -----~-------7---7-- 5755555555555 555575--
`
`009
`
`.tb3.urbperfmonwrapper.urbperfmon_ rbcntxl?_ busylow,
`1024
`-cbh_3.urkperfimen_wrapper.urb_perimen_num_quads passed_z_ low,
`1
`-rb_3.urbperfmon_wrapper.urb perfmon_num_quads failedz low,
`
`.tb3,urbperfmon wrapper.
`urb perimon num 8x256 depth cache fills exp low,
`-rb_3.urb_perfmon_wrapper.
`urb_perfmon_num_8x256_depth_cache_fills_sep_low,
`»rb_3.urb_perfmon_wrapper.
`urb_perfmon_num_$x256_depth_cache_flushes_low,
`th3.urbperfmonwrapper.
`urbperfmen_num$2256depthcacheflushes sep,
`
`4527
`
`0
`
`testbench.
`testbench.
`testbench.
`testbench.
`testbench.
`testbench.
`
`teatbench.
`testbhench.
`testhench.
`testhench.
`testbench.
`testbench.
`testbench.
`
`meenmemeennena end of module rb count ------------------------------------—----
`
`AMD1044_00192069
`
`ATI Ex. 2065
`IPR2023-00922
`Page 2 of 57
`
`AMD1044_00192069
`
`ATI Ex. 2065
`IPR2023-00922
`Page 2 of 57
`
`
`
`February 12¢, 2003
`
`“R400 Program Review
`— Software
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192070
`
`ATI Ex. 2065
`IPR2023-00922
`Page 3 of 57
`
`AMD1044_00192070
`
`ATI Ex. 2065
`IPR2023-00922
`Page 3 of 57
`
`
`
`Contents
`
`
`
`+ R400 BIOS Development
`— BIOS Progress
`— BIOS Verification Status
`- BIOS Risks and Plan
`« R400 2D Display Driver Development
`- 2D Driver Progress
`- 2D Driver Verification Status
`— 2D Driver Risks and Plan
`« R400 3D Graphics Driver Development
`— 3D Driver Progress
`— 3D Driver Verification Status
`
`— 3D Driver Risks and Plan
`+ Some Screenshots
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192071
`
`ATI Ex. 2065
`IPR2023-00922
`Page 4 of 57
`
`AMD1044_00192071
`
`ATI Ex. 2065
`IPR2023-00922
`Page 4 of 57
`
`
`
`R400 BIOS Progress
`
`+ New-architecture based R300/R400 VGA BIOS are
`implemented
`- BIOS ECR Status
`
`he T AE
`
`Saeninry
`
`|_BuildProcess_|0
`
`era
`
`i.
`
`—BOSKit|2
`|105_|Saebrenten!
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192072
`
`ATI Ex. 2065
`IPR2023-00922
`Page 5 of 57
`
`AMD1044_00192072
`
`ATI Ex. 2065
`IPR2023-00922
`Page 5 of 57
`
`
`
`R400 BIOS Verification
`
`+ Command Decoder Coverage Test
`Cesa hs a ec|irhemG)
`
`
`
`SyaeaaPihisRenew [24[0|0|10]
`Pile LastReview|_20_|
`
`"histone [3a]
`FuniCamattentiskenew|9|8|0|1%|
`TThistener [20oe
`pletealanTa
`—"thisReview|71|«|1|93%]
`
`— VgaDiag from Renaissance GRX Inc.
`
`- The new R300 BIOS passed following VGAtests:
`— Amidiag 5.42 from American MegatrendsInc.
`— DMU - DisplayMate ProfessionalUtilities from Sonera
`Technologies
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192073
`
`ATI Ex. 2065
`IPR2023-00922
`Page 6 of 57
`
`AMD1044_00192073
`
`ATI Ex. 2065
`IPR2023-00922
`Page 6 of 57
`
`
`
`R400 BIOSRisks and Plan
`
`+ Risks
`
`
`
`— Amountof testing on IKOS is huge due to new BIOS
`architecture
`
`— Timing critical implementations can not be verified until
`ASIC back
`= Current VGA code is very old and hard to maintain
`» Plan
`
`— Categorize R400 BIOS tasks with properpriority and verify
`them on IKOS in a proper order
`Using existing ASIC (R300)to verify timing critical
`implementation
`Modularize VGA code as a long term goal (may not R400
`timeframe)
`Also plan to make our new BIOS VBE3.0 compliant
`(nVidia claims): investigation phase
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192074
`
`ATI Ex. 2065
`IPR2023-00922
`Page 7 of 57
`
`AMD1044_00192074
`
`ATI Ex. 2065
`IPR2023-00922
`Page 7 of 57
`
`
`
`R400 2D Display Driver Progress
`
`pa)
`
`(rita
`i
`
`Le
`
`fi
`
`The]
`A
`
`A+
`
`i
`
`a
`I ats
`
`i}
`
`
`
`"tteere)tritattle
`CoeeeeeeeeeReESE
`
`tasReview)SO]MSs|sme||2
`Poteetpeeee
`
`eeseteaeseeaese
`pa] |rowameToea
`fameeeEesaemore
`ews0|nananeTpeeeteEnea
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192075
`
`ATI Ex. 2065
`IPR2023-00922
`Page 8 of 57
`
`AMD1044_00192075
`
`ATI Ex. 2065
`IPR2023-00922
`Page 8 of 57
`
`
`
`R400 2D Driver Verification
`
`+ DDT Test Status
`
`
`
`+ New Packets Verification
`=
`(GrechentFill: WHOL Tést= PASS (detected MS DCT defect and MS just fixed it)
`— Alphadlend: WHOL Test - 384 of 405 (77%) PASS, most of the failures are result of
`incorrectly programming the bottom-tight clipping coordinates (fixing now); the other
`igsue ie the lack of support for SRC/OST surfaces of diffenng sizes — John just
`Updated mictotade and PM4 spec (CLWB3549}
`AAPont feature © working, ut like R300 (AAPon tuned of], sav need te resolve
`rendenng problems with overlapping constant background characters
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192076
`
`ATI Ex. 2065
`IPR2023-00922
`Page 9 of 57
`
`AMD1044_00192076
`
`ATI Ex. 2065
`IPR2023-00922
`Page 9 of 57
`
`
`
`R400 2D Driver Risks and Plan
`
`+ Risks
`
`- R400 DALISXO implementation can only be verified on IKOS
`— Bandwidth sensitive tasks can noi be verified until ASIC back
`
`under way
`
`» Plan
`
`= Using the small (5M) IKOS box to start DAL/GXO testing ASAP (only
`MCBIFIDCMASS! HOcks are required): in addition, we are now working
`on wrapping display emulater for siw testing
`Qump more 2D packets for hAy teams testing: 2D packets capture
`support is available: currently debugging playback issues
`Profiling of 2D driver with various benchmarks for performance tuning:
`initial profiling results for WinBench and WinStone are available now and
`under analysis
`» Other
`
`Coniral Panel; R400 display related control panel features are discussed
`and proposed: 30 related control panel features need to be followed
`More thorough R400 CMMAQS verification strategy is defined and is
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192077
`
`ATI Ex. 2065
`IPR2023-00922
`Page 10 of 57
`
`AMD1044_00192077
`
`ATI Ex. 2065
`IPR2023-00922
`Page 10 of 57
`
`
`
`R400 3D Graphics Driver
`Progress
`
`
`
`+ Compiler
`— Code complete all remaining DX9 and OGL2 opcodes
`support (await test cases from verification team forfully
`testing)
`= Couple remaining render states support is under way
`— Bug fixing has been progressing well and number of open
`bugs has been kept small
`— Number of optimization tasks are started
`+ SSM
`— Updated SSM interface
`— Complete rework SSM fetch for 8/8 internal and 16/16
`extemal allocation
`— Design of “wildcarded shaders” support
`— Debugging andfixing problems from DX SDK Apps, DX
`Test Suites, and Func Tests
`
`AT| Corporate Presentation
`Confidential
`
`AMD1044_00192078
`
`ATI Ex. 2065
`IPR2023-00922
`Page 11 of 57
`
`AMD1044_00192078
`
`ATI Ex. 2065
`IPR2023-00922
`Page 11 of 57
`
`
`
`R400 3D Graphics Driver
`Progress (cont.)
`
`+ D3D
`— Completed MSAA, 3D Texture, Cylindrical Wrap, and
`Texture Filtering
`— Pushed through a simple n-patch triangle through the
`DirectX driver, SSM and the R400 emulator
`
`— Focus on debugging failures of DX SOK Apps, DX Test
`Suite, and Func Tests
`
`
`
`+ OGL
`
`— Render to Texture and
`HP_occlusion_test/NV_occlusion_query are supported
`— Shadow Buffers, 2 Sided Lighting, and Polygon Stippling
`are implemented and debugging with SSM/compiler
`— Focus on debugging failures of Conformance Tests,
`Quickcheck Test Suite, and Glut
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192079
`
`ATI Ex. 2065
`IPR2023-00922
`Page 12 of 57
`
`AMD1044_00192079
`
`ATI Ex. 2065
`IPR2023-00922
`Page 12 of 57
`
`
`
`R400 3D Driver Verification
`
`+ SSM/Compiler
`— Currently SSMClient Test Suite consists of cases with and wio
`equivalent OX instructions. For the former, there are golden
`images available; while verification team is working on a
`mechanism to generate golden images for those wo equivalent
`DX instructions (ie., the UNKNOVWW category).
`
`Petia
`
`
`
`SOL eesee iN
`isin|MS|WS||At it i
`
`itaeee ot
`
`Note: some of ERR/HANG are those |Ls not yet supported by
`interpreter —in olher words, those are not SSM/Compiler issues:
`more detailed analysis is under way
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192080
`
`ATI Ex. 2065
`IPR2023-00922
`Page 13 of 57
`
`AMD1044_00192080
`
`ATI Ex. 2065
`IPR2023-00922
`Page 13 of 57
`
`
`
`« D3D Driver
`— Verification Tests (Dx Test Suite = SimplaDaD + DX8/DE9 Shader)
`We
`‘PASS
`|ERRIMANG/UNMNOWN)
`FAIL
`|
`Pass
`|
`
`
`Testun @stReview|31060 roan|tee|we||Sat|
`ThisReview|M57|Mm|mm|1|Oo|She
`a
`
`A slight “accounbng” issue (not “Enron” ©) wall be feed in the incoming melease
`= DXn SDK Apps
`
`R400 3D Driver Verification
`(cont.)
`
`eee cL Ly
`
`AT Corporate Presentation
`Confidential
`
`AMD1044_00192081
`
`ATI Ex. 2065
`IPR2023-00922
`Page 14 of 57
`
`AMD1044_00192081
`
`ATI Ex. 2065
`IPR2023-00922
`Page 14 of 57
`
`
`
`R400 3D Driver Verification
`(cont.)
`
`+ OGL Driver
`= OpenGL on noe Tests (with 18 ATI ean)
`
`and Veriex Amays
`
`= ATI's Quickcheck
`« Clear 300131 Pass
`+ Frostum PASS
`«
`immedateApi: 7 of 14 PASS
`+ Lighting: G4 of 66 PASS
`+ Bapele: 6.of 19 PASS
`+ Kio: 287 PASS:
`+ Th ring Guackohneck beth vane fur, with ne valid neilite obtgorehd (hee bo vend
`eradh, emulvtat problem, of eytem lockup): ARB WertexcProgam, ATiWetexShader, Fog,
`GlutRtedbook Materats, MiniMuelPass, Primitive: Rarer Tex, SecondColor, Texturing,
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192082
`
`ATI Ex. 2065
`IPR2023-00922
`Page 15 of 57
`
`AMD1044_00192082
`
`ATI Ex. 2065
`IPR2023-00922
`Page 15 of 57
`
`
`
`R400 3D Driver Risks and Plan
`
`« Risks
`= Regression failure and feature completeness of emulator
`— Test Coverage of 3D Component Test Sues
`= Compiler and StaleCache performance work nol yel started
`- Plan
`= Completing development of the following planned test suites for IKOS by
`- Emphasizing more on Siw testing and ooares(3168)the following Siw
`vernfication milestone before sAw IKOS sta
`» SSMeCompiler: pace all S24Clien test suite exoepl for 1D)es
`+ DSO: 100% pass of O47 and O48 shader test sulies and func ists; HS pase of OMS
`shiader best sutes amd fare bests.
`« OpenGL: pass all red book apps and x51 applets; at least BOM pass of WHOL Tesi Set
`Contonnanca Teal Suse, and
`ATTe Quickehnch Toet Suite
`
`ai end of
`
`
`
`= poeicn)ae and performance tuning plan for delivery
`= Complete allikyfeatures (required to verify on IKOS) in 3D drivers by
`
`the end of Ma
`- Others
`- OS5-EMU? has been released and provide significant performance
`improvement
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192083
`
`ATI Ex. 2065
`IPR2023-00922
`Page 16 of 57
`
`AMD1044_00192083
`
`ATI Ex. 2065
`IPR2023-00922
`Page 16 of 57
`
`
`
`2D — Text
`
`phe Te SES amet erga
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192084
`
`ATI Ex. 2065
`IPR2023-00922
`Page 17 of 57
`
`AMD1044_00192084
`
`ATI Ex. 2065
`IPR2023-00922
`Page 17 of 57
`
`
`
`==
`
`2D - Lines
`
`alaes
`—=—
`—_
`s=
`
`=L
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192085
`
`ATI Ex. 2065
`IPR2023-00922
`Page 18 of 57
`
`AMD1044_00192085
`
`ATI Ex. 2065
`IPR2023-00922
`Page 18 of 57
`
`
`
`2D - BITLIT
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192086
`
`ATI Ex. 2065
`IPR2023-00922
`Page 19 of 57
`
`AMD1044_00192086
`
`ATI Ex. 2065
`IPR2023-00922
`Page 19 of 57
`
`
`
`2D — DCT BITLIT
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192087
`
`ATI Ex. 2065
`IPR2023-00922
`Page 20 of 57
`
`AMD1044_00192087
`
`ATI Ex. 2065
`IPR2023-00922
`Page 20 of 57
`
`
`
`3D WinBench 200 — Rust Valley
`
`Versio 7.7
`
`Bt syselele
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192088
`
`ATI Ex. 2065
`IPR2023-00922
`Page 21 of 57
`
`AMD1044_00192088
`
`ATI Ex. 2065
`IPR2023-00922
`Page 21 of 57
`
`
`
` 3D WinBench 2000 - Hangar
`are 0 hahacemers4)elt
`
`Ca
`
`nl
`
`AT] Corporaie Presentation
`Conhdential
`
`AMD1044_00192089
`
`ATI Ex. 2065
`IPR2023-00922
`Page 22 of 57
`
`AMD1044_00192089
`
`ATI Ex. 2065
`IPR2023-00922
`Page 22 of 57
`
`
`
`OpenGL — Quake3: Arena
`
`(x)
`Quake 3: Arena
`TAP LLeeeee ee
`
`1771
`
`Te
`
`AT] Corporaie Presentation
`Confidential
`
`AMD1044_00192090
`
`ATI Ex. 2065
`IPR2023-00922
`Page 23 of 57
`
`AMD1044_00192090
`
`ATI Ex. 2065
`IPR2023-00922
`Page 23 of 57
`
`
`
`February 12¢, 2003
`
`“R400 Program Review
`— Software
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192091
`
`ATI Ex. 2065
`IPR2023-00922
`Page 24 of 57
`
`AMD1044_00192091
`
`ATI Ex. 2065
`IPR2023-00922
`Page 24 of 57
`
`
`
`Contents
`
`
`
`+ R400 BIOS Development
`— BIOS Progress
`— BIOS Verification Status
`- BIOS Risks and Plan
`« R400 2D Display Driver Development
`- 2D Driver Progress
`- 2D Driver Verification Status
`— 2D Driver Risks and Plan
`« R400 3D Graphics Driver Development
`— 3D Driver Progress
`— 3D Driver Verification Status
`
`— 3D Driver Risks and Plan
`+ Some Screenshots
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192092
`
`ATI Ex. 2065
`IPR2023-00922
`Page 25 of 57
`
`AMD1044_00192092
`
`ATI Ex. 2065
`IPR2023-00922
`Page 25 of 57
`
`
`
`R400 BIOS Progress
`
`+ New-architecture based R300/R400 VGA BIOS are
`implemented
`- BIOS ECR Status
`
`he T AE
`
`Saeninry
`
`|_BuildProcess_|0
`
`era
`
`i.
`
`—BOSKit|2
`|105_|Saebrenten!
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192093
`
`ATI Ex. 2065
`IPR2023-00922
`Page 26 of 57
`
`AMD1044_00192093
`
`ATI Ex. 2065
`IPR2023-00922
`Page 26 of 57
`
`
`
`R400 BIOS Verification
`
`+ Command Decoder Coverage Test
`Cesa hs a ec|irhemG)
`
`
`
`SyaeaaPihisRenew [24[0|0|10]
`Pile LastReview|_20_|
`
`"histone [3a]
`FuniCamattentiskenew|9|8|0|1%|
`TThistener [20oe
`pletealanTa
`—"thisReview|71|«|1|93%]
`
`— VgaDiag from Renaissance GRX Inc.
`
`- The new R300 BIOS passed following VGAtests:
`— Amidiag 5.42 from American MegatrendsInc.
`— DMU - DisplayMate ProfessionalUtilities from Sonera
`Technologies
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192094
`
`ATI Ex. 2065
`IPR2023-00922
`Page 27 of 57
`
`AMD1044_00192094
`
`ATI Ex. 2065
`IPR2023-00922
`Page 27 of 57
`
`
`
`R400 BIOSRisks and Plan
`
`+ Risks
`
`(nVidia claims): investigation phase
`
`— Amountof testing on IKOS is huge due to new BIOS
`architecture
`
`— Timing critical implementations can not be verified until
`ASIC back
`= Current VGA code is very old and hard to maintain
`» Plan
`
`— Categorize R400 BIOS tasks with properpriority and verify
`them on IKOS in a proper order
`Using existing ASIC (R300)to verify timing critical
`implementation
`Modularize VGA code as a long term goal (may not R400
`timeframe)
`Also plan to make our new BIOS VBE3.0 compliant
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192095
`
`ATI Ex. 2065
`IPR2023-00922
`Page 28 of 57
`
`AMD1044_00192095
`
`ATI Ex. 2065
`IPR2023-00922
`Page 28 of 57
`
`
`
`R400 2D Display Driver Progress
`
`pa)
`
`(rita
`i
`
`Le
`
`fi
`
`The]
`A
`
`A+
`
`i
`
`a
`I ats
`
`i}
`
`
`
`"tteere)tritattle
`CoeeeeeeeeeReESE
`
`tasReview)SO]MSs|sme||2
`Poteetpeeee
`
`eeseteaeseeaese
`pa] |rowameToea
`fameeeEesaemore
`ews0|nananeTpeeeteEnea
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192096
`
`ATI Ex. 2065
`IPR2023-00922
`Page 29 of 57
`
`AMD1044_00192096
`
`ATI Ex. 2065
`IPR2023-00922
`Page 29 of 57
`
`
`
`R400 2D Driver Verification
`
`+ DDT Test Status
`
`rendenng problems with overlapping constant background characters
`
`+ New Packets Verification
`=
`(GrechentFill: WHOL Tést= PASS (detected MS DCT defect and MS just fixed it)
`— Alphadlend: WHOL Test - 384 of 405 (77%) PASS, most of the failures are result of
`incorrectly programming the bottom-tight clipping coordinates (fixing now); the other
`igsue ie the lack of support for SRC/OST surfaces of diffenng sizes — John just
`Updated mictotade and PM4 spec (CLWB3549}
`AAPont feature © working, ut like R300 (AAPon tuned of], sav need te resolve
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192097
`
`ATI Ex. 2065
`IPR2023-00922
`Page 30 of 57
`
`AMD1044_00192097
`
`ATI Ex. 2065
`IPR2023-00922
`Page 30 of 57
`
`
`
`R400 2D Driver Risks and Plan
`
`+ Risks
`
`- R400 DALISXO implementation can only be verified on IKOS
`— Bandwidth sensitive tasks can noi be verified until ASIC back
`
`under way
`
`» Plan
`
`= Using the small (5M) IKOS box to start DAL/GXO testing ASAP (only
`MCBIFIDCMASS! HOcks are required): in addition, we are now working
`on wrapping display emulater for siw testing
`Qump more 2D packets for hAy teams testing: 2D packets capture
`support is available: currently debugging playback issues
`Profiling of 2D driver with various benchmarks for performance tuning:
`initial profiling results for WinBench and WinStone are available now and
`under analysis
`» Other
`
`Coniral Panel; R400 display related control panel features are discussed
`and proposed: 30 related control panel features need to be followed
`More thorough R400 CMMAQS verification strategy is defined and is
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192098
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`
`
`R400 3D Graphics Driver
`Progress
`
`
`
`+ Compiler
`— Code complete all remaining DX9 and OGL2 opcodes
`support (await test cases from verification team forfully
`testing)
`= Couple remaining render states support is under way
`— Bug fixing has been progressing well and number of open
`bugs has been kept small
`— Number of optimization tasks are started
`+ SSM
`— Updated SSM interface
`— Complete rework SSM fetch for 8/8 internal and 16/16
`extemal allocation
`— Design of “wildcarded shaders” support
`— Debugging andfixing problems found by OGL, MM, and
`D3D
`
`AT| Corporate Presentation
`Confidential
`
`AMD1044_00192099
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`R400 3D Graphics Driver
`Progress (cont.)
`
`
`
`+ D3D
`— Complete 3D texture, cylindrical wrap, and texture filtering
`— Continue implementing MSAA, 2Z/Stencil compression,
`and reviewing texture format support
`— Pushed through a simple n-patch triangle through the
`DirectX driver, SSM and the R400 emulator
`— Focus on debugging failures of DX SDK Apps, DX Test
`Suite, and Func Tests
`* OGL
`
`— Render to Texture and
`HP_occlusion_test/NV_occlusion_query are supported
`— Shadow Buffers, 2 Sided Lighting, and Polygon Stippling
`are implemented and debugging with SSM/compiler
`— Focus on debugging failures of Conformance Tests,
`Quickcheck Test Suite, and Glut
`
`AT| Corporate Presentation
`Confidential
`
`AMD1044_00192100
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`R400 3D Driver Verification
`
`+ SSM/Compiler
`— Currently SSMClient Test Suite consists of cases with and wio
`equivalent OX instructions. For the former, there are golden
`images available; while verification team is working on a
`mechanism to generate golden images for those wo equivalent
`DX instructions (ie., the UNKNOVWW category).
`
`Petia
`
`
`
`SOL eesee iN
`isin|MS|WS||At it i
`
`itaeee ot
`
`Note: some of ERR/HANG are those |Ls not yet supported by
`interpreter —in olher words, those may not be SSM/Compiler
`issues; more detailed analysis is under way
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192101
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`« D3D Driver
`— Verification Tests (Dx Test Suite = SimplaDaD + DX8/DE9 Shader)
`We
`‘PASS
`|ERRIMANG/UNMNOWN)
`FAIL
`|
`Pass
`|
`
`
`Testun @stReview|31060 roan|tee|we||Sat|
`ThisReview|M57|Mm|mm|1|Oo|She
`a
`
`A slight “accounbng” issue (not “Enron” ©) wall be feed in the incoming melease
`= DXn SDK Apps
`
`R400 3D Driver Verification
`(cont.)
`
`eee cL Ly
`
`AT Corporate Presentation
`Confidential
`
`AMD1044_00192102
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`R400 3D Driver Verification
`(cont.)
`
`+ OGL Driver
`= OpenGL on noe Tests (with 18 ATI ean)
`
`and Veriex Amays
`
`= ATI's Quickcheck
`« Clear 300131 Pass
`+ Frostum PASS
`«
`immedateApi: 7 of 14 PASS
`+ Lighting: G4 of 66 PASS
`+ Bapele: 6.of 19 PASS
`+ Kio: 287 PASS:
`+ Th ring Guackohneck beth vane fur, with ne valid neilite obtgorehd (hee bo vend
`eradh, emulvtat problem, of eytem lockup): ARB WertexcProgam, ATiWetexShader, Fog,
`GlutRtedbook Materats, MiniMuelPass, Primitive: Rarer Tex, SecondColor, Texturing,
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192103
`
`ATI Ex. 2065
`IPR2023-00922
`Page 36 of 57
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`
`
`R400 3D Driver Risks and Plan
`
`« Risks
`= Regression failure and feature completeness of emulator
`— Test Coverage of 3D Component Test Sues
`= Compiler and StaleCache performance work nol yel started
`- Plan
`= Completing development of the following planned test suites for IKOS by
`- Emphasizing more on Siw testing and ooares(3168)the following Siw
`vernfication milestone before sAw IKOS sta
`» SSMeCompiler: pace all S24Clien test suite exoepl for 1D)es
`+ DSO: 100% pass of O47 and O48 shader test sulies and func ists; HS pase of OMS
`shiader best sutes amd fare bests.
`« OpenGL: pass all red book apps and x51 applets; at least BOM pass of WHOL Tesi Set
`Contonnanca Teal Suse, and
`ATTe Quickehnch Toet Suite
`
`ai end of
`
`
`
`= poeicn)ae and performance tuning plan for delivery
`= Complete allikyfeatures (required to verify on IKOS) in 3D drivers by
`
`the end of Ma
`- Others
`- OS5-EMU? has been released and provide significant performance
`improvement
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192104
`
`ATI Ex. 2065
`IPR2023-00922
`Page 37 of 57
`
`AMD1044_00192104
`
`ATI Ex. 2065
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`
`
`2D — Text
`
`phe Te SES amet erga
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192105
`
`ATI Ex. 2065
`IPR2023-00922
`Page 38 of 57
`
`AMD1044_00192105
`
`ATI Ex. 2065
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`
`
`
`==
`
`2D - Lines
`
`alaes
`—=—
`—_
`s=
`
`=L
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192106
`
`ATI Ex. 2065
`IPR2023-00922
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`AMD1044_00192106
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`
`
`2D - BITLIT
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192107
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`2D — DCT BITLIT
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192108
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`3D WinBench 200 — Rust Valley
`
`Versio 7.7
`
`Bt syselele
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192109
`
`ATI Ex. 2065
`IPR2023-00922
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`AMD1044_00192109
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`
`
` 3D WinBench 2000 - Hangar
`are 0 hahacemers4)elt
`
`Ca
`
`nl
`
`AT] Corporaie Presentation
`Conhdential
`
`AMD1044_00192110
`
`ATI Ex. 2065
`IPR2023-00922
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`AMD1044_00192110
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`
`
`OpenGL — Quake3: Arena
`
`(x)
`Quake 3: Arena
`TAP LLeeeee ee
`
`1771
`
`Te
`
`AT] Corporaie Presentation
`Confidential
`
`AMD1044_00192111
`
`ATI Ex. 2065
`IPR2023-00922
`Page 44 of 57
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`
`
`
`
`“R400 Program Review
`Physical Design
`
`February 12, 2003
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192112
`
`ATI Ex. 2065
`IPR2023-00922
`Page 45 of 57
`
`AMD1044_00192112
`
`ATI Ex. 2065
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`
`
`Staffing and Assignments
`
`
`
`« Rahul Singh to join R400 PD team from ATI
`TOR
`— Physically in Silicon Valley starting 2/18
`— Already started work while in TOR
`« 1 contractor rolling over from RV350 respin
`efforts
`« Starting with rel_3.0C, all tiles (20 unique) will
`have owners
`- R400 PDfully staffed:
`— 18 PD engineerstotal (not counting CAD):
`— 16 tile owners: 9 full time, 7 contractors. 4 tile
`owners are doubled up
`— 2 full time on top level netlisting and P&R
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192113
`
`ATI Ex. 2065
`IPR2023-00922
`Page 46 of 57
`
`AMD1044_00192113
`
`ATI Ex. 2065
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`
`
`Progressin the last month
`
`: Top level netlisting
`— Did three releases based off netlist 3.0
`— Tile netlist quality much improved fram rel_3.0A to
`rel_3.0C :
`- Tile power grid
`» Congestion based pin/ram assignments
`: Repeaters inserted
`+ Tile constraints pushed down from top level constraints
`: Timing budgets used to generate tile io constrainis
`» Found and fixed top level netlist bug
`— Top level netlist now of good enough quality to start top
`level P&R trials
`
`
`
`— Top leveltile refinement
`: KS tile
`- 2 RB tiles
`- 2 MC tiles
`
`: Misc grouping (Sl tile)
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192114
`
`ATI Ex. 2065
`IPR2023-00922
`Page 47 of 57
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`AMD1044_00192114
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`
`
`Progressin the last month (cont)
`
`insertion workaround): BIF, CP, SC
`
`- Tile P&R progress
`— Tile P&Rflow in place and proceeding with
`refinement stage
`some tiles have gone through the flow once already
`with decent timing for rel_3.0B (<1ns setup
`violation): AB, PA, SCB, SX, TP
`Sometiles have already hadtile reviews usingatile
`review template with the LD team.All tile should
`have their reviews regardless of progress this week.
`Othertiles either have gone through the flow with
`poor timing (>1ns) or haven't completed the flow yet,
`but don’t see any show stoppersyet (after the clock
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192115
`
`ATI Ex. 2065
`IPR2023-00922
`Page 48 of 57
`
`AMD1044_00192115
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`Top issues
`
`top level floorplan.
`
`« Many top level issuesstill need to be resolved
`Top level
`arid design
`being refined - moving to thin M7,
`need to
`follow up with pad, analog, TSMC, etc
`Top level power grid needs to be implemented
`Top level clocking needs to be implemented
`Top level P&R started, but experiencing tool crashes
`Run time issues for top level netlisting flow
`« Sometiles having problems getting through the flow
`DC — clocking issues, constraint issues, tool veer) crash
`issues. Many netlist fixes coming in netlist 4.
`RB/SP size issues — causing run time problems [>1 day
`in PKS)
`and tool memory footprint bloat In netlist 3.0, RB has 490K
`instances, SP has 400K instances
`| was to have tiles come
`in< 300K instances. DC and some TC tiles also over 300K)
`MH — currently not routable, working on tile floorplans and
`investigating ways to improve the tile aspect ratio in future netlist
`releases
`54% — roulable, but needed an area bloat, which might impact the
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192116
`
`ATI Ex. 2065
`IPR2023-00922
`Page 49 of 57
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`AMD1044_00192116
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`IPR2023-00922
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`
`
`Top issues (cont)
`
`
`
`« Global issues have causedtile P&R to
`stall/restart
`— Clock insertion strategy and clock gating structures —
`working around for now until fix in netlist 5.0 time
`frame
`
`— Virage memory size fluctuations — invalidated the
`floorplan for sometiles
`« Sometiles really can't start until rel_4.0A, but
`will try to go through the flow using rel_3.0C:
`— 2MCtiles, SQ, 3 TC tiles, KS
`« Tile utilizations pre-repeater insertion seems on
`the high side
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192117
`
`ATI Ex. 2065
`IPR2023-00922
`Page 50 of 57
`
`AMD1044_00192117
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`
`
`Risks and Future Issues
`
`impact into the design
`
`Runtime for top level netlisting flow — Currently about 5
`days. Working with Cadence to bring that down (2-3
`days?). Working on in house solutions to make
`incremental releases faster/easier
`Tile size and growth and changes — impacts top level
`floorplan for both 4.0 and 5.0
`— 4.0: TC split, SP getting bigger (400K > 440K), potential
`MH/SQ aspect ratio change
`— 5.0: RB split — will need a new tile owner
`Top level P&R and timing closure — continue to address
`issues in house and work with Cadence on tool crashes
`Scan — Will get an incremental 4.0 release from LD team
`with DFT logic in place to start implementing
`scanStitching correctly. Currently just getting routing
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192118
`
`ATI Ex. 2065
`IPR2023-00922
`Page 51 of 57
`
`AMD1044_00192118
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`
`February 12, 2003
`
`R400 Program Review
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192119
`
`ATI Ex. 2065
`IPR2023-00922
`Page 52 of 57
`
`AMD1044_00192119
`
`ATI Ex. 2065
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`
`
`R400 Review Action Summary
`- Program — Next tentative review date is on March 12"
`- Last Month
`- Rdé00 Software
`> Plan support for packet dump capiure — “oom ple!
`» Quality goal needed for conformance1eee code -
`- KOS. Meehng wih Ron VWwhile for Sv —
`f
`R400 Hardware
`: SDR 3.3 aupper an OVO porn (requiraments) — |
`« RB break-up for Netlist delivery (NL4.0 ve NLS ao= Plan
`- Code covenge analysia on all bloke —
`[npr
`:
`» DBC dependency on ae NOF - Ken Correll
`
`
`
`: PA performance registers = Compile!
`- GC testbench fer better performance etn! at work
`»
`(Gontractors to runfanalyre tests -
`t
`I
`Chip oe.
`» Power = Greg&.one
`» Operations = |),
`: Ped — Review
`Physical Design
`» Feedback from Nellis! 3 needed — Mark Le
`
`|
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192120
`
`ATI Ex. 2065
`IPR2023-00922
`Page 53 of 57
`
`AMD1044_00192120
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`ATI Ex. 2065
`IPR2023-00922
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`
`
`R400 Review Action Summary
`
`
`
`COpon
`
`: This review
`————
`= R400 Software
`+ Quality goal needed for conformance of compression/coherency code -
`=
`la HV beating waing Sel_state or Typed packets in teats — Mark Fowler
`- Sinan ints problem recestly
`= Lc Hardware
`« RB spilt for netlist & - Frank Hering
`« AB file dumps = Mike Manbar / Lany Sealer
`- Remove degamma from DATC as a feature 7
`‘Code coverage analysis on blocks -— Mark Fowler
`- TC performance path — Steve Morein | Clay Taylor / Andy Gruber
`» DC instance count high = Lili S.Frank H, to close with Mark Low
`» Assist with debug of 20 tesis = Mark Earl! John Garey ! Harry Wise
`SOVS% has risk, continue to monitor = Peter Peente
`+ Review (OP code
`= Rewrite of 20 Drivers for derivative area savings = Joe Cox
`— CP code removed, need to review — Andy Gruber ! John Carey
`= Performance
`» Orlando to work more with playback = Chris ear ae G
`+ GC testbench for better performance data = ©)
`— Chip Integration
`: Thermal schution need overall owner
`- Boards group involvement priceity (or window te bowl)
`-
`‘Operations -— give menmontuse package to Anita for ASE
`» Pad = clock distnbuton in pads needs to be finalized with Si
`— Physical Design
`+ BIF description tor R400 PD — Lil Sinclair
`: POte LO communication mostly working (may neod to expandichangelist)
`» Ciock insertion methodology = mesting 214
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192121
`
`ATI Ex. 2065
`IPR2023-00922
`Page 54 of 57
`
`AMD1044_00192121
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`High Level Schedule
`
`1-4-0
`
`G
`Eriulsice Tee! template Comsieia
`(20 Emuleter istegeation- f triaregle
`Cape Enmiilated pond! aheter idle tut
`Blech Tewting Begina
`GOAChip Inpaqiatien Sean
`Sbreutyie | Triangle ( Ereulatorready for 5
`Fine Syntheses [24]
`Verilog FeatureComplete
`Second Syrthecis in}
`ING Erutation start
`Paieg Syrthern ie
`Early blockdelivery ciara
`Figtiast
`Viertlices 3,4)
`(KOS Errulation fim! cttware! begins
`FTL.Frac! Fira Mette: bev BOOonty]
`Al) Bae Lorena: Tapeceul
`Alt Mei LopersTipecut
`Fine: Samples torBagireperig
`Ra) AiretCustomer Sanples
`412 Tapeoet
`Al2 Samplestor Eagineering
`Rao Customer Samples
`Product Delivery
`
`0-46-03
`02-11-02
`bh19-02
`ceD1-02
`C102
`Brb-O2
`De-E-02
`1
`1H
`3-0
`bite
`eb
`bor
`Choo
`1-16-07
`Gl-F1-09
`Dh78-03
`Bh403
`7-0]
`OF-15-
`OHI
`GOO]
`Ty
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192122
`
`ATI Ex. 2065
`IPR2023-00922
`Page 55 of 57
`
`AMD1044_00192122
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`Back-Up Slides
`
`ATl Corporate Presentation
`Confidential
`
`AMD1044_00192123
`
`ATI Ex. 2065
`IPR2023-00922
`Page 56of 57
`
`AMD1044_00192123
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
`
`ERSESSeRSESa &
`
`Tinta
`mn
`tia FD:
`5
`303-383
`Bd
`momtha
`1B
`iarimesh
`Lanny
`4 ey
`7aai ia
`
`DesassspeesessBERS
`
`ST
`aeaSear
`aoa rar
`sae aTTatra
`aT
`mauMann
`ids5
`
`a1i11ia1aaa1a11aaaa P
`
`y
`
`EedapPotomaeeA
`
`R400 Area Summary (2/09/03)
`
`Phe Fine
`ee |
`aren
`oe eM Bona! ey
`,a
`test
`6
`oatEe
`ha
`6
`arba
`ma Le
`fait 1een
`1a
`a
`LL seer
`LootMal vt
`DE heel TH.
`EB a
`eer ree?
`fbi Sod ee
`eT
`‘7
`ot Pinei el ae
`aS fe
`STS ua
`oie
`a
`mw
`a
`
`Peay 2Tet AGnaaD
`
`eeeotddddadddsddssgedd
`
`utie
`HG Pal
`riecea
`(are
`LeeTd
`ear?
`re
`marr
`oh Fite
`Thi
`SL TET
`ttehait
`aT
`"1 FmUSeT
`subTa
`mim
`RITLire
`
`ATI Corporate Presentation
`Confidential
`
`AMD1044_00192124
`
`ATI Ex. 2065
`IPR2023-00922
`Page 57of 57
`
`AMD1044_00192124
`
`ATI Ex. 2065
`IPR2023-00922
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`
`
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