`regress
`
`Gate
`regress
`
`Area
`
`Design
`BIF
`
`MC
`
`HDP
`
`RTL
`Coding
`100%
`
`95%
`
`100%
`
`VIP/ROM/I2C
`
`100%
`
`Display
`
`100%
`
`DFT/IO
`System
`
`100%
`NA
`
`Synthesis
`timing
`SCLK
`BCLK
`AGPCLK
`MCLK
`SCLK
`MCLK
`SCLK
`BCLK
`SCLK
`FCP
`SCLK
`PIXCLK
`P2GCLK
`OV0CLK
`TMDS
`TVOUT
`DVOCLK
`NA
`NA
`
`Internal
`Worst
`timing
`
`External
`Worst
`timing
`
`Target
`timing
`
`Violation
`
`NA
`
`NA
`
`NA
`
`NA
`
`AMD1044_0188854
`
`
`
`Design
`
`RTL
`specs
`
`RTL
`coding Emulation
`
`Tests
`Written
`
`dcp
`lb
`scl
`crtc
`dispout
`tvout
`
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`
`90%
`100%
`
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`
`90%
`100%
`
`100%
`98%
`98%
`100%
`100%
`80%
`no emu
`no emu
`no emu
`no emu
`99%
`100%
`
`90%
`100%
`
`100%
`98%
`91%
`100%
`100%
`50%
`no tests
`no tests
`no tests
`no tests
`100%
`100%
`
`30%
`100%
`
`display
`
`dccg
`dccif
`rbbmif
`dmif
`vga
`vip
`VideoIP(DC)
`BIF
`IDCT
`Total
`
`12/9/2002
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 2 of 10
`
`
`
`Clock
`2.25
`2.25
`2.25
`2.25
`2.25
`10.00
`2.25
`2.25
`
`14.00
`3.50
`2.25
`2.25
`
`Area (mm2)
`2.41
`1.42
`1.39
`0.25
`0.67
`0.93
`0.39
`0.49
`8.27
`1.63
`
`Area
`accuracy
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`100%
`97%
`99%
`
`1.22
`
`99%
`
`Timing
`3.72
`3.25
`3.23
`2.25
`3.13
`10.76
`4.43
`2.38
`
`12.39
`3.50
`2.78
`2.90
`
`display
`
`Design
`dcp
`lb
`scl
`crtc
`dispout
`tvout
`
`vga
`vip
`VideoIP(DC)
`BIF
`
`IDCT
`Total
`
`12/9/2002
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 3 of 10
`
`
`
`Design
`features
`VideoIP(DC) display
`
`dcp
`lb
`scl
`crtc
`dispout
`tvout
`
`EMU
`100%
`#DIV/0!
`100%
`#DIV/0!
`
`100%
`#DIV/0!
`100%
`100%
`100%
`
`100%
`100%
`
`Completed Planned Added
`143
`143
`0
`
`89
`
`54
`
`100
`72
`458
`
`396
`854
`
`89
`
`54
`
`100
`72
`458
`
`396
`854
`
`0
`
`0
`
`
`
`
`
`
`
`Subtotal
`
`IDCT
`Total
`
`8/1/2002
`
`vga
`vip
`
`
`
`
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 4 of 10
`
`
`
`Planned
`M1
`features
`VideoIP(DC 30-Apr
`dcp
`30-Apr
`lb
`30-Apr
`scl
`30-Apr
`crtc
`30-Apr
`dispout
`30-Apr
`dispout
`30-Apr
`vga
`30-Apr
`vip
`30-Apr
`bif
`30-May
`idct
`30-May
`idct
`30-May
`
`Achieved
`M1
`31-May
`31-May
`31-May
`31-May
`31-May
`31-May
`31-May
`31-May
`31-May
`
`30-Jun
`30-Jun
`
`Planned
`M2
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`
`Achieved
`M2
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`
`Achieved
`M2
`
`Planned
`M2
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`
`feature
`completion
`#REF!
`180
`14
`8
`34
`54
`54
`34
`270
`225
`279
`279
`783
`
`code
`freeze
`#REF!
`202
`18
`78
`50
`79
`79
`154
`275
`240
`279
`279
`798
`
`VideoIP Milestones
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`Planned M1
`Actual M1
`
`Planned M2
`Actual M2
`
`Planned M3
`
`1
`
`Design
`VideoIP(DC)
`
`vga
`vip
`
`
`
`
`Year 2002
`
`
`
`
`
`
`
`BIF
`IDCT
`IDCT
`Total
`
`Design
`VideoIP(DC)
`
`features
`
`dcp
`lb
`scl
`crtc
`dispout
`dispout
`vga
`vip
`
`
`
`
`vga
`vip
`
`
`
`
`RTL
`regress
`#REF!
`32%
`21%
`38%
`44%
`54%
`54%
`65%
`100%
`7%
`86%
`86%
`63%
`
`Tests
`passing
`#REF!
`57
`3
`3
`15
`29
`29
`22
`270
`15
`240
`240
`495
`
`Tests
`Written
`#REF!
`180
`14
`8
`34
`54
`54
`34
`270
`225
`279
`279
`783
`
`Tests
`Planned
`#REF!
`202
`18
`78
`50
`79
`79
`154
`275
`240
`279
`279
`798
`
`100%100%
`
`100%
`
`85%
`
`89%
`
`100%
`
`92%
`
`91%
`
`36%
`
`tests passing
`
`6%
`
`0%
`
`
`
`
`
`
`
`BIF
`IDCT
`IDCT
`Total
`
`120%
`
`100%
`
`80%
`
`60%
`
`40%
`
`20%
`
`0%
`
`features
`DC
`dcp
`lb
`scl
`crtc
`dispout
`tvout
`vga
`vip
`bif
`idct
`system
`
`vga
`vip
`
`
`
`
`Design
`VideoIP(DC)
`
`
`
`
`
`
`
`BIF
`IDCT
`
`Total
`
`12/9/2002
`
`RTL
`regress
`
`Tests
`passing
`
`Tests
`Written
`
`Tests
`Planned
`
`Tests
`written
`
`100%
`100%
`85%
`100%
`89%
`36%
`92%
`100%
`6%
`91%
`0%
`93%
`
`375
`47
`98
`131
`206
`18
`202
`275
`15
`255
`0
`1607
`
`375
`47
`105
`131
`232
`25
`220
`275
`40
`279
`0
`1689
`
`375
`47
`115
`131
`232
`50
`220
`275
`240
`279
`80
`1724
`
`100%
`100%
`91%
`100%
`100%
`50%
`100%
`100%
`17%
`100%
`0%
`98%
`
`Block Rregression 12/10
`
`tests passing
`tests written
`tests planned
`
`blocks
`
`400
`
`350
`
`300
`
`250
`
`200
`
`150
`
`100
`
`50
`
`0
`
`number of tests
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 5 of 10
`
`
`
`Design
`VideoIP(DC)
`
`features
`
`dcp
`lb
`scl
`crtc
`dispout
`dispout
`vga
`vip
`
`
`
`
`vga
`vip
`
`
`
`
`RTL
`regress
`#REF!
`32%
`21%
`38%
`44%
`54%
`54%
`65%
`100%
`7%
`86%
`86%
`63%
`
`Tests
`passing
`#REF!
`57
`3
`3
`15
`29
`29
`22
`270
`15
`240
`240
`495
`
`Tests
`Written
`#REF!
`180
`14
`8
`34
`54
`54
`34
`270
`225
`279
`279
`783
`
`Tests
`Planned
`#REF!
`202
`18
`78
`50
`79
`79
`154
`275
`240
`279
`279
`798
`
`Planned
`M1
`features
`VideoIP(DC 30-Apr
`dcp
`30-Apr
`lb
`30-Apr
`scl
`30-Apr
`crtc
`30-Apr
`dispout
`30-Apr
`dispout
`30-Apr
`vga
`30-Apr
`vip
`30-Apr
`bif
`30-May
`idct
`30-May
`idct
`30-May
`
`Achieved
`M1
`31-May
`31-May
`31-May
`31-May
`31-May
`31-May
`31-May
`31-May
`31-May
`
`30-Jun
`30-Jun
`
`Design
`VideoIP(DC)
`
`
`
`
`
`
`
`BIF
`IDCT
`IDCT
`Total
`
`vga
`vip
`
`
`
`
`Planned
`M2
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`31-Jul
`
`Achieved
`M2
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`31-Aug
`
`Achieved
`M2
`
`Planned
`M2
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`31-Oct
`
`feature
`completion
`#REF!
`180
`14
`8
`34
`54
`54
`34
`270
`225
`279
`279
`783
`
`code
`freeze
`#REF!
`202
`18
`78
`50
`79
`79
`154
`275
`240
`279
`279
`798
`
`91%
`
`64%
`
`tests passing
`
`10%
`
`0% 0% 0% 0% 0% 0%
`
`2%
`
`0%
`
`
`
`
`
`
`
`BIF
`IDCT
`IDCT
`Total
`
`100%
`90%
`80%
`70%
`60%
`50%
`40%
`30%
`20%
`10%
`0%
`
`features
`DC
`dcp
`lb
`scl
`crtc
`dispout
`tvout
`vga
`vip
`bif
`idct
`system
`
`vga
`vip
`
`
`
`
`Design
`VideoIP(DC)
`
`
`
`
`
`
`
`BIF
`IDCT
`
`Total
`
`11/10/2002
`
`RTL
`regress
`
`Tests
`passing
`
`Tests
`Released
`
`Tests
`Planned
`
`10%
`0%
`0%
`0%
`0%
`0%
`0%
`91%
`2%
`64%
`0%
`11%
`
`37
`
`0
`249
`5
`179
`0
`184
`
`375
`47
`105
`131
`232
`25
`220
`275
`51
`279
`0
`1740
`
`375
`47
`115
`131
`232
`50
`220
`275
`240
`279
`80
`2044
`
`100%
`100%
`91%
`100%
`100%
`50%
`100%
`100%
`21%
`100%
`0%
`
`Chip Regression 12/5
`
`tests passing
`tests written
`tests planned
`
`blocks
`
`400
`
`350
`
`300
`
`250
`
`200
`
`150
`
`100
`
`50
`
`0
`
`number of tests
`
`Planned M1
`Actual M1
`
`Planned M2
`Actual M2
`
`Planned M3
`
`VideoIP Milestones
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`1
`
`Year 2002
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 6 of 10
`
`
`
`Design
`VideoIP(DC) display
`
`features
`
`
`
`
`
`
`
`Subtotal
`BIF
`IDCT
`Total
`
`vga
`vip
`
`
`
`
`RTL
`regress
`100%
`#DIV/0!
`100%
`#DIV/0!
`100%
`#DIV/0!
`100%
`100%
`100%
`100%
`100%
`100%
`
`dcp
`lb
`scl
`crtc
`dispout
`
`
`
`
`Tests
`passing
`143
`
`No. of
`tests
`143
`
`No. of
`new tests
`0
`
`89
`
`54
`
`100
`72
`458
`120
`396
`974
`
`89
`
`54
`
`100
`72
`458
`120
`396
`974
`
`0
`5
`
`5
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 7 of 10
`
`
`
`Display/VIP/HDP/I2C/ROM
`Wayne Wu
`Eric Shen
`Jonathan Wang
`Nat Barbarieo
`Merat Khabbari
`Stephen Bagshaw
`Gabriel Abarca
`Slaven
`
`CG/CGM/dispclkblk
`
`Nader Tavasoli
`
`8
`100% Team Lead
`100% Display syn; syncgen, macrovision, vip
`90% ov0scale, vcp
`100% subpic, i2c, rom
`100% tvout, dvo, panel, panel2
`60% hdcp, rmx
`100% display1, display2, hdp, cgms
`100% vip syn; syncgen, macrovision,
`
`1
`
`100%
`
`clock generation, power
`management, dynamic
`clocking
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 8 of 10
`
`
`
`MC
`Carl Mizuyabu
`Desmond Wong
`William Hui
`Boris Boskovic
`Mark Dell'Agnese
`BIF
`Danny Cheung
`Gord Caruk
`Anthony Tam
`DFT
`Rob Treuer
`Ed Morson
`Name
`
`5
`70% Team Lead, architect
`100% mc syn, performance improvements
`100% mc client interfaces
`100% QDR IO changes
`100% MC verification
`3
`90% Team Lead
`90% agp fast write
`bif syn & verification
`
`3
`50% Team lead
`50% JTAG; scan chain
`100% scan insertion(sblk1, sblk2)
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 9 of 10
`
`
`
`Completion
`
`Diag
`plan(status)
`
`Software
`plan(status)
`
`IKOS functions
`IKOS PC#1-boot up
`Reg r/w
`mem r/w
`bios,Display/2D
`IKOS PC#2-boot up,
`sdr bring up
`3D/AGP
`DDR, SDR
`
`Plan
`15-Sep
`22-Sep
`29-Sep
`30-Oct
`
`15-Nov
`30-Nov
`30-Dec
`
`AMD1044_0188854
`
`ATI Ex. 2051
`
`IPR2023-00922
`Page 10 of 10
`
`