December11, 2002
`
`~ R400 Program Review
`
`AT! Corporate Presentation
`
`AMD1044_0188841
`
`ATI Ex. 2048
`IPR2023-00922
`Page 1 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 1 of 11
`
`
`
`~ R400 Program Review
`
`AT! Corporate Presentation
`
`AMD1044_0188841
`
`ATI Ex. 2048
`IPR2023-00922
`Page 1 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 1 of 11
`
`
`
`
`Target Milestones in Last Month
`
`
`
`HY
`
`
`
`
`
`
`
`
`- R400 Program Milestones
`— Code freeze by 11/23
`
`
`
`- Toronto R400 milestones
`— Complete DC phase #3 by 10/30
`— Chip level regression run by 10/30
`— Ikos validation start 11/4
`
`vd
`CONEIDENTIAL
`
`AT! Corporate Presentation
`
`AMD1044_0188842
`
`ATI Ex. 2048
`IPR2023-00922
`Page 2 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 2 of 11
`
`
`
`
`
`
`What Have We Achieved
`
`
`
`
`
`
`
`- Status Summary
`— Although codeis not frozen the coding is completed
`with bug fixes only.
`— Achievedregister spec freeze.
`— Completed 99% emulation work.
`— Achieved overall 93% block regression passing with
`few tests outstanding in tvout, scaler, bif & system.
`— Overall 15%chip regression passing.
`— Closed Virage Star memory timing issues.
`
`Ki}
`CONEIDENTIAL
`
`AT! Corporate Presentation
`
`AMD1044_0188843
`
`ATI Ex. 2048
`IPR2023-00922
`Page 3 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 3 of 11
`
`
`
`
`What Have WeAchieved
`
`(specs, coding, emulation, tests)
`
`
`- Coding is 100% complete with the exception ofbif.
`+ Emulation is 100% completed in mostblocks with the rest to finish by 12/20.
`+ Tests are mostly 100% released exceptfor Ib, scl, tvout, bif & system. The
`remaining block tests plan to complete by 12/20 while system tests by 1/20.
`
`
`
`Tests
`RTL
`coding Emulation Written
`
`100%
`
`100%
`
`
`
`90%
`95%
`BIFO| 95%
`
`ve=|IDCT ||100% 100% 100% 100%
`
`
`4
`
`AT! Corporate Presentation
`
`AMD1044_0188844
`
`ATI Ex. 2048
`IPR2023-00922
`Page 4 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 4 of 11
`
`
`
`6/14/2017
`
`5
`CONEIDENTIAL
`
`What Have We Achieved
`(block RTL regression)
`
`- Dep, Ib, crtc, vip are 100%passing
`- Scaler, dispout, vga & idct are above 90%passing
`- Tvout plan to resolve clocking issue and reach 100%passing by
`Jan 6. Bif is behind due to resource shortage.
`
`Block Rregression 12/10
`
`
`
`
`
`400
`
`350
`
`300
`
`250
`200
`
`450
`
`numberoftests
`
`@ tests passing
`@ tests written
`
`@ tests planned
`
`££
`2
`
`-<
`
`SS
`wf
`SF
`s & 3
`
`SF
`
`SC QS YK
`SL
`we
`TV
`DH
`ww? se
`blocks
`
`
`
`AT! Corporate Presentation
`
`AMD1044_0188845
`
`ATI Ex. 2048
`IPR2023-00922
`Page 5 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 5 of 11
`
`
`
`6/14/2017
`
`6
`CONEIDENTIAL
`
`What Have WeAchieved
`(Chip regression)
`
`- VIP 91%, IDCT 64%, dcp 10%& bif 2% tests passed
`- Other display tests run were gated by DC-MH interface bugs &
`golden images.It’s in debug stage.
`- Debug resourcein bif will be addedstarting this week.
`
`——
`
`Chip Regression 12/5
`
`400
`
`350
` 300
`
`numberoftests
`
`250
`200
`
`150
`100
`
`50
`
`0
`
`es © o x# s od Fr S YS S
`s
`&
`blocks
`
`@ tests passing
`@ tests written
`
`@ tests planned
`
`AT! Corporate Presentation
`
`AMD1044_0188846
`
`ATI Ex. 2048
`IPR2023-00922
`Page6 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 6 of 11
`
`
`
`
`
`
`What Have WeAchieved
`(Area & Timing)
`
`- Most blocks have violations with the worst path of 4.43ns
`- Moreefforts will be in place for achieving revised target
`speed of 440mhz scik
`
`0
`
`Clock
`
`Area(mm2) accuracy Timing
`
`Area
`
`VideolIP(DC)| —s
`BIF
`
`14.00
`
`8.27
`1.63
`
`97%
`99%
`
`CONEIDENTIAL
`6/14/2017
`
`DoT
`
`2254.22
`
`99%
`
`12.39
`3.50
`2.78
`2.90
`
`AT! Corporate Presentation
`
`
`
`AMD1044_0188847
`
`ATI Ex. 2048
`IPR2023-00922
`Page 7 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 7 of 11
`
`
`
`
`
`
`What’s ahead?
`
`
`
`
`
`
`Managetherisk in BIF design:
`
`- BIF becamea high risk block due to
`— 1 design resource allocated for both RV280 & R400, as a result
`R400 is compromised in schedule.
`— No design verification resource dedicated for porting the existing
`tests from R300 due to resource shortages.
`— Strategic decision was madeto usechip asverification
`vehichale for BIF. However, chip level environmentisstill not
`stable to date. This obviously hurt the BIF progress.
`
`
`
`
`
`
`
`
`
`- Steps to control the risk
`— Allocate 1 design resource from DC to strengthen the debug
`Capability, starting now.
`— Add anew hire as a third resourcein BIF, starting next week.
`— Allocate dedicated design verification resource to complete test
`porting and newtests, already started
`
`b]
`CONEIDENTIAL
`6/14/2017
`
`AT! Corporate Presentation
`
`AMD1044_0188848
`
`ATI Ex. 2048
`IPR2023-00922
`Page8 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 8 of 11
`
`
`
`
`What’s ahead?
`
`
`
`
`Next Set of Goals:
`
`- Achieve 100% passing in block regression
`by 12/13 with tvout being 1/6.
`- Start IKOS debug 12/20.
`- Achieverevisedtiming goals by 12/30.
`- Achieve 50% regression passing in chip by
`12/30, 100% by 1/30.
`- Start Gate level simulation in Jan.
`
`
`
`
`
`
`
`
`- Complete system tests & debugged by 1/30
`
`- Deliverfinal netlist 1/30.
`
`9
`CONEIDENTIAL
`
`AT! Corporate Presentation
`
`AMD1044_0188849
`
`ATI Ex. 2048
`IPR2023-00922
`Page 9 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 9 of 11
`
`
`
`Open Issues
`
`
`
`
`- Need to determine R400 capability of
`supporting 480Mhz DDR DVO
`- Need to determine Endian swap on 64bpp
`
`
`
`
`alt)
`CONEIDENTIAL
`6/14/2017
`
`AT! Corporate Presentation
`
`AMD1044_0188850
`
`ATI Ex. 2048
`IPR2023-00922
`Page 10 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 10 of 11
`
`
`
`
`
`
`
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`
`
`Chip releases has been quite unstable. This has
`impacted chip validation progress,in turn bif validation.
`Chip regressionis a bottleneck for Toronto to meetfinal
`netlist date
`Delayed support of MH/MC interfaces on chip
`regression & ikos validation can delay the final netlist
`date for Toronto designs.
`Emulator maintenance on solaris will be a bottleneck
`for chip gate sim debugif anyone ignores the
`breakdowns.
`BIF AGP 64byte write feature will likely to be left out
`due to the fact that BIF is behind the schedule.
`
`
`
`
`
`
`Risks
`
`oh
`CONEIDENTIAL
`
`AT! Corporate Presentation
`
`AMD1044_0188851
`
`ATI Ex. 2048
`IPR2023-00922
`Page 11 of 11
`
`ATI Ex. 2048
`
`IPR2023-00922
`Page 11 of 11
`
`
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