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`ATI TECHNOLOGIES INC.
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`R400 PD
`
`June 14, 2017
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`AMD1044_0188744
`
`ATI Ex. 2044
`IPR2023-00922
`Page 1 of 8
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`1 PD Manager
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`* 8 ATI PD Engineers
`* 6 PD Contractors
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`*
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`1 ATI CAD Engineer
`2 CAD Contractors
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`R400 Full Time PD Staff
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`ATI TECHNOLOGIES INC.
`
`June 14, 2017
`
`AMD1044_0188745
`
`ATI Ex. 2044
`IPR2023-00922
`Page 2 of 8
`
`ATI Ex. 2044
`
`IPR2023-00922
`Page 2 of 8
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`R400 PD Activities
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`Initial floorplanning effort
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`Initial tile netlist generation effort
`*
`* Block P&R experiments
`* Tool evaluation
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`Top Level flow development
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` ATI TECHNOLOGIES INC.
`
`[DateTime]
`
`June 14, 2017
`
`AMD1044_0188746
`
`ATI Ex. 2044
`IPR2023-00922
`Page 3 of 8
`
`ATI Ex. 2044
`
`IPR2023-00922
`Page 3 of 8
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`Initial Floorplanning Effort
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`After someinitial startup problems with tool usage and
`netlist connectivity, have now donetwofloorplan reviews
`with Front End and Back End teams based on netlist 2.
`Steve M in SiV Monday/Tuesdayof this week and based on
`the 2"! review provided 4 testcases to run. Goalis to provide
`feedback to him by Thursday so we can have another review
`and Steve can give us moretestcasesto run by Friday.
`Will have to go throughthis flow again for netlist 3 since
`block areas will change.
`
`Have gotten tool run time downbyhalf.
`eects is an FEfile to seedthetile netlist generation
`
`ow.
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`ATI TECHNOLOGIES INC. [DateTime]
`
`June 14, 2017
`
`AMD1044_0188747
`
`ATI Ex. 2044
`IPR2023-00922
`Page 4 of 8
`
`ATI Ex. 2044
`
`IPR2023-00922
`Page 4 of 8
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`Initial Tile Netlist Generation
`Effort
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`Using early version of Steve M’s area based
`floorplan as a guide (pre-FE feedback).
`Initial tile partitioning very manual.
`FEfile from initial floorplan effort will help automate
`this process more.
`* Close to getting first cut at tile netlists.
`Deliverable is netlists/defs/etc ready for P&R flow.
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`ATI TECHNOLOGIES INC.
`
`June 14, 2017
`
`AMD1044_0188748
`
`ATI Ex. 2044
`IPR2023-00922
`Page 5 of 8
`
`ATI Ex. 2044
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`IPR2023-00922
`Page 5 of 8
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`Block P&R experiments
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`Took mh, sp, sc, and dc block netlists and madetiles out of
`them quickly in FE without toplevel connectivity/floorplan
`information
`Working through netlist/environment compatibility issues
`Had to relax timing for mh, sc, and de
`Currently all tiles are iterating through placement
`Deliverables are wireload models to the Front End team for
`review and congestion/routing/timing data.
`Investigated ways to generate wireloads using placement
`tools, but the feedback from vendorsis that the quality is
`very hit and miss.
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`ATI TECHNOLOGIES INC. [DateTime]
`
`June 14, 2017
`
`AMD1044_0188749
`
`ATI Ex. 2044
`IPR2023-00922
`Page6 of 8
`
`ATI Ex. 2044
`
`IPR2023-00922
`Page 6 of 8
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`Tool Evaluation
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`Focus is on doing spot tool evaluations, not creating an all-Cadenceflow.
`Doing 3 independenttool evals.
`Purposeis to be able to cut the P&Ritiming iterations to help routing and
`timing closure.
`Flow in place for PC replacement eval using FE/PKS.
`3 tiles actively running through this PC replacementflow to generate
`results.
`Flow in developmentfor pbopt replacementeval using PKS
`Flow developmentfor wroute replacementeval using nanoroute needs to
`get started
`Goalis to wrap up bythe end of the year, however probablywill push out
`to thefirst of the year. Understand the need to lock down the P&Rflow
`early.
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` AT! TECHNOLOGIES INC.
` [DateTime]
`
`
`June 14, 2017
`
`AMD1044_0188750
`
`ATI Ex. 2044
`IPR2023-00922
`Page7 of 8
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`ATI Ex. 2044
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`IPR2023-00922
`Page 7 of 8
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`Top Level Flow
`Development
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`* Running small R300 based SCtestcaseall the way
`through LVS/DRCto validate the toplevelflow.
`* Most functionality there, but a few issues need to be
`resolved (repeaters, powergrid, etc).
`* Need to movefrom feature additions to support
`mode soon. Meeting this week to lock downall
`features.
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`
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`ATI TECHNOLOGIES INC.
`
`June 14, 2017
`
`AMD1044_0188751
`
`ATI Ex. 2044
`IPR2023-00922
`Page 8 of 8
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`ATI Ex. 2044
`
`IPR2023-00922
`Page 8 of 8
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