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`ATI TECHNOLOGIESINC.
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`R400 PD
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`June 14, 2017
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`AMD1044_0185528
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`ATI Ex. 2040
`IPR2023-00922
`Page 1 of 9
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`:
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`R400 PD Team
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`oals
`¢ Schedule, schedule, schedule, schedule, ...
`* Reuse Flow: better floorplan, reduce # oftiles,
`put tiles on the shelf earlier...
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`ATI TECHNOLOGIES INC.
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`Staffing
`« Ed C (owns PD schedule)
`* Joe G (ownsfront-end Marlboro *Link’)
`* Dedicated PD team (separate teams for RV350 &
`R350 Re-spin’s & SB300)
`* Experienced R400 PD team (15 total)
`2 ATI on R400 now
`8 ATI roll over from RV350 (9) PD team
`5 Contractors (Nova & Spike) & ATI
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`June 14, 2017
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`AMD1044_0185529
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`ATI Ex. 2040
`IPR2023-00922
`Page 2 of 9
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`Flow/Tools
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`+ Leverage RV350flow/tools
`¢ PhysOpt for Placement Engine
`* Clockwise for Clock Tree Generation
`* Celtic for Signal Integrity analysis
`¢ Voltage Storm for IR analysis
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`ATI TECHNOLOGIES INC.
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`[DateTime]
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`June 14, 2017
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`AMD1
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`044_0185530
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`ATI Ex. 2040
`IPR2023-00922
`Page 3 of 9
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`Netlist Handoff’s
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`1st Netlist
`* Netlist quality good enough soinitial floorplan work not wasted
`* Rough pad ring and analog macro placementin place.
`* Clock structure in place, with some documentation
`* Reasonable top level constraints
`* Needlibraries in-place (e.g.., preliminary lef’s of all netlist
`components)
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`Deliverable from Marlboro
`* 1% SPC passfloor-plan (Marlboro lead, SVC CAD support)
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`Pen)
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`ATI TECHNOLOGIES INC.
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`June 14, 2017
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`AMD1044_0185531
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`ATI Ex. 2040
`IPR2023-00922
`Page 4 of 9
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`Netlist Cont’d
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`N+1 to 95% Netlist
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`Deliverable from Marlboro
`*95% netlist, meeting pre-layout timing w/ slack
`* Powercompiler, pipeline flops, and any specialnetlist all in
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`place.
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`*Fullchip constraints (SDC) w/ false/multi-cycle paths
`* Synthesis frozen for new features. Bug fixes only.
`* DFT near final, with final documentation.
`* Clock structure nearfinal, with final documentation, including
`fullchip clock diagram.
`* SPC floorplan with valid superblocksidentified
`(good pin count, < 300K instances, 70%initial utilization)
`* Replicable blocks identified.
`* PADring in place, with replication in mind.
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`Pen)
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`ATI TECHNOLOGIES INC.
`
`June 14, 2017
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`AMD1044_0185532
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`ATI Ex. 2040
`IPR2023-00922
`Page 5 of 9
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`Netlist Cont’d
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`N+1 to 95% Netlist
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`SVC Responsibility
`* Execute and create real floor-plan, with superblocks,
`and toplevel.
`* Create constraints for the superblocks
`* Implement real powergrid, including SRAM power
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`Pen)
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`strategy
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`* Iterate to find best SRAM placements.
`* Iterate to find best analog macro placements
`* Execute PD flow for all unique superblocks, provide
`feedback on routability and timing
`* Execute PD flow for toplevel, provide feedbackfor
`
`iming
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`ATI TECHNOLOGIES INC.
`
`June 14, 2017
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`AMD1044_0185533
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`ATI Ex. 2040
`IPR2023-00922
`Page 6 of 9
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`Netlist Cont’d
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`Final Netlist
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`Deliverable from Marlboro
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`* Final netlist
`* All bug fixes by ECO only or as requested by SVC
`* Final padring
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` [DateTime]
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`ATI TECHNOLOGIES INC.
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`June 14, 2017
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`AMD1044_0185534
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`ATI Ex. 2040
`IPR2023-00922
`Page 7 of 9
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`Netlist Cont’d
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`Final Netlist
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`SVC Responsibility
`* Iterate to get routability/good timing on all superblocks
`* Execute and createreal floor-plan, with superblocks,
`and toplevel.
`* Create constraints for the superblocks.
`* Implement real powergrid, including SRAM power
`strategy.
`* Finalize SRAM placements.
`* Finalize analog macro placements.
`* Execute PD flow for all unique superblocks, provide
`feedback on routability and timing.
`* Execute PD flow for toplevel, provide feedbackfor
`
`Pen)
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`iming.
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`ATI TECHNOLOGIES INC.
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`June 14, 2017
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`AMD1044_0185535
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`ATI Ex. 2040
`IPR2023-00922
`Page 8 of 9
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`R400 PD Schedule
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`2
`<--—-----------> S$---—-—-—---—--> SS
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`A
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`A
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`A
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`A
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`1st Netlist
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`95% Netlist
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`Final Netlist
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`Tape-Out
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`
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`ATI TECHNOLOGIES INC.
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`[DateTime]
`
`June 14, 2017
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`AMD1
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`044_0185536
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`ATI Ex. 2040
`IPR2023-00922
`Page 9 of 9
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