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`ATI TECHNOLOGIES INC.
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`R400 I/O
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`February 12, 2003
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`May 2, 2017
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`AMD1044_0051118
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`ATI Ex. 2019
`IPR2023-00922
`Page 1 of 8
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`R400 I/O Activities
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`* Pad ring review with Greg S. on 2/14 in SiV
`*
`JO/NPL review on 2/25 & 2/26 in SiV with team from
`Marlborough
`* Viper program
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`ATI TECHNOLOGIES INC.
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`May 2, 2017
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`AMD1044_0051119
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`ATI Ex. 2019
`IPR2023-00922
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`ATI Ex. 2019
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`IPR2023-00922
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`Memory W/O & Clock
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`First pass design of the memory I/O is complete.
`* First pass design of the memory clock is complete.
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`* Layout schedule
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`* Memory I/O - 2/13
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`* Memory clock - 2/18
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`* Memory calibration - 2/20
`* Memory strobe - 2/21
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`* Library files
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`* Verilog - complete and checkedinto the tree
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`* LEF of Memory I/O, clock, calibration, and strobe -- 2/18
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`* TLF/LIB/DB of memory I/O,clock,calibration, and strobe - 2/21
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` ATI TECHNOLOGIES INC. [DateTime]
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`May 2, 2017
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`AMD1044_0051120
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`ATI Ex. 2019
`IPR2023-00922
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`ATI Ex. 2019
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`IPR2023-00922
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`Memory Near Pad Logic
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`RTL-to-schematic implementation
`* ADDR, DATA, DQSM, DQSS and HCLKare done first pass
`* All five pass LEC
`* Started timing simulations (HSPICE)
`* Found bug in IO/NPL which required the NPL to be updated
`* Layout to start on 2/15 and complete on 3/15
`* Library files (LEF, TLF, LIB, and DB) will be deliver on 3/1
`On going memory system timing - complete on 3/15
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`[DateTime]
`ATI TECHNOLOGIES INC.
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`May 2, 2017
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`AMD1044_0051121
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`ATI Ex. 2019
`IPR2023-00922
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`ATI Ex. 2019
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`IPR2023-00922
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`Delay Line and misc
`layout
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`* Design is done
`* Layout is complete
`* Miscellaneouslayout
`* ChrisV/KarenW started layout on the miscellaneouscells
`* PVREF
`* Corners
`* Spacers
`* Breaks
`Complete on 3/1
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`ATI TECHNOLOGIES INC. [DateTime]
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`May 2, 2017
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`AMD1044_0051122
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`Viper program
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`* What is the Viper program?
`*
`It’s a joint development between ATI and Micron to design
`the bring up vehicle for GDDR3.
`* Viper is a test chip which contains the memory controller
`and supporting logic from Micron.
`* ATI provides the I/Os, analog components (PLL and Delay
`line), and package design.
`*
`|/Os, PLL and Delayline are the same design used for R400.
`* Designed for the TSMC 0.13um cyber shuttle (the process
`is similar to the RV350/R400).
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` ATI TECHNOLOGIES INC. [DateTime]
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`May 2, 2017
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`AMD1044_0051123
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`ATI Ex. 2019
`IPR2023-00922
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`Weekly (Tuesdays) conferencecall with Micron.
`° Deliveredinitial views of all cells to be used in Viper.
`* Delivery of final models to Micron on 2/21.
`* Pad ring spreadsheetis complete.
`* Pad ring DRC/LVS clean to Micron on 2/28.
`°
`If all goes well, Viper tapes out in mid Marchto early
`April (also depends on cyber shuttle schedule).
`Started package design on 2/11.
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`ATI TECHNOLOGIES INC.
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`Viper Schedule
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`May 2, 2017
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` Deliverables
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`* Final LEF, TLF, LIB, DB and verilog on 3/1 (ontarget)
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`* Ring DRC/LVSclean and gds delivery on 4/15 (on target)
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` ATI TECHNOLOGIES INC. [DateTime]
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`May 2, 2017
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