` icrosoft Site Visit
`February 20, 2003
`
`ATI Corporate Presentation
`
`AMD1044_0050923
`
`ATI Ex. 2015
`IPR2023-00922
`Page 1 of 16
`
`ATI Ex. 2015
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`IPR2023-00922
`Page 1 of 16
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`
`
`Agenda
`
`@ 9:30 — 10:00
`
`@ 10:00 — 10:30
`
`Introduction / Orlando Organization
`Overview of Development Process
`& Tools
`
`@ 10:30 — 11:00
`
`@ 11:00 — 12:00
`
`Top Level Development Schedule
`Demo’s
`
`@ 12:00 — 1:00
`
`Lunch
`
`CONEIDENTIAL
`
`
`@ 1:00 — 4:00
`
`@ 4:00
`
`2
`
`Meetings with individual Teams
`Architecture
`Verification
`Performance / Benchmarking
`Wrap-Up
`
`ATI Corporate Presentation
`
`AMD1044_0050924
`
`ATI Ex. 2015
`IPR2023-00922
`Page 2 of 16
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`ATI Ex. 2015
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`IPR2023-00922
`Page 2 of 16
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`
`
`ATI Orlando Office - Histo
`2 6ge CR AARNEMREDORR ENETRCNRREESE Ae
`
`@ ATI Orlando
`
`@ 40 Employees
`
`e 16 SW&Sys Validation
`
`e 24 HW Design &
`Validation
`
`raw
`
`Real 31 Start-up
`
`
`ATE
`
`a 99-Present
`aA 97-99
`A 746Co-op
`feeder BST etmentfree
`aA —_
`@ Commercial Experience
`SEENONSus
`
`bravesepoet ag caitel
`
`96-97
`
`.
`
`.
`
`@ Sega Model 1 (Daytona USA)
`@ Sega Model 2
`@ Intel 740 3D Graphics
`K
`77-93
`Architecture
`CONEIDENTIAL
`BIAyALASf
`
`93-96
`
`ATI Corporate Presentation
`
`AMD1044_0050925
`
`ATI Ex. 2015
`IPR2023-00922
`Page 3 of 16
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`ATI Ex. 2015
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`IPR2023-00922
`Page 3 of 16
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`
`
`ATI - Orlando Staffing
`Feb 2003
`
`
`
`Joe Cox
`Site Director
`|
`
`ay
`
`mn
`
`nee
`
`Cane may OORT
`
`
`
`
`
` Phat Hungh
`
`
`
`
`a [JohnCarey
`
`
`
`|
`¥
`Rd
`¥.
`¥
`¥
`¥
`
`Chris Gra
`Mike Mantor
`Jeff Weyman
`Clay Taylor
`Tim Kelley
`Dave Gotwalt
`Nae Mot
`Architect(*
`SWManager
`Bi Arch /Emul, Mgr.
`"*«|
`SWaArchitect/
`|**4=-SWArchitect/
`HW Mgr.
`PTL, OpenGL
`Tech. Evangelist
`DirectX-Geometry
`DirectX-Raster
`
`
`Alex Ashkar
`Mike Quinlan
`{Mike Meng|
`
`
`Jot Brady
`
`©{ScottHartog|
`Brian Buchner
`
`Steve Camiin
`~|Marcos
`Dan Clifton
`Dean Waiker
`Mack Earl
`Sunshine Chen
`Bob Hankinson
`
`Randy Ramsey
`Tushar Shah
`
`rs
`CONEIDENTIAL
`BAVAwe
`
`ATI Corporate Presentation
`
`AMD1044_0050926
`
`ATI Ex. 2015
`IPR2023-00922
`Page 4 of 16
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`ATI Ex. 2015
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`IPR2023-00922
`Page 4 of 16
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`
`
`Orlando HW Staff by Programs
`
`
`Hardware Resources by Architecture
`
`BAVAwe
`R300
`
`NY
`@ Orlando Site Established on
`April 19, 1999 with 8
`persons
`@
`1% Generation (R100)
`Transform / Clipping /
`Lighting Engine
`
`Graph Includes Hardware,
`Software, & Validation
`
`Includesall Derivative
`Programs from Base
`Architecture
`
`NOTE:
`e@AUELG)
`Faget.
`eu
`Fito b]
`RI7OO
`
`
` e]
`@ Site / Admin
`
`4
`s
`$
`SPS”
`§
`SPSS SSS 9
`SF EK KC Kore KK oS s¥
`
`4y
`
`B Driver Devel & QA
`BHW Devel
`OHW Validation (Dedicated)
`© Architects
`
`
`
`Staff(heads)
`
`5
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0050927
`
`ATI Ex. 2015
`IPR2023-00922
`Page 5 of 16
`
`ATI Ex. 2015
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`IPR2023-00922
`Page 5 of 16
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`
`
`Orlando Software Break-Out
`
`Siaif(Heads
`
`BR100 SW x
`
`ARISOBERDD PTERRNOBT SESE LAI NY LEESON TAL rerun
`BR400 SW
`OR300 SW
`OUnified Driver
`
`@R200 SW
`
`wu
`SY
`SY
`~
`=
`Seer se ee SS Pee Ss ss s
`
`
`
`
`Orlando Software Team responsible for
`Vertex Processing Functionality in
`RADEON™ Family
`
`Typical Driver development...
`a
`+t year development cycle
`e
`1 year Performance &
`Sustaining support
`
`C
`CONEIDENTIAL
`BAVAwe
`
`BQE
`
`DX Architect
`
`® SW Mgr / OGL Lead
`
`OOGL Vertex Processing
`0 DX Vertex Processing
`
`ATI Corporate Presentation
`
`AMD1044_0050928
`
`ATI Ex. 2015
`IPR2023-00922
`Page 6 of 16
`
`ATI Ex. 2015
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`IPR2023-00922
`Page 6 of 16
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`
`
` Acrchitecture & Design
`
`
`ATI Corporate Presentation
`
`AMD1044_0050929
`
`ATI Ex. 2015
`IPR2023-00922
`Page7 of 16
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`ATI Ex. 2015
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`IPR2023-00922
`Page 7 of 16
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`
`
`BAVAwe Architecture Development Process
`
`
`CONEIDENTIAL
`
`@ Requirements
`9 Marketing/Customer/API inputs
`e
`(Cost, Performance, Features, & Schedule)
`@ Available Technologies and limitations
`@ Concept
`@ High level simulation (proof of concept and performancevalidation)
`@ Block level diagrams/ interface descriptions etc.
`@ Final Process and Cell Library selections
`9 Coarsesize estimates
`@ Detailed development
`2 Specification (Register Specification, Interface Definition, Block Diagrams,
`algorithm development & description)
`@ C/C++ Simulation (Detailed Simulation)
`e Algorithmic code to start simulations for driver development, verification of
`requirements, and hardwaredefinition
`e Transaction based bit precise code for hardwareverification
`e
`Interface & Random vector dumpsfor RTLtesting at all levels
`@ Test Plan
`
`e Tests developmentto verify feature & performance requirements
`
`ATI Corporate Presentation
`
`AMD1044_0050930
`
`ATI Ex. 2015
`IPR2023-00922
`Page 8 of 16
`
`ATI Ex. 2015
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`IPR2023-00922
`Page 8 of 16
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`
`
`BAVAwe Hardware Development Process
`
`
`9
`CONEIDENTIAL
`
`@ RTL (verilog/module compiler)
`@ Conceptual design
`e
`Identify timing critical circuits for early evaluation/modeling
`@ Look for reuse of previous hardware (minimize risk and schedule)
`@ Setup of environment for design, compilation, test, synthesis, and
`configuration management
`@ Major Block Partitioning, Team assignments, and Development
`» Complexity and schedule used to identify required resources
`@ Team approach, keepit simple, brainstorm ideas for best solution
`@ Strive for parallelization (minimize schedule, prevent single point
`failures, fast closure)
`e@ Sub block partitioning and coding
`— RTL code developmentwith test bench
`— Sub unit level validation (hand or C-Sim dumps)
`Block level development and test benchesin parallel
`Block level validation against C-Sim
`Block level random testing
`Test bench injectors and checkers modular for maximal reuse
`Code Coverage tools used to improve test at block level
`
`e@¢¢@@@
`
`ATI Corporate Presentation
`
`AMD1044_0050931
`
`ATI Ex. 2015
`IPR2023-00922
`Page 9 of 16
`
`ATI Ex. 2015
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`IPR2023-00922
`Page 9 of 16
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`
`
`
`
`
`oe
`CONEIDENTIAL
`BAVAwe
`
`“ee
`
`Hardware DevelopmentProcess (Cont'd)
`@ Subsystem and Full Chip integration. of Blocks...
`@ Major subsystem integration - such as graphics pipe
`e@ Test benches with csim validation (functional, random, and
`stress test. Also reuse components and tests from lowerlevel
`testing)
`@ Insertions of real memories, memory test logic, debug logic,
`performance monitoring circuits, power management
`enhancements, BIST, Scan Chains etc.
`@ Configuration testing
`@ Synthesis & Timing Closure
`e@ Port synthesis scripts for consistent/repeatable results.
`@ Perform synthesis w/feedback to designer for solutions
`@ Post P&R Timing Closure
`@ PD and Designersplan block and chip floor plans
`@ Reviews held early and often to identify problem areas
`@ RTLcode changes & re-synthesis for major issues
`3 Scripting language and in-housetools to simplify and document
`eco process
`
`ATI Corporate Presentation
`
`AMD1044_0050932
`
`ATI Ex. 2015
`IPR2023-00922
`Page 10 of 16
`
`ATI Ex. 2015
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`IPR2023-00922
`Page 10 of 16
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`
`
` -& Tools
`
`
`Validation
`
`ATI Corporate Presentation
`
`AMD1044_0050933
`
`ATI Ex. 2015
`IPR2023-00922
`Page 11 of 16
`
`ATI Ex. 2015
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`IPR2023-00922
`Page 11 of 16
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`
`
`Hardware Validation Process
`
`@ Regressions — Nightly Builds and Regressions
`@ Hardware — Sanity and Functional tests are run nightly
`against current RTL code. A set of tests are regressed
`nightly on the following test benches:
`e Block — All test cases regressed
`e GC-Most test cases regressed
`e Chip — Subsetof test cases are regressed
`@ Emulator — Sanity and all Functional tests are run and
`compared against a golden file set
`e All designers must pass ‘sanity’ regressions prior to
`submitting emulator changes to depot
`e Emulator builds checked regularly against golden setoffiles
`for full test suite
`
`BAVAwe
`
`
`re
`CONEIDENTIAL
`
`e@ Reports generated for both Hardware and Emulator
`regressions are created and posted on web site
`
`ATI Corporate Presentation
`
`AMD1044_0050934
`
`ATI Ex. 2015
`IPR2023-00922
`Page 12 of 16
`
`ATI Ex. 2015
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`IPR2023-00922
`Page 12 of 16
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`
`
`BAVAwe
`
`
`13
`CONEIDENTIAL
`
`Hardware Validation Process
`(continued)
`
`@ Test Suite Development
`@ Libraries developed for ease of test development
`@ Test cases are compiled C++files that are linked into emulator as a
`dynamiclinked library
`@ All C++ tests can be run on both block and chip level
`2 Post Net-List Validation — Chris Gray
`@ Gate level simulation — RTL test benches also support gate level
`simulations
`@ Block — test suite run on block gate netlist
`@ Chip— Build environment supports any combination of RTL and gate level
`netlists. Full chip RTL simulation performed on post P&R netlist
`@ FormalVerification
`@ RTL to Synthesis check
`e All post synthesis changesto netlist are comparedfor equality
`e Used in ECOflow for both base layer and metal layer ecos
`@ IKOS used to accelerated simulations
`e Supports driver development pre-silicon
`e Testbed for highly stressful / complicated test cases
`e@
`Further validation of netlist
`
`ATI Corporate Presentation
`
`AMD1044_0050935
`
`ATI Ex. 2015
`IPR2023-00922
`Page 13 of 16
`
`ATI Ex. 2015
`
`IPR2023-00922
`Page 13 of 16
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`
`
`BAVAwe ©eoemUm8WmUmUMOUCUGSMUUCUCUOUCMOMUCUCUMOOWUCUOUCOMUCh}MhUhSHUHhCU!}O
`
`
`aC
`CONEIDENTIAL
`
`DevelopmentTools
`
`Microsoft Developer Visual Studio
`Perforce for cross platform configuration management
`Synopsys Design Compiler
`Synopsys Module Compiler
`Synopsys Physical Compiler
`In house Scripts to drive all synthesis
`In house Scripts to manage all levels of regressions
`In house tools to support PD
`LSF to manage compute resources
`Virage Compiler for memory models
`Leda RTL syntax checking
`ncSim (Cadence) / vcs (Synopsys) Simulation tools
`nWave (Debussy) waveform editor
`Code Coveragetools
`Formal Verification Tool (Formality / Verplex)
`Synopsys primetime
`
`ATI Corporate Presentation
`
`AMD1044_0050936
`
`ATI Ex. 2015
`IPR2023-00922
`Page 14 of 16
`
`ATI Ex. 2015
`
`IPR2023-00922
`Page 14 of 16
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`
`
` op Level Schedule
`
`
`ATI Corporate Presentation
`
`AMD1044_0050937
`
`ATI Ex. 2015
`IPR2023-00922
`Page 15 of 16
`
`ATI Ex. 2015
`
`IPR2023-00922
`Page 15 of 16
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`
`
`Top Level Schedule,
`
`)
`
`ee
`
`BAVAwe
`
`
`ah)
`CONEIDENTIAL
`
`ATI Corporate Presentation
`
`AMD1044_0050938
`
`ATI Ex. 2015
`IPR2023-00922
`Page 16 of 16
`
`ATI Ex. 2015
`
`IPR2023-00922
`Page 16 of 16
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`
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