UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_______________
`REALTEK SEMICONDUCTOR CORP.,
`
`and
`TCL INDUSTRIES HOLDINGS CO., INC.
`
`Petitioner
`
`v.
`
`ATI TECHNOLOGIES ULC
`Patent Owner
`_______________
`Case No.: IPR2023-00922
`
`U.S. Patent No. 8,760,4541
`Issue Date: June 24, 2014
`Title: Graphics Processing Architecture Employing a Unified Shader
`_______________
`
`DECLARATION OF HANSPETER PFISTER, PH.D. IN SUPPORT OF
`PETITIONER’S REPLY TO PATENT OWNER’S RESPONSE TO
`PETITION IN THE INTER PARTES REVIEW OF U.S. PATENT NO.
`8,760,454
`
`1 Joinder with IPR2024-00366
`
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`

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`TABLE OF CONTENTS
`
`Page
`
`I.
`II.
`
`B.
`
`C.
`
`INTRODUCTION .......................................................................................... 1
`CLAIMS 1-11 ARE UNPATENTABLE AS BEING OBVIOUS
`OVER LINDHOLM ’685 PATENT AND LINDHOLM ‘913
`PATENT ......................................................................................................... 1
`A.
`ATI Adds Limitations to Claims 1, 3, 4, and 5 That Are Not
`Required ............................................................................................... 1
`1.
`The ‘454 patent does not require an “evaluation” of
`available storage space. .............................................................. 2
`Lindholm describes a thread prioritization scheme based
`on available storage space to store source data. ........................ 5
`Lindholm discloses a Resource Scoreboard that keeps
`track of incoming data by monitoring the status of source
`registers in the Register File. ..................................................... 7
`Lindholm explicitly discloses vertex and pixel operations
`based on the availability of data at the input buffer. .................. 8
`The Lindholm ’685 and ’913 Patents Disclose A Processor Unit
`That Performs Vertex Manipulation Operations and Pixel
`Manipulation Operations At Various Degrees Of Completion
`Based On Switching Between Instructions In The Instruction
`Store As Seen In Claim 11. .................................................................. 9
`1.
`Claim 11 does not require switching between
`“unfinished” vertex and pixel operations. .................................. 9
`Lindholm discloses a multithreaded unified shader,
`including the ability to switch between pixel and vertex
`operations. ................................................................................ 12
`Lindholm discloses an embodiment of switching between
`operations of different types at various degrees of
`completion. ............................................................................... 15
`The Lindholm ’685 and ’913 Patents Disclose Execution of
`Instructions “In Response to” Receiving Selected Data (Claim
`2) ......................................................................................................... 17
`
`2.
`
`3.
`
`4.
`
`2.
`
`3.
`
`-i-
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`1.
`
`2.
`
`3.
`
`D.
`
`E.
`
`ATIs interpretation of “in response to selected data from
`the general purpose register” is not supported by the
`evidence and goes counter to common usage by a
`POSITA. ................................................................................... 18
`Lindholm demonstrates the execution of operations “in
`response to selected data from the general purpose
`register” (Claim 2). .................................................................. 22
`ATIs distinction between “data during processing” vs.
`“data that is to be processed” is not supported by the
`evidence. .................................................................................. 25
`The Lindholm ’685 and ’913 Patents Disclose “Memory”
`Separate From the “Store” (Claim 6) ................................................. 26
`1.
`Lindholm discloses a sequencer connected to “memory”
`that is separate from the “store.” .............................................. 26
`The Lindholm ’685 and ’913 Patents Disclose a “Control
`Signal” (Claims 7, 10) and “Arbiter” (Claim 10) .............................. 30
`1.
`“Thread entries,” “state data,” or “priority” are control
`signals. ...................................................................................... 30
`Lindholm discloses the claimed “control signal” and
`“arbiter.” ................................................................................... 31
`ATI is confused by the common understanding of the
`term “information.” .................................................................. 33
`III. Ground #2: Claims 1-11 based on the Combination of Amanatides and
`Kohn .............................................................................................................. 35
`A.
`The Amantides + Kohn Patents Determine Which Data To
`Process By Evaluating Storage Capacity As Seen In Claims 1,
`3, 4, and 5. .......................................................................................... 35
`1.
`The ‘454 patent does not require an “evaluation” of
`available storage space. ............................................................ 35
`Amanatides + Kohn disclose a priority scheme for
`processing pixel and vertex data that is based on storage
`capacity. ................................................................................... 36
`
`2.
`
`3.
`
`2.
`
`-ii-
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`3.
`
`4.
`
`5.
`
`Amanatides + Kohn disclose processing of pixel and
`vertex data based on the availability of shared resources. ....... 39
`The ID correctly identified the priority scheme in
`Amanatides + Kohn as disclosing processing of pixel and
`vertex data based on the availability of shared resources. ....... 41
`ATI falsely imbues intelligent behavior to the graphics
`processing system of Amanatides. ........................................... 45
`The Amantides + Kohn Patents Disclose A Processor Unit That
`Performs Vertex Manipulation Operations And Pixel
`Manipulation Operations At Various Degrees Of Completion
`Based On Switching Between Instructions In The Instruction
`Store (Claim 11). ................................................................................ 45
`1.
`Kohn discloses operations “at various degrees of
`completion based on switching between 30 instructions
`in the instruction store.” ........................................................... 46
`A POSITA would be motivated to combine Amanatides
`+ Kohn. ..................................................................................... 48
`Amantides + Kohn Disclose “Selected Data” (claims 2 and 5) ......... 49
`1.
`Amanatides does not impose any temporal restrictions of
`the processing of GM and RM packets. ................................... 50
`Reading data from FIFOs in Amanatides is “selecting
`data” from a data store. ............................................................ 52
`Claims 7 and 10 do not require that the “Selection
`Circuit” is within the processor of the “Unified Shader”. ....... 54
`Amanatides and Kohn include the “Selection Circuit”
`within the “Unified Shader” as required by claims 7 and
`10. ............................................................................................. 55
`Amantides + Kohn Disclose a “Control Signal” (claims 7 and
`10) ....................................................................................................... 57
`1.
`Packets in Amanatides and Kohn include a priority. ............... 57
`2.
`ATI is relies on colloquial sources and non-technical
`terminology. ............................................................................. 59
`
`2.
`
`2.
`
`3.
`
`4.
`
`-iii-
`
`B.
`
`C.
`
`D.
`
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`E.
`
`2.
`
`3.
`
`Amantides + Kohn Disclose a “Selection Circuit” and
`“Arbiter,” (claim 10) .......................................................................... 60
`1.
`ATI fails to understand the basic circuits of FIFOs and
`buses. ........................................................................................ 60
`Packets in Amanatides are sent from FIFOs over the bus
`to DRAM, VRAM, and the on-chip cache. ............................. 62
`The “control signal” in Amanatides prompts information
`to be transmitted and stored. .................................................... 64
`Claim 10 does not require specific timing for arbitration........ 65
`4.
`IV. Ground #3: Claims 1-11 based on the Combination of Selzer and
`Fiske .............................................................................................................. 67
`A.
`The Selzer + Fiske Patents Determine Which Data To Process
`By Evaluating Storage Capacity As Seen In Claims 1, 3, 4, and
`5. ......................................................................................................... 67
`1.
`The ‘454 patent does not require an “evaluation” of
`available storage space. ............................................................ 67
`Selzer discloses processing of pixel and vertex data based
`on storage capacity. .................................................................. 67
`Fiske’s hardware context switch discloses processing of
`pixel and vertex data based on storage capacity. ..................... 71
`Claim 1 in the ‘454 patent does not impose timing
`constraints or ordering on the processing of vertex and
`pixel data. ................................................................................. 73
`Selzer + Fiske do not impose any timing constraints on
`the processing of vertex and pixel data. ................................... 76
`Selzer + Fiske discloses performing pixel calculation
`operations and then vertex calculation operations based
`on resources and vice versa (claims 3 + 4). ............................. 78
`Selzer + Fiske Disclose A Processor Unit That Performs Vertex
`Manipulation Operations And Pixel Manipulation Operations
`At Various Degrees Of Completion Based On Switching
`Between Instructions In The Instruction Store (Claim 11). ............... 81
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`B.
`
`-iv-
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`Fiske discloses performing operations “at various degrees
`of completion based on switching between instructions in
`the instruction store.” ............................................................... 82
`The combination of Selzer and Fiske discloses claim 11. ....... 83
`There is motivation to combine Selzer and Fiske for fast
`multithreaded graphics processing. .......................................... 84
`Selzer + Fiske disclose switching between incomplete
`instruction in the instruction store. .......................................... 85
`Selzer + Fiske Disclose Execution of Instructions “In Response
`to” Receiving Selected Data (Claim 2). ............................................. 87
`1.
`ATIs interpretation of “in response to selected data from
`the general purpose register” is not supported by the
`evidence and goes counter to common usage by a
`POSITA. ................................................................................... 87
`Selzer demonstrates the execution of operations “in
`response to selected data from the general purpose
`register” (Claim 2). .................................................................. 87
`Fiske demonstrates the execution of operations “in
`response to selected data from the general purpose
`register” (Claim 2). .................................................................. 90
`Selzer + Fiske Disclose the “Sequencer,” “Instruction Store,”
`“Circuitry,” “Selection Circuit,” and “Arbiter” Within the
`“Unified Shader” As Required (Claims 2, 5-7, 10, 11). .................... 91
`1.
`Selzer’s “Master Module” discloses a “Sequencer” and
`“Circuitry” (claims 2, 5, and 6) ................................................ 92
`Selzer + Fiske Disclose a “Selection Circuit” and
`“Arbiter” (claims 7 and 10) ...................................................... 95
`The “Sequencer” And “Instruction Store” in Selzer Maintain
`Instructions (Claims 2, 5, and 11) ...................................................... 96
`Selzer + Fiske Disclose the “Arbiter” (Claim 10) and “Control
`Signal” (Claims 7, 10) ........................................................................ 98
`G. Motivation to Combine Selzer + Fiske .............................................. 99
`
`C.
`
`D.
`
`E.
`
`F.
`
`1.
`
`2.
`3.
`
`4.
`
`2.
`
`3.
`
`2.
`
`-v-
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`TABLE OF CONTENTS
`(continued)
`
`Page
`
`1.
`
`2.
`
`3.
`
`Both Fiske and Selzer adapt the activities of the
`processing units to the actual processing requirements ........... 99
`The multithreading in Fiske improves the performance of
`rendering calculations in Selzer ............................................. 100
`Task switching in Selzer is not the same as
`multithreading in Fiske, but it helps motivate the
`combination of Selzer + Fiske ............................................... 102
`Combining Selzer and Fiske would be obvious and easy
`for a POSITA. ........................................................................ 104
`Secondary Considerations ................................................................ 105
`H.
`DECLARATION ........................................................................................ 107
`
`4.
`
`V.
`
`-vi-
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`
`I.
`
`INTRODUCTION
`1.
`I was asked to provide this declaration containing my rebuttal
`
`opinions and analysis to issues raised in Dr. Mangione-Smith’s declaration dated
`
`February 23, 2024 and the corresponding Patent Owner Response (POR or
`
`Response) to which it alleges to support. Having carefully read and evaluated all
`
`of the issues raised in those documents, it is clear that my opinions are confirmed
`
`and claims 1-11 of the ʼ454 patent are unpatentable.
`
`II.
`
`CLAIMS 1-11 ARE UNPATENTABLE AS BEING OBVIOUS OVER
`LINDHOLM ’685 PATENT AND LINDHOLM ‘913 PATENT
`A.
`ATI Adds Limitations to Claims 1, 3, 4, and 5 That Are Not
`Required
`ATI argues that Lindholm does not disclose “Executing Operations
`
`2.
`
`Depending Upon an Amount Of Space Available In The Store (Claim 5), Much
`
`Less Performing Vertex Operations Or Pixel Operations Until Enough Storage Is
`
`Available For The Other Operation Type (Claims 1, 3, 4)” Response Sec. 2, p. 29.
`
`3.
`
`In support, ATI argues that the Lindholm patents are not “evaluating
`
`available storage space for incoming data, much less doing so to determine what to
`
`execute.” Response p. 31. As shown in the Petition and below, ATI is incorrect on
`
`every point.
`
`1
`
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`1.
`
`The ‘454 patent does not require an “evaluation” of
`available storage space.
`In their response, ATI incorrectly use the term “evaluating” available
`
`4.
`
`storage space, which does not appear in the ‘454 patent. “The ’454 Patent’s
`
`Unified Shader Determines Which Data To Process By Evaluating Storage
`
`Capacity As Seen In Claims 1, 3-10”, Sec. III A. The ‘454 patent claims and
`
`description do not use the terms ‘evaluating’ or ‘evaluation’ or ‘determine’ or
`
`‘determination’ in conjunction with storage space. Instead, the claims require the
`
`ability to store data in registers that are free or available. There is no need for any
`
`“evaluating” of free storage space, nor do the claims and patent description of the
`
`‘454 patent mention any “evaluating” or “evaluation” of storage space. For
`
`example, a first-in, first-out (FIFO) memory allows new data to be stored without
`
`first “evaluating” whether there is available space. If the FIFO is full, i.e., has no
`
`more free storage space, its circuitry overwrites the oldest entry in its registers with
`
`new incoming data. The embodiment of storage space as a FIFO is entirely within
`
`the scope and claims of the ‘454 patent. To the extent any evaluation steps is done
`
`with respect to the available space, it is done by the arbiter, which is not part of the
`
`claimed unified shader in the ’454 patent. As shown in Figure 4A and described in
`
`the ’454 patent specification, the arbiter is a stand-alone component at least one
`
`component (MUX) removed from the unified shader. However, all of the ’454
`
`2
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`patent claims are directed specifically to the unified shader, e.g., claim 1 – “A
`
`method carried out by a unified shader comprising,” claim 2-5, 11 – “A unified
`
`shader comprising.” Further, the only “determination” made based on that
`
`“evaluation” or “consideration” of available space is also done by the arbiter when
`
`it determines what vertex or pixel data to transmit to the general purpose register
`
`block 92 via the MUX 66. Ex. 1001, 5:41-44. The unified shader of the ’454
`
`patent has no such evaluation or determination functionality and, instead, merely
`
`operates on the information passed to the general purpose register block via the
`
`multiplexer.
`
`5.
`
`In my opinion, he argument by ATI that the claims require
`
`“considerations for determining what to process” is false. Response p. 31 a
`
`POSITA would not understand there to be any “determining” or “determination” in
`
`the ‘454 patent concerning what to process or concerning storage space carried out
`
`by the claimed unified shader. Similarly, ATI’s statement that Lindholm does not
`
`“disclose the required evaluation of available storage space for incoming data to
`
`determine what to execute” also reads false requirements into the claims.
`
`“Evaluation” of available storage space is not required by the unified shader,
`
`especially not in conjunction with determining what to execute.
`
`3
`
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`6.
`
`Claim 1 of the ‘454 patent requires performing vertex operations
`
`“unless the general purpose register block does not have enough available space
`
`therein to store incoming vertex data.” It also requires continuing pixel calculation
`
`operations “until enough registers within the general purpose register block
`
`become available.” The patent claim refers to the availability of storage space and
`
`does not require an “evaluation” of the storage space.
`
`7.
`
`Claim 3 of the ‘454 patent requires performing pixel calculation
`
`operations “until enough shared resources become available and then use the
`
`shared resources to perform vertex calculation operations.” No “evaluation” of
`
`shared resources is required in the claim. In addition, shared resources could refer
`
`to storage, arithmetic-logic units (ALUs), or other computational units.
`
`8.
`
`Claim 4 of the ‘454 patent requires the execution of vertex calculation
`
`operations “until enough shared resources become available and then use the
`
`shared resources to perform pixel calculation operations.” No “evaluation” of
`
`shared resources is required in the claim. In addition, shared resources could refer
`
`to storage, arithmetic-logic units (ALUs), or other computational units.
`
`9.
`
`Claim 5 of the ‘454 patent requires the execution of pixel and vertex
`
`calculation operations “depending upon an amount of space available in the store,”
`
`where the term “store” refers to data storage. No “evaluation” of storage space is
`
`4
`
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`required in the claim. Thus, a POSITA would not consider or understand these
`
`claims to require any “evaluation” or “determination” steps that ATI is attempting
`
`to create.
`
`2.
`
`Lindholm describes a thread prioritization scheme based on
`available storage space to store source data.
`10. ATI claims: “For example, prioritizing based on how much data is in
`
`the buffers doesn’t disclose the requirement of claim 1 to perform vertex
`
`operations until there is no space for new incoming vertex data, in which case
`
`performing only pixel calculations until there is once again room for new vertex
`
`data.” Response at p. 32. In my opinion, ATI is wrong for several reasons.
`
`Performing vertex or pixel operations based on the available storage space is a
`
`form of prioritization. Vertex or pixel operations get priority, i.e., executed,
`
`depending on the available storage space.
`
`11.
`
`Lindholm discloses such a prioritization scheme based on available
`
`storage space, including storage in the vertex and pixel input buffers. The ID
`
`correctly found that this element is met because “Lindholm ’685 discloses
`
`determining thread execution priority based on the amount of sample data in the
`
`pixel and vertex input buffers and recognizes that the maximum number of threads
`
`that can be executed simultaneously depends on the size of storage for thread state
`
`data.” ID, 40-41.
`
`5
`
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`12. Moreover, even taking ATI’s wrong limitations into account,
`
`Lindholm discloses all of the elements in claims 1, 3, 4, and 5. The ’685 patent
`
`uses a complex arbitration scheme in the Instruction Cache and Instruction
`
`Scheduler in order to select which instructions from the available threads will be
`
`processed based on the available data. These units can select “any instruction
`
`within the IWU 435 [to] be executed based on the availability of computation
`
`resources in an Execution Unit 470 and source data stored in Register File 350.”
`
`Ex. 1005 at 7:56-64; 8:47-64. (emphasis added) Thus, the ’685 patent employs
`
`arbitration at the data level based on the “availabil of “source data stored in
`
`Register File 350.” This indicates to a POSITA that there must be available
`
`storage space in Register File 350 to store source data. In other words, it is obvious
`
`that the instruction is only being executed if there is space to store source data.
`
`13.
`
`If a particular program instruction specifies available source data, the
`
`scheduler will schedule that program instruction to be executed, because doing so
`
`would not stall the system. Id. at 8:49-53. If the specified source data is not
`
`available, the scheduler will instead schedule a different thread’s program
`
`instruction for execution. See id. (emphasis added) In short, the scheduler bases
`
`its decision to execute a particular program instruction based on the availability of
`
`source data specified by that instruction. Id. at 8:49-53; 17:41-44. Program
`
`6
`
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`execution is conducted on an instruction-by-instruction basis, and the scheduler
`
`switches at will between instructions and threads of various sample types. Id. at
`
`17:41-44.
`
`3.
`
`Lindholm discloses a Resource Scoreboard that keeps track
`of incoming data by monitoring the status of source
`registers in the Register File.
`Lindholm also disclosed a way to track storage space using a
`
`14.
`
`Resource Scoreboard. The Resource Scoreboard tracks the status of source
`
`registers scheduled to be written during processing (i.e., destination registers).
`
`These registers are marked as “write pending.” When a write operation is
`
`completed, and the data in the destination register becomes available for use as
`
`source data, the Resource Scoreboard indicates this change. Ex. 1005, 8:58-65 In
`
`some embodiments, the Resource Scoreboard snoops (i.e., observes) the interface
`
`between the Execution Unit 470 and Register File 350 to monitor incoming data.
`
`Id., 9:53-56
`
`15.
`
`The Resource Scoreboard uses the location of each program
`
`instruction’s required source data to track whether that data is available for
`
`processing vertex or pixel threads, as well as whether the necessary computational
`
`resources are available. Id. at 8:58-60; 9:2-4, 16:53-54, 17:45-46. The scheduler
`
`uses this information from the resource scoreboard to determine which program
`
`7
`
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`instructions have their source data available, and consequently, which program
`
`instructions to schedule for execution. See, e.g., Ex. 1003 at 14:20-30.
`
`16. Once the program instructions have been scheduled for execution, a
`
`third component, the instruction dispatcher, gathers the specified source data and
`
`scheduled instructions and outputs them to the execution unit so that the
`
`corresponding sample may be processed. Id. at 9:40-42; 16:55-57; 17:47-50. This
`
`completes the processing operation.
`
`4.
`
`Lindholm explicitly discloses vertex and pixel operations
`based on the availability of data at the input buffer.
`17. ATI claims that Lindholm does not disclose “evaluating available
`
`storage space for incoming data, much less doing so to determine what to execute.”
`
`Response at p. 31. This is false, as can be seen with direct quotes from the ‘685
`
`patent: “Each Execution Pipeline 240 signals to Vertex Input Buffer 220 when a
`
`sample can be accepted or when a sample cannot be accepted.” Ex. 1005 at 4:34-
`
`36 “Each Execution Pipeline 240 signals to Pixel Input Buffer 240 when a sample
`
`can be accepted or when a sample cannot be accepted as described further herein.”
`
`Ex. 1005 at 5:24-26.
`
`18. Accordingly, the undisputed evidence establishes that Lindholm
`
`discloses executing operations depending upon the amount of space available in
`
`the store (Claim 5) and performing vertex operations or pixel operations until
`
`8
`
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`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`enough storage is available for the other operation type (Claims 1, 3, 4). At a
`
`minimum, all of these disclosures render these claims obvious.
`
`B.
`
`19.
`
`The Lindholm ’685 and ’913 Patents Disclose A Processor Unit
`That Performs Vertex Manipulation Operations and Pixel
`Manipulation Operations At Various Degrees Of Completion
`Based On Switching Between Instructions In The Instruction
`Store As Seen In Claim 11.
`Petitioner and ATI agree that Lindholm discloses a unified shader
`
`(processor unit) to execute pixel or vertex operations. However, ATI wrongly
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`claims that Lindholm does not disclose that the processor can switch between
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`“unfinished vertex operations and pixel operations,” as required by claim 11. In my
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`opinion, this is false.
`
`1.
`
`Claim 11 does not require switching between “unfinished”
`vertex and pixel operations.
`First, the ‘454 patent and claim 11 do not specify the timing of vertex
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`20.
`
`and pixel operations. They could happen sequentially, without overlap in time, or
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`simultaneously, at the same time. Switching between pixel or vertex operations
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`could occur while these operations are executed sequentially or simultaneously.
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`ATI does not dispute and agrees with the Petitioner that Lindholm discloses a
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`processor capable of switching between pixel and vertex operations based on
`
`instructions in the instruction store.
`
`9
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`Realtek Ex. 1018, Page 16
`Realtek Semiconductor Corp. v. ATI Technologies ULC
`IPR2023-00922
`
`

`

`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`21. Claim 11 requires that the vertex and pixel operations related to the
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`instructions are “at various degrees of completion.” This includes operations that
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`have just started, are in process, or have finished. It is not, as ATI claims, only a
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`“switch between unfinished vertex operations and pixel operations.” Response p.
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`32. (emphasis added) The ATI term “unfinished,” which excludes switching
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`between completed operations, differs from the claim term “at various degrees of
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`completion,” which includes switching between finished operations.
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`22. ATI incorrectly states that I agreed this claim “requires the processor
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`unit to switch between unfinished vertex operations and pixel operations.”
`
`Response 32. The question asked of me was an unrealistic and incomplete
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`hypothetical in which I had to make several assumptions to try and answer.
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`Initially I was asked to assume “full completion,” which was a fuzzy concept,
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`which I indicated was not a concept I had considered. Ex. 2123, 60:5-61:1. Mr.
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`Dokyanchy implied I should assume that “full completion” and “completion”
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`(which is what is recited in the claim) were the same by stating he “was just using
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`the claim language.” Id., 61:5-6. I do not agree that “completion” in the claim
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`means “full completion.” I was then asked to assume “there are definite
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`boundaries of when an operation begins and when an operation ends.” Id. 61:7-10.
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`Next, I was asked to assume that two “operations” (1 and 2) had a “defined
`
`10
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`Realtek Ex. 1018, Page 17
`Realtek Semiconductor Corp. v. ATI Technologies ULC
`IPR2023-00922
`
`

`

`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`boundary.” Id., 61:13-14. It was not clear if the “defined boundary” for each
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`operation was meant to include the previous assumption of beginning and end. No
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`other details were provided about whatever assumed system or unified shader
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`might be carrying out the hypothetical operations. Then I was asked to answer the
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`questions “would it meet the claim language if the switch between operation 1 and
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`operation 2 was after operation 1 was completed?” Id., 61:16-18. No details were
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`provided about switching, what switching meant, if I was supposed to assume a
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`switch as claimed, how many other switches are made, etc., other than the
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`question. The question implies a single switch between operation 1 and 2. I
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`assumed there must be at least one other switch because the claim requires
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`“various” degrees of completion, which to a POSITA means there must be at least
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`two. The only switch I was given to assume in the question was a switch after
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`operation 1 was complete. Id., 61:16-18. Because after completion of operation 1
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`the only operation left is operation 2, there could never be a second switch. So, to
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`satisfy the claim language, if there are only two operations, the only way to get
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`“various degrees of completion” would be to have a switch before completing
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`operation 1. That would leave some operations left (e.g., to come back and finish
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`operation 1, or to execute some or all of operation 2) where a second switch could
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`take place to satisfy the “various” and/or plural requirement of the claims.
`
`11
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`Realtek Ex. 1018, Page 18
`Realtek Semiconductor Corp. v. ATI Technologies ULC
`IPR2023-00922
`
`

`

`Patent No. 8,760,454
`Petition for Inter Partes Review
`Ex. 1018 – Declaration of Dr. Hanspeter Pfister
`
`However, if you have more than two operations, you can have switches where the
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`switch occurs after completion and still satisfy the claim language. Furthermore, if
`
`these operations do not have to be finished, as was assumed in the question by
`
`adding that “completion” implied “full completion” to the hypothetical, then the
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`operations could have just started, be in process, or have finished. Nothing in claim
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`11 or the ‘454 patent requires switching between “unfinished” or “fully completed”
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`vertex and pixel operations. All possible timings of vertex and pixel operations are
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`within the limitations of claim 11 as long as they are “at various degrees of
`
`completion.”
`
`2.
`
`Lindholm discloses a multithreaded unified shader,
`includin