`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`_________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_________________________
`
`REALTEK SEMICONDUCTOR CORP.,
`Petitioner,
`v.
`ATI TECHNOLOGIES ULC
`Patent Owner.
`_________________________
`Case No. IPR2023-00922
`U.S. Patent No. 8,760,454
`_________________________
`
`DECLARATION OF DR. WILLIAM MANGIONE-SMITH
`REGARDING U.S. PATENT NO. 8,760,454
`
`
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`
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`ATI Ex. No 2121
`IPR2023-00922
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`TABLE OF CONTENTS
`
`I.
`II.
`
`B.
`
`C.
`
`Page
`INTRODUCTION ........................................................................................... 1
`SUMMARY OF CONCLUSIONS ................................................................. 2
`A.
`Summary of Conclusions Regarding Reduction to Practice,
`Conception, and Diligence .................................................................... 2
`Summary of Conclusions Regarding Validity ...................................... 3
`B.
`III. EXPERT QUALIFICATIONS ........................................................................ 3
`IV. HIGH LEVEL GRAPHICS PROCESSING OVERVIEW ............................. 7
`A. Graphics Processors Use Vertex and Pixel Data to Create
`Display Images ...................................................................................... 7
`Graphics Processors Use Instruction “Threads” To Transform
`Vertex and Pixel Data.......................................................................... 10
`Conventional Graphics Processors Executed Vertex And Pixel
`Threads Using Separate Vertex Shaders And Pixel Shaders .............. 11
`V. OVERVIEW OF THE ’454 PATENT .......................................................... 14
`A.
`The ’454 Patent’s Unified Shader ....................................................... 15
`B.
`The ’454 Patent’s Unified Shader Determines Which Data to
`Process by Evaluating Storage Capacity and Additional
`Analyses As Seen In Claims 1, 3-10 ................................................... 16
`The Unified Shader Can Simultaneously Execute Vertex and
`Pixel Operations and Switch Quickly Between Operations at
`Various Degrees of Completion As In Claim 11 ................................ 18
`The Invention of the ’454 Patent Triggers Execution by
`Transmitting Data Rather Than Instructions As In Claim 2 ............... 19
`The ’454 Patent’s Challenged Claims ................................................. 20
`E.
`VI. RELEVANT LEGAL STANDARDS ........................................................... 20
`Conception and Reduction to Practice ................................................ 21
`
`Claim Construction ............................................................................. 22
`
`Obviousness ......................................................................................... 23
`
`VII. GENERAL DESIGN AND DEVELOPMENT PROCESS AT AMD ......... 24
`VIII. CONCEPTION .............................................................................................. 28
`’454 Patent ........................................................................................... 30
`
`1.
`Claim 1 ...................................................................................... 30
`
`C.
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`D.
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`Claim 2 ...................................................................................... 41
`Claim 3 ...................................................................................... 58
`Claim 4 ...................................................................................... 65
`Claim 5 ...................................................................................... 73
`Claim 6 ...................................................................................... 83
`Claim 7 ...................................................................................... 85
`Claim 8 ...................................................................................... 90
`Claim 9 ...................................................................................... 93
` Claim 10 .................................................................................... 97
` Claim 11 .................................................................................. 100
`IX. DILIGENCE IN REDUCING TO PRACTICE .......................................... 107
`X.
`CONSTRUCTIVE REDUCTION TO PRACTICE .................................... 151
`’454 Patent ......................................................................................... 153
`
`Claim 1 .................................................................................... 153
`
`Claim 2 .................................................................................... 159
`
`Claim 3 .................................................................................... 170
`
`Claim 4 .................................................................................... 180
`
`Claim 5 .................................................................................... 190
`
`Claim 6 .................................................................................... 195
`
`Claim 7 .................................................................................... 197
`
`Claim 8 .................................................................................... 198
`
`Claim 9 .................................................................................... 199
`
` Claim 10 .................................................................................. 200
` Claim 11 .................................................................................. 201
`XI. NO ABANDONMENT, SUPPRESSION, OR CONCEALMENT OF
`R400 ............................................................................................................. 207
`XII. ASSERTED PRIOR ART ........................................................................... 208
`A.
`Lindholm ’685 ................................................................................... 209
`B.
`Amanatides ........................................................................................ 211
`C.
`Selzer ................................................................................................. 212
`XIII. EVALUATION OF PETITIONER’S PROPOSED GROUNDS ............... 214
`A. Ground 1: Lindholm ’685 and Lindholm ’913 Do Not Render
`the ’454 Patent Obvious .................................................................... 214
`No Executing Operations Depending Upon an Amount Of
`
`Space Available In The Store (Claim 5), Much Less Performing
`Vertex Operations Or Pixel Operations Until Enough Storage Is
`Available For The Other Operation Type (Claims 1, 3, 4) ..... 214
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`B.
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`C.
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`
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`No Execution of Instructions “In Response to” Receiving
`Selected Data (Claim 2) .......................................................... 219
`No “Memory” Separate From the “Store” (Claim 6) ............. 221
`No “Control Signal” (Claim 7) or “Arbiter” (Claim 10) ........ 222
`No Processor Unit That Performs Vertex Manipulation
`Operations and Pixel Manipulation Operations At Various
`Degrees Of Completion Based On Switching Between
`Instructions In The Instruction Store (Claim 11) .................... 223
`Ground 2: Amanatides and Kohn Do Not Render the ’454
`Patent Obvious .................................................................................. 226
`No Executing Operations Depending Upon An Amount Of
`
`Space Available In The Store (Claim 5), Much Less Performing
`Vertex Operations Or Pixel Operations Until Enough Storage Is
`Available For The Other Operation Type (Claims 1, 3, 4) ..... 226
`No Processor Unit That Performs Vertex Manipulation
`Operations And Pixel Manipulation Operations At Various
`Degrees Of Completion Based On Switching Between
`Instructions In The Instruction Store (Claim 11) .................... 234
`No “Selected Data” (Claims 2, 5) ........................................... 237
`Alleged “Selection Circuit” Is Not Within Alleged “Unified
`Shader” As Required (Claims 7, 10) ...................................... 239
`No “Control Signal” (Claims 7, 10) ........................................ 242
`
`No “Selection Circuit” or “Arbiter,” “(Claim 10) .................. 243
`
`Ground 3: Selzer and Fiske Do Not Render the ’454 Patent
`Obvious ............................................................................................. 245
`No Executing Operations Depending Upon An Amount Of
`
`Space Available In The Store (Claim 5), Much Less Performing
`Vertex Operations Or Pixel Operations Until Enough Storage Is
`Available For The Other Operation Type (Claims 1, 3, 4) ..... 246
`No Processor Unit That Performs Vertex Manipulation
`Operations And Pixel Manipulation Operations At Various
`Degrees Of Completion Based On Switching Between
`Instructions In The Instruction Store (Claim 11) .................... 251
`No Execution of Instructions “In Response to” Receiving
`Selected Data (Claim 2) .......................................................... 254
`Alleged “Sequencer,” “Instruction Store,” “Circuitry,”
`“Selection Circuit,” and “Arbiter” Are Not Within Alleged
`“Unified Shader” As Required (Claims 2, 5-7, 10, 11) .......... 256
`Alleged “Sequencer” And “Instruction Store” Do Not Maintain
`Instructions (Claims 2, 5, and 11) ........................................... 258
`
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`C.
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`No “Arbiter” (Claim 10) or “Control Signal” (Claims 7, 10) 260
`No Motivation to Combine Selzer and Fiske and no Reasonable
`Expectation of Success in Doing So ....................................... 261
`XIV. SECONDARY CONSIDERATIONS SUPPORT NON-
`OBVIOUSNESS OF THE ’454 PATENT .................................................. 265
`A.
`Initial Skepticism of ATI’s Unified Shader Technology .................. 267
`B.
`Unexpected Results in Developing the Unified Shader
`Technology ........................................................................................ 272
`The Satisfaction of a Long-Felt Need by the Unified Shader of
`the Xenos GPU and Failed Attempts by Others ............................... 274
`Industry Praise of the Unified Shader in Xbox 360’s Xenos
`GPU ................................................................................................... 276
`Commercial Success of the Xbox 360 Containing ATI’s
`Unified Shader in the Xenos GPU .................................................... 278
`Adoption by Others ........................................................................... 280
`F.
`XV. CONCLUSION ............................................................................................ 281
`
`D.
`
`E.
`
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`TABLE OF ABBREVIATIONS
`
`Abbreviation
`
`Full Description
`
`AMD
`ATI
`GPU
`
`Advanced Micro Devices, Inc.
`ATI Technologies, ULC
`Graphics processing unit
`
`
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`TABLE OF EXHIBITS
`
`1008
`
`1009
`
`Exhibit # Reference Name
`1001
`U.S. Patent 8,760,454 to Morein et al.
`1002
`Prosecution History of U.S. Patent 8,760,454
`1003
`Declaration of Hanspeter Pfister, Ph.D.
`1004
`Curriculum Vitae of Hanspeter Pfister, Ph.D.
`1005
`U.S. Patent 7,038,685 to Lindholm et al. (“Lindholm ’685”)
`1006
`U.S. Patent No. 7,015,913 to Lindholm et al. (“Lindholm ’913”)
`1007
`John Amanatides and Edward Szurkowski, A Simple, Flexible,
`Parallel Graphics Architecture, In Proceedings of Graphics
`Interface at 155-160 (Canadian Information Processing Society
`1993) published in Proc. Graphics Interface ’93 in May 1993
`(“Amanatides”)
`Les Kohn and Neal Margulis, Introducing the Intel i860 64-bit
`Microprocessor, IEEE, Volume 9, Issue 4, pages 15-30, August
`1989 (“Kohn”)
`Harald Selzer, Dynamic Load Balancing within a High
`Performance Graphics System, In Proceedings of Rendering,
`Visualization and Rasterization Hardware (Eurographics' 91
`Workshop) at 37-53 (Springer-Verlag 1993) published in 1993
`(“Selzer”) [Library of Congress]
`Stuart Fiske and William J. Dally, Thread prioritization: A Thread
`Scheduling Mechanism for Multiple-Context Parallel Processors,
`In Proceedings of First Symposium on High-Performance
`Computer Architecture, 1995 at 210-221 (IEEE 1995) published in
`1995 (“Fiske”)
`Harald Selzer, Dynamic Load Balancing within a High
`Performance Graphics System, In Proceedings of Rendering,
`Visualization and Rasterization Hardware (Eurographics' 91
`Workshop) at 37-53 (Springer-Verlag 1993) published in 1993
`(“Selzer”) [University of California, Berkeley, Library]
`EX 2001 Declaration of William Mangione-Smith and CV
`EX 2002
`IPR2015-00325, Declaration of Dr Wolfe, Sept. 9, 2015
`EX 2003
`IPR2015-00325, Declaration of Calvin Watson, Sept. 9, 2015
`EX 2004
`IPR2015-00325, Declaration of Lefebvre, Sept. 9, 2015
`
`1010
`
`1016
`
`ii
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`EX 2007
`
`EX 2006
`
`Exhibit # Reference Name
`EX 2005
`IPR2015-00325,-00326, and-00330, Deposition Transcript of
`Calvin Watson, November 4, 2015
`IPR2015-00325, -00326, and -00330, Deposition Transcript of
`Dr. Wolfe, Nov. 10, 2015
`IPR2015-00325,-00326, and -00330, Deposition Transcript of
`Laurent Lefebvre, Nov.13, 2015
`EX 2008 Gruber et al, R400 Shader Processor 2001, Oct. 9, 2015
`EX 2009 R400 Document Library Folder History, November 1, 2000
`through April 8, 2005
`EX 2010 R400 Sequencer Specification (Version 0 4), August 14, 2001
`EX 2011 R400 Sequencer Specification (Version 2 0), September 24, 2001
`EX 2012 R400 Shader Processor (Version 0 1), Jan. 23, 2001
`EX 2013 R400 Top Level Specification (Version 0 2), March 11, 2001
`EX 2014 R400 Program Logs
`EX 2015 Microsoft Site Visit (Feb. 2003)
`EX 2016
`Log of Exhibits and File Location
`EX 2017 R400 Program Review Documentation (Feb. 2003)
`EX 2018 R400 MM Software Status (Feb. 2003)
`EX 2019 R400 I/O Presentation (Feb. 2003)
`EX 2020 R400 I/O Presentation (Feb. 2003)
`EX 2021 R400 August Program Review
`EX 2022
`Executive Review - R400 (Oct. 2002)
`EX 2023 R400 Area Estimate
`EX 2024 R400 Executive Review (Sept. 2002)
`EX 2025 GFIXIP 9x SX Micro-Architecture Specification
`EX 2026 WD/IA VGT Micro-Architecture Specification
`EX 2027 GX9 SPI Specification
`EX 2028 R400 Top Level Specification (Version 0.2)
`EX 2029 R400 Folder History Log
`EX 2030 R400 Folder History Log
`EX 2031 R400 Folder History Log
`EX 2032 R400 Review PowerPoint
`
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`Exhibit # Reference Name
`EX 2033 R400 Review PowerPoint
`EX 2034 R400 Development and Documentation
`EX 2035 Xenos GFX Change History July 2003 - Dec. 2003 Log
`EX 2036 R400 GFX Change History March 2003 - Dec. 2003
`EX 2037 R400 Primitive Assembly
`EX 2038 R400 Primitive Assembly
`EX 2039 Development Documentation
`EX 2040 Development Documentation
`EX 2041 Development Documentation
`EX 2042 R400 Performance Verification
`EX 2043 Development Documentation
`EX 2044 R400 PAD Program Review (Dec. 2002)
`EX 2045 R400 EMU Test Regress History Log
`EX 2046 R400 EMU Test Regress Statistics Log
`EX 2047 R400 Program Review (Dec. 2002)
`EX 2048 R400 Program Review (Dec. 2002)
`EX 2049 Device Development Progress
`EX 2050 Device Development Progress
`EX 2051 Device Development Progress
`EX 2052 Device Development Progress
`EX 2053 R400 Review Status PowerPoint
`EX 2054
`TV Specification
`EX 2055 R400 Program Review PowerPoint and Test Results
`EX 2056 Development Documentation
`EX 2057 R400 PowerPoint
`EX 2058 R400 Program Review PowerPoint
`EX 2059 R400 Program Review
`EX 2060 Block Development Progress
`EX 2061 R400 Program Review (Dec. 11, 2002)
`EX 2062 R400 Program Review (Dec. 12, 2002)
`EX 2063 Development Documentation
`EX 2064 Development Documentation
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`Exhibit # Reference Name
`EX 2065 Development Documentation
`EX 2066 R400 Technical Documentation
`EX 2067 R400 Technical Documentation
`EX 2068 R400 GFX Change History March 2003 to December 2003 Log
`EX 2069
`Ikos 2002 Spreadsheet
`EX 2070 R400 - Program Review (Oct. 2002)
`EX 2071
`Sqsp Regress Report
`EX 2072 Xenos Sq Change Log
`EX 2073 R400 Regress Testing
`EX 2074 Virtual Logic 3.1 User's Guide
`EX 2075 Virtual Logic 3.5.5 User's Guide
`EX 2076
`IKOS Virtual Logic 2.1
`EX 2077
`IKON Screenshots
`EX 2078
`IKON Screenshots
`EX 2079 GFX9 User's Guide
`EX 2080 US Patent No. 6,897,871
`EX 2081
`Samsung Exynos 5430 Octa SoC
`EX 2082
`Samsung Exynos 3 Quad 3470 Processor Database
`EX 2083 HW Emulator First Triangle
`EX 2084 HW Simulator First Triangle
`EX 2085 R400 Regress Testing Logs
`EX 2086 R400 Regress Testing Logs
`EX 2087 R400 IKOS Status
`EX 2088 R400 Program Review
`EX 2089 R400 Program Review Documentation
`EX 2090
`PA Check-in History Log
`EX 2091 RB Check-in History Log
`EX 2092
`SC Check-in History Log
`EX 2093
`SPI Check-in History Log
`EX 2094
`SP Check-in History Log
`EX 2095
`SQ Check-in History Log
`EX 2096
`SX Check-in History Log
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`Exhibit # Reference Name
`EX 2097 VGT Check-in History Log
`EX 2098 R400 File Logs 10/1/2002 – 4/17/2003
`EX 2099 Netlist Area Sheets
`EX 2100
`IKOS Schematic
`EX 2101
`Stephen Morein Depo Transcript (AMD v. LG) May 25, 2017
`EX 2102
`Laurent Lefebvre Depo Transcript (337-TA-1044) June 28, 2017
`EX 2103
`IPR2015-00325, Declaration of Laurent Lefebvre
`EX 2104 Development Documentation
`EX 2105 Development Documentation
`EX 2106 Development Documentation
`EX 2107 Development Documentation
`EX 2108 Development Documentation
`EX 2109 Development Documentation
`EX 2110
`IPR2015-00325, EX 2018 - EX. 2056
`EX 2111
`IPR2015-00325, EX 2057 - EX 2071
`EX 2112 Block Change Logs
`EX 2113 Andrew Gruber Depo Transcript (AMD v. LG) July 27, 2017
`EX 2114
`IPR2015-00326, EX 2001 - EX2002
`EX 2115
`IPR2015-00326, EX 2003
`EX 2116
`IPR2015-00326, EX 2004
`EX 2117
`IPR2015-00326, EX 2005
`EX 2118
`IPR2015-00326, EX 2006
`EX 2119
`IPR2015-00326, EX 2007 - EX 2072
`EX 2120
`IPR2015-00326, EX 2073 - EX 2118
`EX 2121
`Supplemental Declaration of William Mangione-Smith
`EX 2122
`Supplemental Declaration of Calvin Watson
`EX 2123 Deposition Transcript of Hanspeter Pfister (02/16/2024)
`EX 2124 Beyond3D-ATI Xenos: Xbox 360 Graphics Demystified – July
`26, 2017
`EX 2125 Dictionary of Computing 5th Ed (excerpt)
`EX 2126 Microsoft Computer Dictionary 5th Edition (excerpt)
`EX 2127 How GPUs Work, David Luebke, Greg Humphreys
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`EX 2131
`EX 2132
`
`Exhibit # Reference Name
`EX 2128
`2006 Microsoft Corporation Annual Report
`EX 2129 ATI and NVIDIA Proclaim Different Graphics Processors
`Architecture Goals, Anton Shilov (December 23, 2004)
`EX 2130 NVIDIA Chief Architect: Unified Pixel and Vertex Pipelines –
`The Way to Go. NVIDIA Says It Would Make a Chip with
`Unified Pipes “When it Makes Sense” Anton Shilov (July 11,
`2005)
`FORTUNE: Review of the Xbox 360 – Nov. 17, 2005
`TECHSPOT – History of the Modern Graphics Processor, Part 3
`– The Fall of 3Dfx and The Rise of Two Giants, Graham Singer
`(April 10, 2013)
`EX 2133 Working of Xbox 360 – How Xbox 360 Works (February 11,
`2010)
`EX 2134 Xbox 360: the Ars Technica Review, Ben Kuchera (November
`30, 2005)
`EX 2135 Microsoft Xbox dominates a sluggish 2011 gaming market,
`Nathan Pensky (January 13, 2012)
`EX 2136 Microsoft’s Xbox 360, Sony’s PS3 – A Hardware Discussion,
`Anand Lal Shimpi & Derek Wilson (June 24, 2005)
`EX 2137 Qualcomm History and its GPU (R)evolution – Ryan Shrout
`(June 22, 2015)
`EX 2138 Xbox 360 vs. PlayStation 3: The Hardware Throwdown – IGN,
`Jesse Schedeen (August 26, 2010)
`EX 2139 Xbox 360 and Playstation 3’s Graphics Card (GPU) Compared –
`Red Gaming Tech, CrimsonRayne (March 11, 2013)
`EX 2140 Xbox 360 GPU – NeutralX2 (April 26, 2006)
`EX 2141 Wikipedia - Adreno
`EX 2142 Game Consoles: Global Market share 2006-2010 – Statista
`EX 2143 NVIDIA – Frequently Asked Questions
`EX 2144
`The Xbox 360 Uncloaked – The Real Story Behind Microsoft’s
`Next-Generation Video Game Console, Dean Takahashi
`EX 2145 Xbox 360 System Architecture
`EX 2146
`Interview with Ken Kutaragi, President of Sony – “Why I worked
`with NVIDIA on the PS3” (Certified Translation)
`
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`Exhibit # Reference Name
`EX 2147
`Scott Wasson, “Details of ATI’s Xbox 360 GPU unveiled,” The
`Tech Report (May 19, 2005)
`
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`PROTECTIVE ORDER
`
`I.
`
`INTRODUCTION
`1.
`I have been retained by ATI Technologies UCL (“ATI” or “Patent
`
`Owner”), as an independent expert in this proceeding before the Patent Trial and
`
`Appeal Board (“PTAB” or “Board”), to examine whether United States Patent No.
`
`8,760,454 (“the ’454 Patent”) was conceived and diligently reduced to practice prior
`
`to the Lindholm ’685 and ’913 patents, whose effective dates are June 30, 2003 and
`
`June 27, 2003, respectively. I understand that Realtek requested the Board institute
`
`an Inter Partes Review (“IPR”) proceeding of the ’454 Patent (EX. 1001) in
`
`IPR2023-00922, and that the Board instituted the IPR on December 1, 2023.
`
`2.
`
`I am providing this testimony for consideration by the Patent Trial and
`
`Appeal Board in this proceeding. I have personal knowledge of the facts and
`
`opinions set forth in this declaration and all the opinions and conclusions found in
`
`this declaration are my own.
`
`3.
`
`I am being compensated at my ordinary hourly rate for my efforts with
`
`regards to this matter. My compensation does not depend in any way on the outcome
`
`of this proceeding or the opinions I express, or the testimony I give.
`
`4.
`
`This declaration contains my conclusions and a summary of my
`
`analysis including a summary of my conclusions, an overview of my qualifications
`
`as an expert, an overview of the materials I have considered in arriving at my
`
`conclusions, an overview of the terminology and legal principles that I applied in
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`
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`my analysis, an overview of the technical background of the subject matter, an
`
`overview of the ’454 Patent, and an analysis of when the inventions of the ’454
`
`Patent were conceived and diligently reduced to practice.
`
`5.
`
`This declaration is based on information currently available to me. I
`
`intend to continue my investigation and study, which may include a review of
`
`documents and information that may yet be produced, as well as deposition
`
`testimony from depositions for which transcripts are not yet available or that may
`
`yet be taken in this proceeding. Therefore, I expressly reserve the right to expand or
`
`modify my opinions as my investigation and study continue, and to supplement my
`
`opinions in response to any additional information that becomes available to me, any
`
`matters raised by Petitioner (or its experts) or the Board (or its experts), or in light
`
`of any relevant opinions or orders from the Patent Trial and Appeal Board or other
`
`authoritative body. Moreover, I reserve the right to provide rebuttal testimony
`
`regarding any analyses and opinions raised in opposition to my declaration.
`
`II.
`
`SUMMARY OF CONCLUSIONS
`A.
`Summary of Conclusions Regarding Reduction to Practice,
`Conception, and Diligence
`It is my opinion that the historical ATI design documentation
`
`6.
`
`demonstrates that at least by at least August 24, 2001, the inventors had conceived
`
`of the inventions claimed in claims 1-11 of the ’454 Patent. It is also my opinion that
`
`the inventors diligently reduced the inventions of the ’454 Patent to practice. It is
`
`2
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`my opinion that the filing of US Patent Application 10/718,318 application, a parent
`
`application to the application which resulted in the ’454 Patent, on November 20,
`
`2003 qualifies as a constructive reduction to practice of claims 1-11 of the ’454
`
`Patent. US Patent Application 10/718,318 resulted in U.S. Patent No. 6,897,871 (the
`
`“’871 Patent”). The specification of the ’871 Patent discloses each and every element
`
`of claims 1-11 of the ’454 Patent.
`
`B.
`7.
`
`Summary of Conclusions Regarding Validity
`It is my opinion that the ’454 Patent is not obvious in view of: (i)
`
`Lindholm ’685 and Lindholm ’913; (ii) Amanatides and Kohn; and (iii) Selzer and
`
`Fiske. It is also my opinion that secondary considerations supports validity of the
`
`claims of the ’454 Patent.
`
`III. EXPERT QUALIFICATIONS
`8. My technical background and experience cover most aspects of
`
`computer system design, including low level circuitry, computer architecture,
`
`computer networking, graphics, application software, client-server application, Web
`
`technology, and system software (e.g., operating systems and compilers). I am a
`
`member of the Institute of Electrical and Electronics Engineers and the Association
`
`for Computing Machinery, which are the two most significant professional
`
`organizations in my profession. I have been employed as a design engineer, research
`
`engineer, professor, and technical expert. Over my professional career, I have been
`
`3
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`an active inventor with 112 issued U.S. patents, 200 published and pending U.S.
`
`patent applications and many unpublished U.S. patent applications.
`
`9.
`
`From 1984 until 1991, I attended the University of Michigan in Ann
`
`Arbor, Michigan, where I was awarded the degrees of Bachelor of Science and
`
`Engineering, Master of Science and Engineering, and Doctorate of Philosophy. My
`
`doctoral research focused on high performance computing systems including
`
`computer architecture, applications and operating system software, and compiler
`
`technology. One of my responsibilities during my graduate studies included
`
`teaching senior undergraduate students who were about to enter the profession.
`
`10. After graduating from the University of Michigan, I was employed by
`
`Motorola in Schaumburg, Illinois. While at Motorola, I was part of a team designing
`
`and manufacturing the first commercial battery-powered product capable of
`
`delivering Internet email over a wireless (i.e., radio frequency) link and one of the
`
`first personal digital assistants. I also served as the lead architect on the second-
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`generation of this device with control over the entire system design including the
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`memory subsystem architecture, embedded processor, ASIC, power system, and
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`analog circuitry. Part of my responsibilities at Motorola involved the specification,
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`design, and testing of system control Application-Specific Integrated Circuits
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`(“ASICs”). I conducted the initial research and advanced design that resulted in the
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`Motorola M*Core embedded microprocessor. M*Core was designed to provide the
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`high performance of desktop microprocessors with
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`the
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`low power of
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`contemporaneous embedded processors. The M*Core received widespread use in
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`many communications products including various cellular handsets, advanced
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`pagers, and embedded infrastructure. While at Motorola I was the sole inventor on
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`one U.S. patent.
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`11. From 1995 until 2005, I was employed by the University of California
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`at Los Angeles (“UCLA”) as a professor of Electrical Engineering. I was the director
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`of the laboratory for Compiler and Architecture Research in Embedded Systems
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`(“CARES”) and served as the field chair for Embedded Computing Systems. The
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`CARES research team focused on research, engineering, and design challenges in
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`the context of battery-powered and multi-media mobile computing devices. One of
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`the key developments of my lab was the Mediabench software tool, which is widely
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`used to design and evaluate multi-media embedded devices. Key elements of
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`Mediabench include software that is essential for modern digital wireless
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`communications. My primary responsibility, in addition to classroom teaching,
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`involved directing the research and training of graduate students. I was a tenured
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`member of the faculty and had responsibilities for teaching as well as scholarly
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`research. While at UCLA I was a named inventor on three U.S. patent applications,
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`one of which issued as a patent. My colleagues at UCLA were some of the leading
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`scientists and engineers in the world with a long list of innovations from computer
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`network security devices to the nicotine patch. The graduate student researchers in
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`my laboratory came from a diverse set of backgrounds, all with undergraduate
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`degrees in computer engineering, electrical engineering, or computer science, many
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`with multiple years of experience working as professional engineers in areas such as
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`software development, computer system design and ASIC circuit design.
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`12. From 2005 until 2009, I was employed at Intellectual Ventures in
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`Bellevue, Washington. My responsibilities at Intellectual Ventures included
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`business development, technology assessment, market forecasting, university
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`outreach, collaborative inventing, intellectual property licensing support, and
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`intellectual property asset pricing. My colleagues and co-inventors at Intellectual
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`Ventures included the former lead intellectual property strategist at Intel, Intel’s
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`former lead IP council, Microsoft’s former chief software architect, the founder of
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`Microsoft research, the designer of the Mach operating system, the architect of the
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`U.S. Defense Department’s Strategic Defense Initiative, the founder of Thinking
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`Machines (a seminal parallel processing computer system), and Bill Gates. I had
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`responsibility for hiring and managing over 15 staff members including multiple
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`Ph.Ds. with degrees in electrical engineering and decades of experience in product
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`design and engineering.
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`13. A summary of some of my qualifications for forming the opinions in
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`this declaration are as follows: I have more than 30 years of experience as a computer
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`architect, computer system designer, educator, and as an executive in the PC and
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`electronics business. I am also a member of several professional associations, such
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`as the ACM, IEEE and have been intimately involved in professional research
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`through the International Symposium on Microarchitecture (Program Chair for 26th
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`and General Chair for 36th), IEEE Transactions on Computers (Associate Editor),
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`ACM Transactions on Embedded Computing Systems (Associate Editor), and IEEE
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`Computer (Associate Editor). I also have been on the program committees for ISCA,
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`MICRO, ISLPED, Network Processors Workshop, FPL, Complexity-Effective
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`Design, RAW, Workshop on Mediaprocessors, and DSP, FPT, and INTERACT.
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`14. For further details regarding my employment and academic history,
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`please refer to my curriculum vitae Appendix A.
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`IV. HIGH LEVEL GRAPHICS PROCESSING OVERVIEW
`15. The ’454 Patent discloses novel architectures for graphics processing
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`unit circuitry. Consumer products are often used to generate and display graphics on
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`an output device such as a built-in screen or an external monitor. When complex and
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`realistic graphics are desired, there is often additional specialized circuitry, in the
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`form of a chip, which is added to the consumer product to assist it with the complex
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`processing that it must perform to render the graphics to the screen. This specialized
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`circuitry is known as a graphics processing unit or “GPU.”
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`A. Graphics Processors Use Vertex and Pixel Data to Create Display
`Images
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`16. Graphics processors (GPUs) are designed to convert a three-
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`dimensional object into an image for display on a two-dimensional screen. As part
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`of this process, a three-dimensional object is rendered as a collection of simple
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`shapes, called primitives. For example, in the figure below, a three-dimensional
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`character has been rendered as a collection of triangular primitives.
`
`
`17. Each triangular primitive is defined by the positions of its three corner
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`points, i.e., its “vertices.” After a three-dimensional object is rendered as a group of
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`primitives, subsequent processing steps include converting the vertices of each
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`primitive from three-dimensional coordinates to two-dimensional coordinates. To
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`illustrate, in the example shown below, a triangular primi