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`RECENTLY,
`the development of
`new types of sophisticated field-
`programmable devices (FPDs) has
`dramatically changed the process
`of designing digital hardware.
`Unlike previous' generations of
`hardware technology in which
`board level designs included large
`numbers of SSI (small-scale inte-
`gration) chips containing basic
`gates, virtually every digital design
`produced today consists mostly of
`high-density devices. This is true
`not only of custom devices such as
`processors and memory but also
`of logic circuits such as state ma-
`chine controllers, counters, regis-
`ters, and decoders When such
`circuits are destined for high-vol-
`ume systems, designers integrate
`them into high-density gate arrays.
`However, the high nonrecurring
`engineering costs and long manufac-
`turing time of gate arrays make them
`unsuitable for prototyping or other low-
`volume scenarios. Therefore, most pro-
`totypes and many production designs
`now use FPDs. The most compelling
`advantages of FPDs are low startup
`cost, low financial risk, and, because
`the end user programs the device,
`quick manufacturing turnaround and
`easy design changes.
`
`difficulty is the complex1
`sophisticated devices.
`the confusion, we prov
`
`42
`
`0740-7475/96/$05 00 0 1996 IEEE
`
`Authorized licensed use limited to: IEEE Publications Operations Staff. Downloaded on February 28,2023 at 16:58:07 UTC from IEEE Xplore. Restrictions apply.
`
`Intel Exhibit 1013
`Intel v. Iida
`
`

`

`Inputs and flip-flop
`feedbacks
`
`utputs
`
`Figure 7. PAL structure.
`
`plane output to produce the logical
`sum of any AND plane output. With this
`structure, PLAs are well-suited for im-
`plementing logic functions in sum-of-
`products form. They are also quite
`versatile, Since both the AND and OR
`terms can have many inputs (product
`literature often calls this feature “wide
`AND and OR gates”).
`When Philips introduced PLAs in the
`early 1970s, their main drawbacks were
`expense of manufacturing and some-
`what poor speed performance. Both
`disadvantages arose from the two lev-
`els of configurable logic; programma-
`ble logic planes were difficult to
`manufacture and introduced significant
`propagation delays. To overcome these
`weaknesses, Monolithic Memories
`(MMI, later merged with Advanced
`Micro Devices) developed PAL devices.
`As Figure 1 shows, PALS feature only a
`single level of programmability-a pro-
`grammable, wired-AND plane that
`feeds fixed-OR gates. To compensate
`for the lack of generality incurred by the
`fixed-OR plane, PALS come in variants
`with different numbers of inputs and
`outputs and various sizes of OR gates.
`To implement sequential circuits, PALS
`usually contain flip-flops connected to
`the OR gate outputs.
`The introduction of PAL devices pro-
`foundly affected digital hardware de-
`sign, and they are the basis of some of
`the newer, more sophisticated archi-
`
`SUMMER 1996
`
`tectures that we will describe shortly.
`Variants of the basic PAL architecture
`appear in several products known by
`
`FPDs, including PLAs, PALS, and PAL
`like devices, into the single category of
`simple programmable-logic devices
`
`43
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`

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`44
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`
`

`

`Switch type
`
`Reprogramma ble?
`
`Volatile?
`
`Technology
`
`Fuse
`EPROM
`
`EEPROM
`
`S
`
`M
`
`
`
`Anti fuse
`
`No
`Yes
`(out of circuit)
`Yes
`(in circuit)
`Yes
`(in circuit)
`No
`
`are floating gate transistors like those
`used in EPROM (erasable programma-
`ble read-only memoiy) and EEPROM
`(electrically erasable PROM). For
`FPGAs, they are SRAM (static RAM) and
`antifuse. Table 1 lists the most impor-
`tant characteristics of these program-
`ming technologies.
`To use an EPROM or EEPROM tran-
`sistor as a programmable switch for
`CPLDs (and many SPLDs), the manu-
`facturer places the transistor between
`two wires to facilitate implementation
`of wired-AND functions. Figure 4 shows
`EPROM transistors connected in a
`CPLD’s AND plane. An input to the AND
`plane can drive a product wire to logic
`level 0 through an EPROM transistor, if
`that input is part of the corresponding
`product term. For inputs not involved
`in a product term, the appropriate
`EPROM transistors are programmed as
`permanently turned off. The diagram of
`an EEPROM-based device would look
`similar to the one in Figure 4.
`Although no technical reason pre-
`vents application of EPROM or EEP-
`ROM to FPGAs, current commercial
`FPGA products use either SRAM or an-
`tifuse technologies. The example of
`SRAM-controlled switches in Figure 5 il-
`lustrates two applications, one to con-
`trol the gate nodes of pass-transistor
`switches and the other, the select lines
`of multiplexers that drive logic block in-
`puts. The figure shows the connection
`of one logic block (represented by the
`
`SUMMER 1996
`
`No
`No
`
`No
`
`Yes
`
`Bipolar
`UVCMOS
`
`EECMOS
`
`CMOS
`
`CMOS+
`
`I
`
`I
`
`7
`
`I
`
`I
`
`I-
`
`I
`
`Product
`wire
`
`11
`I
`
`I EPROM
`
`I EPROM
`
`Figure 4. EPROM programmable
`switches.
`
`I
`
`I
`
` I
`I
`I
`Figure 5. SRAM-controlled programmable switches.
`
`AND gate in the upper left comer) to an-
`other through
`two pass-transistor
`switches and then a multiplexer, all
`controlled by SRAM cells. Whether an
`FPGA uses pass transistors, multiplex-
`ers, or both depends on the particular
`product.
`Antifuses are originally open circuits
`that take on low resistance only when
`programmed. Antifuses are manufac-
`tured using modified CMOS technolo-
`
`gy. As an example, Figure 6 (next page)
`depicts Actel’s PLICE (programmable
`logic interconnect circuit element), an
`tifuse structure.’ The antifuse, posi-
`tioned between two interconnect wires,
`consists of three sandwiched layers:
`conductors at top and bottom and an
`insulator
`the middle. Unpro-
`in
`grammed, the insulator isolates the top
`and bottom layers; programmed, the in-
`sulator becomes a low-resistance link.
`
`45
`
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`
`

`

`F
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`ctel's PLICE antifuse structure
`
`Fix errors
`
`Programming unit
`
`Automatic
`
`I
`
`language, or combines these
`Since initial logic entry is not usually in
`an optimized form, the s
`algorithms to optimize
`Then additional algorithms
`resulting logic equations
`into the SPLD. Simulation
`rect operation, and the designer returns
`to the design entry step
`When a design simulates
`designer loads it into a pr
`
`can accommodate large d
`more common to use diffe
`
`Figure 7. CAD process for SPLDs.
`
`PLICE uses polysilicon and n+ diffusion
`as conductors and a custom-developed
`compound, ONO (oxide-nitride-ox-
`insulator. Other antifuses
`eta1 for conductors, with
`amorphous silicon as the middle lay-
`er.2,3
`
`CAD for FPDs
`Computer-aided design programs are
`essential in designing circuits for im-
`plementation in FPDs Such software
`tools are important not only for
`and FPGAs, but also for
`cal CAD system for SPLD
`ware for the following tasks: initial
`design entry, logic optimization, device
`fitting, simulation, and configuration.
`Figure 7 illustrates the SPLD design
`process. To enter a design, the designer
`creates a schematic diagram with a
`graphical CAD tool, describes the de-
`sign in a simple hardware description
`
`46
`
`Authorized licensed use limited to: IEEE Publications Operations Staff. Downloaded on February 28,2023 at 16:58:07 UTC from IEEE Xplore. Restrictions apply.
`
`

`

`ond-sourced by other companies. The
`designation 16R8 means that the PAL
`has a maximum of 16 inputs (eight ded-
`icated inputs and eight input/outputs)
`and a maximum of eight outputs, and
`that each output is registered (R) by a D
`flip-flop. Similarly, the 22V10 has a max-
`imum of 22 inputs and ten outputs. The
`V meansversatile-that
`is, each output
`can be registered or combinational.
`Another widely used and second-
`sourced SPLD is the Altera Classic
`EP610. This device is similar in com-
`plexity to PALS, but offers more flexibil-
`ity in the production of outputs and has
`larger AND and OR planes. The EPGlOs
`outputs can be registered, and the flip-
`flops are configurable as D, T, JK, or SR.
`Many other SPLD products are avail-
`able from a wide array of companies.
`All share common characteristics such
`as logic planes (AND, OR, NOR, or
`NAND), but each offers unique features
`suitable for particular applications. A
`partial list of companies that offer SPLDs
`includes AMD, Altera, ICT, Lattice,
`Cypress, and Philips-Signetics. The com-
`plexity of some of these SPLDs ap-
`proaches that of CPLDs.
`
`CPLDs. As we said earlier, CPLDs
`consist of multiple SPLD-like blocks on
`a single chip. However, CPLD products
`are much more sophisticated than
`SPLDs, even at the level of their basic
`SPLD-like blocks. In the following de-
`scriptions, we present sufficient details
`to compare competing products, em-
`phasizing the most widely used devices.
`
`Altera Max. Altera has developed
`three families of CPLD chips: Max 5000,
`7000, and 9000. We focus on the 7000
`series because of its wide use and state-
`of-the-art logic capacity and speed per-
`formance. Max 5000 represents an older
`technology that offers a cost-effective
`solution; Max 9000 is similar to Max
`7000 but offers higher logic capacity
`(the industry's highest for CPLDs). ' '
`Figure 8 depicts the general archi-
`
`SUMMER 1996
`
`I10
`block
`
`Logc
`array
`,II block
`
`PIA
`
`gure 8. Ahera Max 7000 series architecture.
`
`Array of 16
`macrocells
`
`PIA
`
`-
`
`To I/O cells
`
`A
`gure 9. Ahera Max 7000 logic array block.
`
`cture of the Altera Max 7000 series. It
`Insists of an array of logic array blocks
`id a set of interconnect wires called a
`.ogrammable interconnect array
`'IA). The PIA can connect any logic
`ray block input %r output to any 0th-
`logic array block. The chip's inputs
`
`and outputs connect directly to the PIA
`and to logic array blocks. A logic array
`block is a complex, SPLD-like structure,
`and so we can consider the entire chip
`an array of SPLDs.
`Figure 9 showsthe structure of a log-
`ic array block. Each logic array block
`
`47
`
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`
`

`

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`
`
`Local logic
`array block
`interconnect
`Figure 10. Max 7000 macrocell.
`
`To PIA f-
`
`I
`
`Figure 1 1 . AMD Mach 4 structure
`
`110 (32)
`
`consists of two sets of eight macrocells
`(shown in Figure 10). A macrocell is a
`rogrammable product terms
`(part of an AND plane) that feeds an OR
`gate and a flip-flop. The flip-flops can
`be D, JK, T, or SR, or can be transpar-
`As Figure 10 shows, the product se-
`matrix allows avariable number of
`inputs to the OR gate in a macrocell.
`
`48
`
`Any or all of
`the m
`
`ic arr
`bility makes the Max 7000 s
`efficient in chip area than cla
`bec
`mo
`
`Authorized licensed use limited to: IEEE Publications Operations Staff. Downloaded on February 28,2023 at 16:58:07 UTC from IEEE Xplore. Restrictions apply.
`
`

`

`between this block and a normal PAL
`1) a product term (PT) allocator be-
`tween the AND plane and the macro-
`cells (the macrocells comprise an OR
`gate, an EXOR gate, and a flip-flop), and
`2) an output switch matrix between the
`OR gates and the I/O pins. These fea-
`tures make a Mach 4 chip easier to use
`because they decouple sections of the
`PAL-like block. More specifically, the
`product term allocator distributes and
`shares product terms from the AND
`plane to OR gates that require them, al-
`lowing much more flexibility than the
`fixedsize OR gates in regular PALS. The
`output switch matrix enables any
`macrocell output (OR gate or flip-flop)
`to drive any I/O pin connected to the
`PAL-like block, again providing greater
`flexibility than a PAL, in which each
`macrocell can drive only one specific
`I/O pin. Mach 4’s combination of insy5
`tem programmability and high flexibil-
`ity allow easy hardware design changes.
`
`Lattice pLSI and ispLSI. Lattice offers
`a complete range of CPLDs, with two
`main product lines: the pLSI and the
`isplsI. Each consists of three families of
`EEPROM CPLDs with different logic ca-
`pacities and speed performance. The
`ispLSI devices are insystem program-
`mable.
`Lattice’s earliest generation of CPLDs
`is the pLSI and ispLSI 1000 series. Each
`chip consists of a collection of SPLD-
`like blocks and a global routing pool to
`connect the blocks. Logic capacity
`ranges from about 1,200 to 4,000 gates,
`and pin-to-pin delays are 10 ns. Lattice
`also offers the 2000 series-relatively
`small CPLDs with between 600 and
`2,000 gates. The 2000 series features a
`higher ratio of macrocells to I/O pins
`and higher speed performance than the
`1000 series. At 5.5-ns pin-to-pin delays,
`the 2000 series provides state-of-the-art
`speed.
`Lattice’s 3000 series consists of the
`company’s largest CPLDs, with up to
`5,000 gates and 10- to 15-ns pin-to-pin
`
`SUMMER 1996
`
`I10 (8)
`
`Figure 12. Mach 4 34V16 PAl-like block.
`
`m...........
`Figure 73. lattice plSl and isplSl architecture.
`
`I...........
`
`jelays. Compared with the chips dis-
`xssed so far, the functionality of the
`3000 series is most similar to that of the
`Uach 4. Unlike the other Lattice CPLDs,
`he 3000 series offers enhancements to
`juppoit more recent design styles, such
`3s IEEE Std 1149.1 boundaly scan.
`Figure 13 shows the general structure
`3f a Lattice pLSI or ispLSI device.
`$round the chip’s outside edges are
`%directional I/Os, which connect to
`30th the generic logic blocks and the
`global routing pool. As the magnified
`Jiew on the right side of the figure
`jhows, the generic logic blocks are
`
`small PAL-like blocks consisting of an
`AND plane, a product term allocator,
`and macrocells. The global routing
`pool is a set of wires that span the chip
`to connect generic logic block inputs
`and outputs. All interconnects pass
`through the global routing pool, so tim-
`ing between logic levels is fully pre-
`dictable, as it is for the AMD Mach
`devices.
`
`Cypress Flash370. Cypress has re-
`cently developed CPLD products simi-
`lar to the AMD and Lattice devices in
`several ways. Cypress Flash370 CPLDs
`
`49
`
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`
`

`

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`
`clot; (4)
`
`110s
`110s
`110s
`
`l10s
`
`I/OS
`
`0-16 kputs
`,I OR, bypassable
`,,,' (D, T, latch)
`--- - _ _ _ _ _ - -.
`flip-flop,
`tristate buffer
`Figure 14. Cypress Flash370 architecture. (PIM: programmable interconnect matrix,.)
`
`__ . -__
`-,----
`
`_*--,, 32 (macrocells --.,
`_ _ - -
`_ - -
`_ - -
`and I10 pins)
`,'
`- '
`
`'\
`
`I
`
`I/O
`I/O
`110
`
`I/O
`
`-, ,, -
`
`'*\
`
`Data in
`
`Address
`
`Control
`
`Clock
`Data out
`
`Figure 15. Altera Flashlogic CPLD: general architecture (a); CFB in PAL mode {b]; CFB
`in SRAM mode [c)
`
`use flash EEPROM technology and of-
`fer speed performance of 8.5 to 15 ns
`pin-to-pin delays. The Flash370s are not
`in-system programmable. To meet the
`needs of larger chips, the devices pro-
`vide more I/O pins than competing
`products, with a linear relationship be-
`tween the number of macrocells and
`the number of bidirectional
`
`50
`
`The smallest parts have 32 macrocells
`and 32 I/O pins; the largest have 256
`macrocells and 256 pins.
`Figure 14 shows that Flas
`a typical CPLD architectu
`ple PAL-like blocks connecte
`grammable interconnect
`
`Authorized licensed use limited to: IEEE Publications Operations Staff. Downloaded on February 28,2023 at 16:58:07 UTC from IEEE Xplore. Restrictions apply.
`
`

`

`all other CPLDs: Instead of containing
`AND/OR logic, a CFB can serve as a
`IO-ns SRAM block. Figure 15b shows a
`CFB configured as a PAL, and Figure
`15c shows another configured as an
`SRAM. In the SRAM configuration, the
`PAL block becomes a 128-word by 10-
`bit read/write memory. Inputs that
`would normally feed the AND plane in
`the PAL become address lines, data
`lines, or control signals for the memo-
`ry. Flip-flops and tristate buffers are still
`available in the SRAM configuration.
`In the Flashlogic device, the AND/OR
`logic plane's configuration bits are
`SRAM cells connected to EPROM or
`EEPROM cells. Applying power loads
`the SRAM cells with a copy of the non-
`volatile EPROM or EEPROM, but the
`SRAM cells control the chip's configu-
`ration. The user can reconfigure the
`chips in system by downloading new in-
`formation into the SRAM cells. The user
`can make the SRAM cell reprogram-
`ming nonvolatile by writing the SRAM
`cell contents back to the EPROM cells.
`
`ICT PEEL Arrays. ICT PEEL (pro-
`grammable, electrically-erasable logic)
`Arrays are large PLAs that include logic
`macrocells with flop-flops and feed-
`back to the logic planes. Figure 16 il-
`lustrates this structure, which consists
`of a programmable AND plane that
`feeds a programmable OR plane. The
`OR plane's outputs are partitioned into
`groups of four, and each group can be
`input to any of the logic cells. The log-
`ic cells provide registers for the sum
`terms and can feed back the sum terms
`to the AND plane. Also, the logic cells
`connect sum terms to I/O pins.
`Because they have a PLA-like struc-
`ture, the logic capacity of PEEL Arrays
`is difficult to measure compared to the
`CPLDs discussed so far, but we estimate
`a capacity of 1,600 to 2,800 equivalent
`gates. Containing relatively few I/O pins,
`the largest PEEL Array comes in a 40-pin
`package. Since they do not consist of
`SPLD-like blocks, PEEL Arrays do not fit
`
`SUMMER 1996
`
`pins &
`
`I/O
`
`El-
`Input
`pins
`
`terms
`
`U 'Group of four
`sum terms
`Figure 76. ICT PEEL Array architecture
`
`the CPLD
`category.
`into
`well
`Nevertheless, we include them here b e
`cause they exemplify PLA-based (rather
`than PAL-based) devices and offer larg-
`er capacity than a typical SPLD.
`The PEEL Array logic cell, shown in
`Figure 17, includes a flip-flop, config-
`urable as D, T, or JK, and two multi-
`plexers. Each multiplexer produces a
`logic cell output, either registered or
`combinational. One logic cell output
`can connect to an I/O pin, and the oth-
`er output is buried. An interesting fea-
`ture of the logic cell is that the flip-flop
`clock, preset, and clear are full sum-of-
`product logic functions. Distinguishing
`PEEL Arrays from all other CPLDs,
`which simply provide product terms for
`these signals, this feature is attractive for
`some applications. Because of their
`PLA-like OR plane, PEEL Arrays are es-
`pecially well suited to applications that
`require very wide sum terms.
`
`CPLD applications. Their high
`speeds and wide range of capacities
`make CPLDs useful for many applica-
`tions, from implementing random glue
`logic to prototyping small gate arrays.
`An important reason for the growth of
`the CPLD market is the conversion of
`designs that consist of multiple SPLDs
`into a smaller number of CPLDs.
`CPLDs can realize complex designs
`such as graphics, LAN, and cache con-
`trollers. As a rule of thumb, circuits that
`
`Four
`sum A+..---$-
`erms
`
`I Global reset
`Figure 77. ICJ PEEL Array logic cell
`structure.
`
`:an exploit wide AND/OR gates and do
`iot need a large number of flip-flops are
`good candidates for CPLD implemen-
`ation. Finite state machines are an ex-
`:ellent example of this class of circuits.
`4 significant advantage of CPLDs is that
`hey allow simple design changes
`hrough reprogramming (all commer-
`5al CPLD products are reprogramma-
`de). In-system programmable CPLDs
`?veri make it possible to reconfigure
`iardware (for example, change a pro-
`ocol for a communications circuit)
`Nithout powering down.
`Designs often partition naturally into
`he SPLD-like blocks in a CPLD, pro-
`jucing more predictable speed perfor-
`nance than a design split into many
`small pieces mapped into different ar-
`?as of the chip. Predictability of circuit
`mplementation is one of the strongest
`idvantages of CPLD architectures.
`FPGAs. As one of the fastest growing
`segments of the semiconductor indus-
`ry, the FPGA marketplace is volatile.
`rhe pool of companies involved
`Zhanges rapidly, and it is difficult to say
`Nhich products will be most significant
`Nhen the industry reaches a stable
`state. We focus here on products cur-
`cently in widespread use. In describing
`2ach device, we list its capacity in two-
`nput NAND gates as given by the ven-
`joy. Gate count is an especially
`zontentious issue in the FPGA industry,
`md so the numbers given should not
`3e taken too seriously. In fact, wags
`
`51
`
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`

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`F
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`c1 c2 G3 e4
`
`A M M
`
`A
`
`__ __
`
`channels
`not shown
`
`Figure 19. X i h x XC4000 wire segments.
`
`have coined the term “d
`erence to the often-cited ratio between
`human and dog years, to indicate the
`
`Xilinx FPGAs. Xilinx FP
`array-based structure, eac
`
`or antifuse-base
`
`52
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`short wire segments that span a single
`CLB (the number of segments in each
`channel varies for each member of the
`XC4000 family), longer segments that
`span two CLBs, and very long segments
`that span the chip’s entire length or
`width. Programmable switches are
`available (see Figure 5) to connect CLB
`inputs and outputs to the wire segments
`or to connect one wire segment to an-
`other. A small section of an XC4000
`routing channel appears in Figure 19.
`The figure shows only the wire seg-
`ments in a horizontal channel-not
`the
`vertical routing channels, CLB inputs
`and outputs, and the routing switches.
`An important point about the Xilinx in-
`terconnect is that signals must pass
`through switches to reach one CLB
`from another, and the total number of
`switches traversed depends on the par-
`ticular set of wire segments used. Thus,
`an implemented circuit’s speed perfor-
`mance depends in part on how CAD
`tools allocate the wire segments to in-
`dividual signals.
`
`Altera Flex 8000 and Flex 10K.
`Altera’s Flex 8000 series combines
`FPGA and CPLD technologies. The de-
`vices consist of a three-level hierarchy
`much like that of CPLDs. However, the
`lowest level of the hierarchy is a set of
`lookup tables, rather than an SPLDlike
`block, and so we categorize the Flex
`8000 as an FPGA. The SRAM-based Flex
`8000 features a four-input lookup table
`as its basic logic block. Logic capacity
`of the 8000 series ranges from about
`4,000 to more than 15,000 gates.
`Figure 20 illustrates the overall Flex
`8000 architecture. The basic logic
`block, called a logic element, contains
`a four-input lookup table, a flip-flop,
`and special-purpose carry circuitry for
`arithmetic circuits (similar to the Xilinx
`XC4000). The logic element also in-
`cludes cascade circuitry that allows ef-
`ficient implementation of wide AND
`functions. Figure 21 shows details of the
`logic element.
`
`SUMMER 1996
`
`Logic array block
`
`i
`
`n...nn...n n...n
`
`Figure 20. Ahera Flex 8000 architecture.
`
`Figure 2 I. Flex 8000 logic element.
`
`This design groups logic elements into
`sets of eight, called logic array blocks (a
`term borrowed from Altera’s CPLDs). As
`shown in Figure 22 on the next page,
`each logic array block contains local in-
`terconnection, and each local wire can
`connect any logic element to any other
`logic element within the same logic ar-
`ray block. The local interconnect also
`connects to the Flex 8000’s FastTrack
`global interconnect. Like the long wires
`
`in the Xllinx XC4000, each FastTrack wire
`extends the full width or height of the d e
`vice. However, a major difference be-
`tween Flex 8000 and Xilinx chips is that
`FastTrack consists only of long lines,
`making the Flex 8000 easy for CAD tools
`to configure automatically. All FastTrack
`horizontal wires are identical. Therefore,
`interconnect delays in the Flex 8000 are
`more predictable than in FPGAs that
`employ many shorter segments because
`
`53
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`

`

`F
`
`I
`
`E
`
`L
`
`D
`
`-
`
`P
`
`R
`
`O
`
`G
`
`R
`
`A
`
`M
`
`M
`
`A
`
`B
`
`L
`
`E
`
`
`
`From
`FastTrac k
`interconnect Control Cascade, carry
`
`Figure 22. Flex 8000 logic array block.
`
`3
`
`Figure
`
`AT&T ORCA. AT&T's
`
`Figure 24. AT&T ORCA p
`function unit.
`
`the longer paths cont
`grammable switches. Moreover, con-
`nections between horizontal and vertical
`lines pass through active buffers, further
`enhancing predicta
`The Flex 10K fam
`able-size blocks of S
`ded array blocks As
`
`block to serve as
`
`54
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`
`

`

`units based on the original ORCA
`architecture.
`
`Actel FfGAs. Actel offers three main
`FPGA families: Act 1, Act 2, and Act 3.
`Although the three generations have
`similar features, we focus on the most
`recent devices. Unlike the FPGAs de-
`scribed so far, Actel’s devices use anti-
`fuse technology and a structure similar
`to traditional gate arrays. Their design
`arranges logic blocks in rows with hor-
`izontal routing channels between adja-
`cent rows (Figure 25). Actel logic
`blocks, based on multiplexers, are
`small compared to those based on
`lookup tables. Figure 26 illustrates the
`Act 3 logic block, which consists of an
`AND and an OR gate connected to a
`multiplexer-based circuit block. In com-
`bination with the two logic gates, the
`arrangement of the multiplexer circuit
`enables a single logic block to realize a
`wide range of functions. About half the
`logic blocks in an Act 3 device also con-
`tain a flip-flop.
`Actel’s horizontal routing channels
`consist of various-length wire segments
`with antifuses to connect logic blocks
`to wire segments or one wire to anoth-
`er. Although not shown in Figure 25,
`vertical wires also overlie the logic
`blocks, forming signal paths that span
`multiple rows. The speed performance
`of Actel chips is not fully predictable b e
`cause the number of antifuses traversed
`by a signal depends on how CAD tools
`allocate the wire segments during cir-
`cuit implementation. However, a rich
`selection of wire segment lengths in
`each channel and algorithms that guar-
`antee strict limits on the number of an-
`tifuses traversed by any two-point
`connection improve speed perfor-
`mance significantly.
`
`Quicklogic pASZC. Actel’s main com-
`petitor in antifuse-based FPGAs is
`Quicklogic, which has two device fam-
`ilies, PASIC and pASIC2. The pASIC, il-
`lustrated in Figure 27a, has similarities
`
`SUMMER 1996
`
`I/O blocks
`
`n
`
`Routing
`channels
`
`U
`
`I
`Figure 25. Actel FPGA structure.
`
`I/O blocks
`
`Inputs
`
`block
`
`U
`
`Multiplexer-based
`
`circuit block * output
`
`Inputs
`
`Figure 26. Actel Act 3 logic module.
`
`~
`
`to several other FPGAs: Like Xilinx
`FPGAs, it has an array-based structure;
`like Actel FPGAs, its logic blocks use
`multiplexers; and like Altera Flex 8OOOs,
`its interconnect consists only of long
`lines. The pASIC2 is a recently intro-
`duced enhanced version, which we will
`not discuss here. Cypress also offers de-
`vices using the pASlC architecture, but
`we discuss only Quicklogic’s version.
`Quicklogic’s ViaLink antifuse struc-
`ture (see Figure 27b) consists of a metal
`top layer, an amorphoussilicon insulat-
`-0 o n
`U
`U
`... ...
`-
`U
`U
`...
`...
`0
`...
`...
`.
`.
` at every
`.
`.
`
`.
`.
`
`.
`.
`
`: : Loaic cell i
`...
`... - -
`U u u
`
`ViaLink
`
`wire
`crossing
`
`i
`
`110 blocks
`
`[a)
`(b)
`Figure 27. Quicklogic pASlC structure (aj and ViaLink (bj.
`
`Metal 1
`
`55
`
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`

`

`F
`
`I
`
`E
`
`L
`
`D
`
`-
`
`P
`
`R
`
` O
`
`G
`
`R
`
`A
`
`
`M
`
`M
`
`A
`
`B
`
` L
`
`E
`
`
`
`B1
`B2
`c1
`c2
`D1
`D2
`E l
`E2
`
`AZ
`
`oz
`
`QZ
`
`NZ
`
`F5
`
`F6 F6
`
`QC QC
`QR
`Figure 28. Quicklogic pASlC logic cell.
`
`ing layer, and a metal bottom layer
`Compared to Actel’s PLICE antifuse
`ViaLink offers very low on-resistance-
`about 50 ohms (PLICE’s is about 30C
`ohms)-and
`a low parasitic capaci
`tance. ViaLink antifuses are present ai
`every crossing of logic block pins aDd in.
`terconnect wires, providing
`connectivity. Figure 28 shows
`multiplexer-based logic block. It is more
`complex than Actel’s logic module, witk
`more inputs and wide (six-input) ANC
`gates on the multiplexer select lines
`Every logic block also contains a flip
`flop.
`
`FPGA applications. FPGAs have
`gained rapid acceptance over the pas
`decade because users can apply therr
`to a wide range of applications: randon
`logic, integrating multiple SPLDs, device
`controllers, communication encoding
`and filtering, small- to mediumsize sys
`terns with SRAM blocks, and many more
`eresting FPGA applicatior
`designs to be implement
`ed in gate arrays by using one or mort
`large FPGAs. (A large FPGA correspond:
`to a small gate array in term
`ty). Still another application
`
`lation of entire large hardware systems
`via the use of many interconnected
`FPGAs. QuickTurn4 and others have d e
`veloped products consisting of the
`FPGAs and software necessary to parti-
`tion and map circuits for hardware em-
`
`An application d y beginning devel-
`opment is the use of FPGAs as custom
`computing machines. This involves us-
`
`ware for execution on a regular CPU. For
`information, we refer readers to the pro
`ceedings of the IEEE Workshop on
`FPGAs for Custom Computing Machines,
`held for the last four years?
`
`signs often map naturally
`
`mapped into an FPGA brea
`logic-block-size pieces d
`through an area of the FPGA. Depending
`
`the logic block interconne
`produce delays. Thus, FP
`mance often depends more
`
`ents in archite
`
`Acknowledgments
`We acknowledge students,
`and acquaintances in mdustiy w
`tributed to our knowledge.
`
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`
`

`

`Roc. Design Automation Conference PAC),
`IEEE CS Press.
`FPGA Symp. Series: Third Int’l ACM Symp.
`Field-Programmable Gate Arrays (FPGA
`95) and Fourth Int’l ACMSymp. Field-Pro-
`grammable Gate Arrays (EPGA 961,
`Assoc. for Computing Machinery, New
`York.
`
`trical engineering, computer engineering,
`and computer science courses. Brown is
`the general and program chair for the
`Fourth Canadian Workshop on Field-Pro-
`grammable Devices (FPD 96), and is on the
`Technical Program Committee for the Sixth
`International Workshop on Field-Program-
`mable Logic (FPL 96). He is a member of
`the IEEE and the Computer Society.
`
`and systems. He coauthored the book Field-
`Programmable Gate Arrays. Rose holds a
`PhD in electrical engineering from the Uni-
`versity of Toronto. He is the general chair
`of the Fourth International Symposium on
`FPGAs (FPGA 96) and serves on the tech-
`nical program committee for the Sixth
`International Workshop on Field-Program-
`mable Logic. In 1990, ICCAD awarded him
`and coauthor Stephen Brown a Best Paper
`award. He is a member of the IEEE, the
`Computer Society, the Association for
`Computing Machinery, and SIGDA.
`
`Stephen Brown is an assistant professor of
`electrical and computer engineering at the
`University of Toronto. He holds a PhD in
`electrical engineering from that university;
`his dissertation (on architecture and CAD
`for FPGAs) won him the Canadian NSERC‘s
`1992 prize for the best doctoral thesis in
`Canada. In 1990, the International Confer-
`ence on Computer-Aided Design awarded
`him and coauthor Jonathan Rose a Best Pa-
`per award. A coauthor of the book Field-
`Programmable Gate Arrays, he has also won
`four awards for excellence in teaching elec-
`
`Jonathan Rose is an associate professor
`of electrical and computer engineering at
`the University of Toronto. His research in-
`terests are in the area of architecture and
`CAD for field-programmable gate arrays
`
`Direct questions concerning this ar