ae Re eRe
`
`FIELD-PROGRAMMABLE
`CTU NairN
`TECHNOLOGY
`
`SCaSTM Oe Reteto Intel Exhibit 1012
`
`edited by
`
`Intel v. lida
`
`Intel Exhibit 1012
`Intel v. Iida
`
`

`

`FIELD-PROGRAMMABLE GATE
`FIELD-PROGRAMMABLE GATE
`ARRAY TECHNOLOGY
`ARRAY TECHNOLOGY
`
`

`

`FIELD-PROGRAMMABLE GATE
`ARRAY TECHNOLOGY
`
`edited by
`
`Stephen M. Trimberger
`Xilinx
`
`with contributions by
`
`Stephen M. Trimberger
`Xilinx
`
`Dennis McCarty
`Telle Whitney
`Actel
`
`and
`The Technical Staff of Altera Corporation
`edited by
`Robert Hartmann
`
`~. "
`
`SPRINGER. SCIENCE+BUSINESS MEDIA, LLC
`
`

`

`Library of Congress Cataloglng-In-Publlcatlon Data
`
`Field -programmable gate array technology / edited by Stephen M.
`Trimberger.
`p. cm.
`Includes bibliographical references and index.
`ISBN 978-1-4615-2742-8 (eBook)
`ISBN 978-1-4613-6183-1
`DOI 10.1007/978-1-4615-2742-8
`1. Gate array circuits. 2. Programmable logic devices.
`3. Programmable array logic. 1. Trimberger, Stephen, 1955 -
`TK7895.G36F54 1994
`621.39'5--dc20
`
`93-39703
`CIP
`
`Copyright © 1994 by Springer Science+Business Media New York
`Originally published by Kluwer Academic Publishers in 1994
`Softcover reprint of the hardcover Ist edition 1994
`AII rights reserved. No part ofthis publication may be reproduced, stored in a retrieval
`system or transmitted in any form orby any means, mechanical, photo-copying, record ing,
`or otherwise, without the prior written permission of the publisher,
`Springer Science+Business Media, LLC.
`
`Printed an acid-free pa per.
`
`

`

`to ross
`to ross
`
`whohad a vision
`who had a vision
`
`

`

`Contents
`
`Preface
`
`Chapter 1. Introduction
`1.1. Logic Implementation Options
`
`1.2. What is an FPGA?
`
`1.3. Advantages of FPGAs
`Low Tooling Costs
`Rapid Turnaround
`Low Risk
`Effective Design Verification
`Low Testing Costs
`Standard-Product Advantages
`Life Cycle Advantages
`
`1.4. Disadvantages of FPGAs
`Chip Size and Cost
`Speed of Circuitry
`Design Methodology
`
`1.5. Technology Trends
`Density
`Speed
`Architecture
`
`1.6. Designing for FPGAs
`Design Migration
`
`1.7. Outline of Subsequent Chapters
`1. Introduction
`2. Programming Technology
`3. Device Architecture
`4. Software
`5. The Future
`6. Design Applications
`7. Acknowledgments
`8. References
`1.8. References
`
`xi
`
`1
`
`1
`
`2
`
`4
`4
`4
`5
`6
`6
`7
`8
`8
`8
`9
`9
`10
`10
`10
`11
`
`11
`11
`
`12
`12
`13
`13
`13
`13
`13
`13
`13
`13
`
`

`

`viii
`
`FPGA Tecbnology
`
`Chapter 2. SRAM Programmable FPGAs
`2.1. Introduction
`
`2.2. Programming Technology
`SRAM Programming
`Advantages and Disadvantages of SRAM Programming
`
`2.3. Device Architecture
`Simple SRAM-Programmable FPGA Architecture
`Design Trade-offs
`The Xilinx XC2000 Architecture
`The Xilinx XC3000 Architecture
`The Xilinx XC4000 Architecture
`Programming the FPGA
`2.4. Software
`Automated Design Implementation
`Technology-Specific Synthesis
`Manual Design
`
`2.5. The Future
`Programming Technology
`Architecture
`Software
`Partitioning in Space and Time
`Design Methodology
`
`2.6. Design Applications
`General Design Issues
`Counter Examples
`Efficient Multiplication by a Constant in an Artificial Neural Network
`Distributed Arithmetic for Signal Processing
`Applications of Reprogramming
`A Fast Video Controller
`A Position Tracker For a Robot Manipulator
`A Fast DMA Controller
`Custom Computing Applications
`2.7. Acknowledgments
`2.8. References
`
`15
`15
`15
`15
`17
`
`19
`19
`23
`29
`35
`43
`52
`53
`54
`63
`63
`
`65
`65
`66
`66
`67
`67
`
`68
`68
`70
`75
`77
`79
`83
`84
`85
`87
`90
`91
`
`

`

`Contents
`
`ix
`
`Chapter 3. Antifuse Programmed FPGAs
`3.1 Introduction
`3.2 Programming Technology
`
`3.3 Device Architecture
`Principles of Programmable Routing
`Routing Architecture of the Actel FPGAs
`Actl Architecture
`Act2 Architecture
`Act3 Architecture
`Programming and Testing
`Capacity
`Perfonnance
`3.4 Software
`
`3.5 The Future
`3.6 Design Applications
`Designing with ACT! and ACT2 FPGAs
`Designing with ACT FPGAs: A 1TL Perspective
`Migrating PLD Designs to FPGAs
`Synthesis Design Flow
`Designing Counters with ACT Devices
`Designing Adders and Accumulators with the ACT Architecture
`State Machine Design
`Using FPGAs for Digital PLLs
`Customer Design Examples
`
`3.7 Acknowledgments
`3.8 References
`
`Chapter 4. Erasable Programmable Logic Devices
`4.1. Introduction
`4.2. Programming Technology
`Logic Structures Using EPROM Transistors
`
`97
`
`97
`
`99
`
`103
`103
`108
`110
`113
`117
`118
`124
`127
`128
`
`132
`133
`133
`137
`140
`143
`144
`153
`160
`164
`167
`168
`168
`
`171
`171
`173
`175
`
`

`

`x
`
`FPGA Technology
`
`4.3. Device Architecture
`Basic Concepts
`Macrocell Architecture
`Logic Array
`Programmable Flip-Flops
`Programmable Clock
`110 Control Block
`Design Security
`Functional Testing
`Operating Requirements for EPLDs
`Architectural Evolution in Array-Based PLDs
`4.3.1 - The "Classic" Family of PLDs
`Functional Description of the EP 1810
`4.3.2 - The MAX (Multiple Array matriX) Product Family
`4.3.3 - MAX 7000
`4.3.4 - MPLDs: Mask-Programmed Logic Devices
`4.4. Software
`
`4.5. The Future
`
`4.6. Design Applications
`4.6.1 MAX 5000 Timing
`4.6.2 Using Expanders to Build Registered Logic in MAX EPLDs
`4.6.3 Simulating Internal Buses in General-Purpose EPLDs
`4.6.4 Fast Bus Controllers with the EPM5016
`4.6.5 Micro Channel Bus Master and SDP Logic with the EPM5032
`EPLD
`4.6.6 FIFO Controller Using an EPM7096
`4.6.7 Integrating an Intelligent 110 Subsystem with a Single EPM5130
`EPLD
`4.6.8 Controlling Complex CCD Imaging Systems with the EPS464
`EPLD
`
`4.7. References
`
`Index
`
`179
`179
`180
`180
`181
`182
`182
`182
`183
`183
`184
`184
`184
`187
`195
`200
`204
`
`218
`
`224
`224
`228
`233
`238
`
`240
`243
`
`246
`
`247
`
`250
`
`253
`
`

`

`Preface
`
`A Field Programmable Gate Array (FPGA) is a programmable logic device that
`implements multi-level logic. FPGAs resemble traditional mask-programmed gate
`arrays by their modular, extensible structure that includes both logic and interconnect.
`but differ in that their programming is done by end users at their site. No masking
`steps are required. In this respect. FPGAs resemble PLDs. FPGAs offer low risk, low
`incremental cost and fast prototyping advantages.
`
`FPGAs are revolutionizing the way systems designers implement logic. By radically
`reducing the development costs and the turnaround time for implementing thousands
`of gates of logic, FPGAs provide a new capability that affects the semiconductor
`industry and the CAE industry. They may also change the way digital systems will be
`designed in the future.
`
`The Scope of the Book
`
`The field of FPGAs is varied and dynamic. Many different kinds of FPGAs exist. with
`different programming technologies, different architectures and different software.
`This book describes the major FPGA architectures available today, covering the three
`programming technologies that are in use and the major architectures built on those
`programming technologies. The goal is to introduce the reader to concepts relevant to
`the entire field of FPGAs using popular devices as examples, without trying to
`enumerate every commercially-available product.
`
`This book includes discussions of FPGA integrated circuit manufacturing, circuit
`design and logic design. It describes the way logic and interconnect are implemented
`in various kinds of FPGAs. It covers particular problems with design for FPGAs and
`future possibilities for new architectures and software. This book compares CAD for
`FPGAs with CAD for traditional gate arrays. It describes algorithms for placement.
`routing and optimization of FPGAs.
`
`The FPGA device descriptions in this book include specifications of capacity and
`speed. These numbers are continually being debated by manufacturers. This book
`does not attempt to enter the debate; there was no attempt to reconcile device
`specifications from different vendors.
`
`FPGA devices and technology are improving rapidly, so specific numbers for gate
`counts and device speeds may already be obsolete. However, the general concepts,
`
`

`

`xii
`
`FPGA Technology
`
`such as programming methods, architectural constraints due to programming
`technologies, device scaling and preferred design methods will remain relevant long
`after the specific devices in this book have only historical interest.
`
`Intended Audience
`
`This book is intended to describe all aspects of FPGA design and development. For
`this reason, it covers a significant amount of material. An extremely detailed
`discussion of all these areas would make this book prohibitively long. Our intent is to
`make each section clear to readers with general technical expertise in digital design
`and design tools. Readers with significant experience in one of these areas may find
`the discussions superficial in that area, but useful in others.
`
`This book assumes the reader has an understanding of the fundamentals of digital
`electronics design. Experience designing or using ASIC gate arrays and software will
`make much of this book much easier to read, since many of the comparisons are with
`respect to gate arrays.
`
`Potential developers of FPGAs will benefit primarily from the FPGA architecture and
`software discussion. Electronics systems designers and ASIC users will find this book
`gives them a background on different types of FPGAs and shows applications of their
`use, which are useful for deciding when an FPGA is appropriate for an application.
`
`This book may be useful in a university setting where it can be used in support of a
`comparative FPGA architectures course, as background reading for a digital design
`course with FPGAs as the target implementation, or as supplemental reading for a
`Computer-Aided Design course for tools targeted to FPGA design automation.
`
`This book is not intended as a product specification for any integrated circuit or
`software product.
`
`Organization of the Book
`
`Chapter 1 introduces the FPGA in comparison with other logic implementation
`techniques. It defines the term FPGA in a form that is both general enough to include
`all types of devices currently being offered, and specific enough to be a guide for
`evaluating other devices that may appear. The bulk of chapter 1 is a comparison of
`FPGAs with mask programmed gate arrays, showing the FPGA advantages and
`disadvantages.
`
`The following three chapters describe three very different FPGA architectures and
`software. Chapter 2 describes Xilinx SRAM-based FPGAs, chapter 3 describes Actel
`antifuse-based FPGAs and chapter 4 describes Altera EEPROM-based FPGAs. The
`three architectures were chosen because they were the most common FPGAs
`currently in use and because they are very different in their approaches to field
`programmable logic. They have different programming technologies, different
`
`

`

`Preface
`
`xiii
`
`methods of implementing logic and different interconnection strategies. Each of these
`chapters includes a discussion of an FPGA family, its architecture, software, and
`applications.
`
`Each chapter was written by an expert in that particular type of architecture. Each
`author expresses the concepts in the terminology familiar to developers and users of
`that architecture. To facilitate comparison of the different FPGAs, the chapters follow
`a common outline, described in chapter 1. In addition, the reader may use the index as
`a glossary, as terms with similar meanings are correlated there.
`
`Acknowledgments
`
`I would like to thank all those who contributed directly and indirectly to the success
`of this book, especially the good folks at Xilinx who allowed me the time for this
`project, especially Bernie Vonderschmitt, Wes Patterson, Gary Leive and Bill Carter. I
`wish also to thank the authors of the architecture sections, whose effort and endurance
`were vital to the completion of this project.
`
`Stephen Trimberger
`San Jose, CA
`
`

`

`xiv
`
`FPGA Technology
`
`Trademarks
`
`Xilinx, XACT, XC2064, XC3090, XC4005, and XC-DS50l are registered trademarks of Xilinx. All XC(cid:173)
`prefix product designations, XACT-Performance, XAPP, X-BLOX, XSI, XChecker, XDM, XEPLD, XFf,
`XAPp, XSI, BITA, Dual Block, FastCLK, HardWire, LCA, Logic Cell, PLUSASM and UIM are
`trademarks of Xilinx. The Programmable Logic Company is a service mark of Xilinx.
`
`Act is a trademark and Actel, Action Logic, Activator, Actionprobe and PLICE are registered trademarks
`of Actel Corporation.
`
`Altera. MAX, and MAX+PLUS are registered trademarks of Altera Corporation. The following are
`trademarks of Altera Corporation: MAX+PLUS II, FastTrack, FLEX, AHDL, MPLD, MAX 5000. MAX
`7000, FLEX 8000, Classic, STG, PLS-FLEX, PLDS-HPS, PLDS-MAX, PLS-WS/sN, PLS-WSIHP, PLS(cid:173)
`EDIE Product design elements and mnemonics are Altera Corporation copyright.
`
`ABEL is a trademark of Data VO Corporation.
`
`Viewlogic is a registered trademark of Viewlogic Systems, Incorporated.
`
`OrCAD is a trademark of OrCAD Systems Corporation.
`
`IBM and AT are registered trademarks and IBM pc, XT, PS/2 and Micro Channel are trademarks of
`International Business Machines Corporation.
`
`Windows is a trademark of Microsoft Corporation.
`
`Sun is a trademark of Sun Microsystems, Incorporated.
`
`PAL and PALASM are registered trademarks of Advanced Micro Devices, Incorporated.
`
`Synopsys and Design Compiler are trademarks of Synopsys, Inc.
`
`Radius is a trademark and Pivot is a registered trademarks of Radius, Inc.
`
`Apple and Macintosh are registered trademarks of Apple Computer, Inc.
`
`Quickturn and RPM Logic Emulator are a trademarks of Quickturn Design Systems.
`
`All trademarks are the property of their respecti ve owners.
`
`

`

`FIELD-PROGRAMMABLE GATE
`FIELD-PROGRAMMABLE GATE
`ARRAY TECHNOLOGY
`ARRAY TECHNOLOGY
`
`

`

`Chapter 1
`Introduction
`
`1.1. Logic Implementation Options
`
`An electronic system designer has several options for implementing digital logic.
`These options include discrete logic devices, often called Small-Scale Integrated cir(cid:173)
`cuits, or SSI; programmable devices such as Programmable Array Logic (PALs or
`PLDs); masked-programmed Gate Arrays or Cell-Based ASICs; and Field Program(cid:173)
`mable Gate Arrays (FPGAs).
`
`Small amounts of logic can be implemented easily with discrete devices. Each SSI
`cbip contains a few identical gates of a specific type. Designers choose the logic they
`want from the selection of available chip types. SSI logic is often referred-to as
`"7400-series," in reference to the widely-used Texas Instruments logic family.
`
`A simple Programmable Logic Device (PLD) is a general-purpose device capable of
`implementing the logic of tens or hundreds of SSI packages. Pioneered by MMI, a
`PLD implements logic as wide fan-in two-level sum-of-products of its inputs. It may
`have optional flip-flops or other logic on the outputs of the sum-of-products array. The
`best-known PLD is the "22VlO", with 22 inputs and 10 outputs, developed by AMD
`and copied by numerous others. A PLD is programmed by users at their site using
`inexpensive programming hardware. Power consumption and delay limit the size of
`the simple sum of products structure to dozens of product terms. Large designs
`require a multi-level logic implementation.
`
`To implement designs with thousands or tens of thousands of gates, designers can use
`a Mask Programmed Gate Array (MPGA), commonly called a gate array. An MPGA
`can implement tens of thousands or even hundreds of thousands of gates of logic on a
`single IC in multi-level logic with wiring between logic stages. An MPGA consists of
`a base of pre-designed transistors with customized wiring for each design. The wiring
`is built during the manufacturing process, so each design requires custom masks for
`the wiring. The mask-making charges make low-volume MPGAs expensive. Typical
`turnaround times for MPGAs are four to six weeks.
`
`Field Programmable Gate Arrays offer the benefits of both programmable logic arrays
`and gate arrays. Like MPGAs, FPGAs implement thousands of gates of logic in a sin(cid:173)
`gle integrated circuit. Like PLDs, FPGAs are programmable by designers at their site,
`
`

`

`2
`
`FPGA Technology
`
`30000
`
`5000
`
`1989
`
`1990
`
`1991
`
`1992
`
`1993
`
`Figure 1.1. Number of Designs Implemented as MPGA Versus
`FPGA (source: Dataquest, 1991 and Xilinx, 1992)
`
`eliminating the long delays and tooling costs. These advantages have made FPGAs
`very popular (figure 1.1).
`
`1.2. What is an FPGA?
`
`An FPGA is a general-purpose, multi-level programmable logic device that is cus(cid:173)
`tomized in the package by the end users. FPGAs are composed of blocks of logic con(cid:173)
`nected with programmable interconnect. The programmable interconnect between
`blocks allows users to implement multi-level logic, removing many of the size limita-
`
`20000
`
`15000
`
`Gates 10000
`
`5000
`
`1 000
`100 • • • !!~~
`
`100
`
`1 000
`
`10000 100000
`
`Units
`Figure 1.2. Preferred Implementation Options in the Design
`Space (Source: Xilinx).
`
`

`

`Introduction
`
`3
`
`tions of the PLO-derived two-level logic structure. This extensible architecture can
`currently support thousands of gates of logic at system speeds in the tens of mega(cid:173)
`hertz.
`
`The size. structure and number of blocks; and the amount and connectivity of the
`interconnect vary considerably among FPGA architectures. This difference in archi(cid:173)
`tectures is driven by different programming technologies and different target applica(cid:173)
`tions of the parts. An architectural organization that worlcs well with a particular
`programming technology typically does not work with another. The segmentation by
`programming style and hence architecture is the basis of the taxonomy in figure 1.3.
`FPGAs fall into four groups: island-style and cellular SRAM-programmed devices;
`channeled, antifuse-programmed devices; and array-style EPROM or EEPROM-pro(cid:173)
`grammed devices.
`
`SRAM-programmed island-style FPGAs include all three Xilinx LCA families. the
`AT&T Orca and Altera Flex, as well as U1FPGAI [Chow 1991]. Cellular-style
`FPGAs include Toshiba. Plessey's ERA, Atmel's (formerly Concurrent Logic) CLi
`family, the Algotronix CAL, as well as Triptych [Ebeling 1991]. Antifuse-based
`channelled gate arrays include Actel's ACT-I and ACT-2, Quicklogic's pASIC and
`Crosspoint's CP20K Series FPGA. EPROM-programmed array-like devices resemble
`a collection of PALs with a central interconnection mechanism. Devices of this type
`are Altera's MAX 5000 and MAX 7000, AMO's Mach and Xilinx's EPLO, among
`others.
`
`This definition of FPGA is similar to the Complex PLO (CPLO) definition used by
`the Oataquest market research company. They divide CPLOs into "Programmable
`Multi-level Devices" (PMOs), which are simple PLO arrays with a programmable
`
`I FPGA I
`
`I
`
`I
`
`SRAM-Programmed
`
`Antifuse-Programmed
`Channeled
`
`EPROM-Programmed
`Array
`
`I
`
`I
`
`I
`
`Island I ~ Cellular
`
`Figure 1.3. Taxonomy of FPGAs.
`
`

`

`4
`
`FPGA Technology
`
`interconnection structure; and "FPGAs", which consists of all other multi-level field(cid:173)
`programmable devices. The Dataquest "FPGA" classification covers those devices in
`the SRAM-Programmed and Antifuse-Programmed boxes in figure 1.3. In this book,
`we use the broader definition of FPGAs, which is equivalent to the Dataquest
`"CPLD" classification.
`
`Currently-available FPGAs implement digital logic, but this is not a fundamental lim(cid:173)
`itation. FPGAs composed of analog blocks with programmable interconnect have
`been proposed and built [Lee 1991], but they are not commercially available. This
`book does not describe analog or hybrid FPGAs. The reader is directed to the refer(cid:173)
`ences for further information on analog FPGAs, also called Field-Programmable Ana(cid:173)
`log Arrays (FPAAs).
`
`1.3. Advantages of FPGAs
`
`Figure 1.4 compares MPGA and FPGA design and manufacturing steps. Design entry
`and verification are similar for both technologies, but there are significant differences
`late in the design cycle. Instead of customizing the part by custom manufacturing
`steps, FPGAs are customized by electrical modification of a packaged part. By elimi(cid:173)
`nating the customization during manufacturing, FPGAs eliminate each design's cus(cid:173)
`tom mask-making, test pattern generation, wafer fabrication, packaging and testing.
`The electrical modification takes milliseconds or minutes, depending on the program(cid:173)
`ming technology and size of the part, compared to weeks for the MPGA steps. FPGA
`programming is done by simple, inexpensive programming devices.
`
`System Design
`
`Logic Design
`
`Place and Route
`
`Timing Simulation
`
`Test Pattern Generation
`
`Mask Making
`
`Wafer Fabrication
`
`Packaging
`
`Testing
`
`System Design
`
`Logic Design
`
`Place and Route
`
`Timing Simulation
`
`Download I programming
`
`System Integration
`
`System Integration
`
`Figure 1.4. Design Steps For MPGA versus FPGA
`
`

`

`Introduction
`
`5
`
`Percentage
`of Design
`Starts
`
`<5
`
`5-10
`10-20 20-100 >100
`Thousands of Units
`
`Figure 1.5. MOS Gate Array Design Starts by Unit Volume
`(source: Dataquest 1991).
`
`Low Tooling Costs
`
`Every design to be implemented in an MPGA requires custom masks to build the cus(cid:173)
`tom wiring patterns. Each mask costs several thousand dollars and the cost is amor(cid:173)
`tized over the total number of units manufactured. The more units built, the lower the
`impact of the masking charges. However, comparatively few designs require more
`than tens of thousands of units (figure 1.5), so, for most MPGA designs, the masking
`charges are significant. There is no custom tooling required for an FPGA, so there are
`no associated tooling costs, making FPGAs cost effective for most logic designs.
`
`Rapid Turnaround
`
`The MPGA manufacturing process takes several weeks from the completion of the
`design to the delivery of the finished parts. An FPGA can be programmed in minutes
`by the user of the part. On an FPGA, a modification to correct a design flaw or to
`address a late specification change can be made quickly and cheaply. Faster design
`turnaround leads to faster product development and shorter time-to-market for new
`FPGA products. Reinertsen [1983] determined that in a high-technology environ(cid:173)
`ment, a six-month delay in product delivery cut the lifetime profits of a product by
`thirty-three percent.
`
`Low Risk
`
`The benefits of low initial Non-Recurring Engineering (NRE) charges and rapid turn(cid:173)
`around means that a design iteration due to an error incurs neither a large expense nor
`a long delay. Low costs encourage early system integration and prototyping. The low
`cost of error also encourages more aggressive logic design, which may yield better
`
`

`

`6
`
`FPGA Technology
`
`performance and more cost effective designs.
`
`Effective Design Verification
`
`Because of substantial NRE costs and manufacturing delays, MPGA users verify their
`designs by extensive simulation before manufacture. Simulation has an inherent
`speed/accuracy trade-off: highly accurate simulators are slow, fast simulators are
`inaccurate. To verify the functionality of the design in a system, large amounts of time
`must be simulated. Proper verification requires that the environment of the design be
`simulated as well. Week-long simulation runs are not uncommon. An MPGA design,
`verified by simulation, may include errors due to inaccuracies or over-simplifications
`in the simulation model.
`
`FPGAs avoid these problems. Instead of simulating large amounts of time, FPGA
`users may choose to use in-circuit verification. Designers can implement the design
`and use a functioning part as a prototype. The prototype operates at full speed and
`with excellent timing accuracy. A prototype can be inserted into the system to verify
`functionality of the system as a whole, eliminating a class of system errors early.
`
`Low Testing Costs
`
`All ICs must be tested to verify proper manufacturing and packaging. This test is dif(cid:173)
`ferent for each design. Designs implemented in an MPGA incur three costs associated
`with testing: on-chip logic to facilitate testing, generation of the test program and test(cid:173)
`ing the parts when manufacturing is complete. FPGAs address all these costs.
`
`Good test programs are hard to write, and schedule pressures tend to abbreviate test
`program generation for MPGAs. The poor coverage of MPGA test programs allows
`some bad chips to pass the testing. These defective parts may not be discovered until
`they fail in a system where the cost of repair is high.
`
`In contrast, the test program for FPGAs is the same for all designs and tests the FPGA
`for all users of the part. Because there is only one test program, it is reasonable to
`invest a considerable amount of effort in it, and it can be continually improved over
`the lifetime of the FPGA. The resulting test program achieves excellent test coverage,
`leading to high-quality les.
`
`In the case of reprogrammable parts, the manufacturer can reprogram all programma(cid:173)
`ble points during testing to verify that the part will work properly after programming.
`For one-time-programmable parts, the FPGAs generally include test circuitry to catch
`most failures during manufacture. Manufacturer-supplied hardware and software ver(cid:173)
`ify post-programming functionality. Those parts that fail to pass the post-program(cid:173)
`ming test are rejected on the programming device. The percentage of successfully(cid:173)
`programmed devices is termed programming yield.
`
`The manufacturer's test program verifies that every FPGA will be functional for all
`possible designs that may be implemented on it. FPGA users are not required to write
`
`

`

`Introduction
`
`7
`
`design-specific tests for their designs. Therefore, designers need not build the testabil(cid:173)
`ity into the design, eliminating "design for testability" and the design effort and over(cid:173)
`head associated with it
`
`Standard-Product Advantages
`
`New, denser integrated circuit technologies drive microelectronic advances. New pro(cid:173)
`cessing technologies have finer geometries with smaller transistors and wires. The
`speed and cost of a chip are related to these dimensions, so a smaller chip is both
`cheaper and faster.
`
`Moving an MPGA design to a new process incurs additional NRE charges for new
`masks and test program verification, so it is rarely done. Because FPGAs are standard
`products, only the FPGA manufacturer incurs the cost of moving the chip to a new
`process technology. FPGAs on the new process are available to all customers without
`additional NRE cost. From the point of view of a user, the FPGA manufacturer lowers
`the price and improves the speed of the parts over time. A user of MPGAs does not
`get these improvements without paying the additional NRE charges.
`
`Normal variations in the integrated circuit manufacturing process leads to a distribu(cid:173)
`tion of performance of integrated circuits. In an MPGA, the customer must design to
`worst-case process characteristics. The chips that meet "typical" specifications rather
`than "worst-case" specifications are approximately twenty percent faster. FPGA man(cid:173)
`ufacturers can separate the fast parts from the slow ones in a process called speed bin(cid:173)
`ning. Slower parts sell for lower price. Faster parts allow designers to design to the
`high-end of the process variation, giving FPGA users a price/performance trade-off
`that MPGA designers do not have.
`
`Volume
`
`Unplanned
`Upside
`
`Time
`
`Figure l.6. Generic Product Life Cycle (source: Xilinx).
`
`

`

`8
`
`FPGA Technology
`
`Life Cycle Advantages
`
`The life of a product does not end when the design of a chip inside it is finished. Fig(cid:173)
`ure 1.6 shows a typical product life cycle plotted as volume versus time. When the
`design is complete, there is a ramp-up into production. This ramp-up may include a
`few prototypes or larger pilot manufacturing runs. During production, a design may
`have periods of increased or decreased sales. At the end of a product lifetime, produc(cid:173)
`tion tapers off.
`
`MPGA are only cost effective when ordered in volume, and the volume must be
`decided months in advance of delivery due to long manufacturing cycle times. An
`MPGA user must maintain a sufficient inventory to handle upturns, and is left with
`excess inventory should sales fail to meet expectations. At the end of a product life(cid:173)
`time, MPGA users are faced with a last-purchase decision that must be made months
`in advance of the end-of-product date. If they order too many parts, they are left with
`unusable parts in inventory, if they order too few, they may not have enough parts to
`build the last few systems.
`
`The cost-effectiveness of FPGAs in low volume and the flexibility provided by field(cid:173)
`programmability provide advantages over all phases of product lifetime. When intro(cid:173)
`ducing a product, an FPGA user may order a few parts at a time while testing the
`design for functionality and the product for market viability. During production, the
`FPGA user can accommodate rapid changes in sales easily because long lead times
`are not required. An FPGA user can make product enhancements by shipping an
`upgraded design on the same FPGA device. This upgrade requires no inventory
`changes, no new hardware and does not interrupt production.
`
`1.4. Disadvantages of FPGAs
`
`FPGAs have on-chip programming overhead circuitry that manages the programming
`of the part. The area of the programming overhead cannot be used by customers, and
`lowers the FPGA gate density. The programmable switches and options in an FPGA
`are larger than the mask programming that can be built in an MPGA. The programma(cid:173)
`ble switches also increase signal delay by adding resistance and capacitance to inter(cid:173)
`connect paths. As a result, FPGAs are larger and slower than equivalent MPGAs.
`
`Chip Size and Cost
`
`The area penalty for field-programmability is significant. Current FPGAs are about
`ten times larger for the same gate capacity as the equivalent MPGA, and are corre(cid:173)
`spondingly more expensive on a per-chip basis.
`
`Because of the overhead of field programmability, current-generation FPGAs are lim(cid:173)
`ited to tens of thousands of gates of capacity, while the largest MPGAs are hundreds
`of thousands of gates. For large designs, designers must either split the design into
`several FPGAs or they must move the design to an MPGA. Multiple-chip partitioning
`
`

`

`Introduction
`
`9
`
`Total
`Project
`Cost
`
`MPGA t
`
`NRE
`
`L-__________ ~ __________ _L_
`
`10k
`Project Volume
`
`20k
`
`Figure 1.7. Cost Versus Volume for MPGAs vs. FPGAs (source:
`Xilinx).
`
`for FPGA designs is available, but still relatively immature.
`
`Figure l.7 shows a cost comparison of MPGAs against FPGAs over a range of vol(cid:173)
`ume for the parts. At some point the initial cost savings from the lack of NRE charge
`with FPGAs is consumed by the increased per-chip costs. That crossover point for a
`five-thousand-gate part is currently above ten thousand units. Designs with greater
`volume are more cost effective using an MPGA, despite the greater start-up costs.
`
`Speed of Circuitry
`
`The connection paths in an FPGA are slowed by the programming circuitry. Program(cid:173)
`mable interconnection points along a wiring path add resistance to the path. All pro(cid:173)
`gramming points in the interconnect add capacitance to the internal paths. Finally,
`since more area is required for the same amount of logic, interconnect lines between
`logic are longer. Longer lines have greater resistance and capacitance, further slowing
`the resulting circuitry. Current FPGAs are two to three times slower than MPGAs and
`it is unlikely that they will ever equal MPGA performance on the same manufacturing
`process.
`
`Design Methodology
`
`FPGAs have been criticized because they are too easy to use, thereby encouraging a
`"try-it-and-see-what-happens" methodology for logic design. If these "sloppy" design
`practices result in poor-quality designs, the resulting products will be inferior.
`
`

`

`10
`
`FPGA Technology
`
`1.5. Technology 'fiends
`
`This section examines the relative performance of FPGAs and MPGAs in the context
`of advancing process technology.
`
`Density
`
`In ASIC terminology, density is the amount of logic that can fit on a chip. The pro(cid:173)
`gramming overhead of FPGAs dictates that, for the same amount of logic, FPGAs
`will always be larger and therefore more expensive than MPGAs. However, many
`MPGA designs are pad limited -- the size of the die is dictated not by the number of
`gates that can be placed in the area, but by the number of I/O pads that surround those
`gates. Since I/O pads are placed on the periphery, they scale linearly with feature size
`as a result of improved IC manufacturing processes, while t