(19) Japan Patent Office (JP)
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`(12) Unexamined Patent Application
`Publication (A)
`Japanese Patent Laid-Open No. H9-121153
`(43) Publication date May 6, 1997
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`(11) Japanese Unexamined
`Patent Application Publication
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`(51) Int.Cl.6
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`H03K
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`19/177
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`Identification
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`JPO file
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`9199-5K
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`FI
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`H03K
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`19/0952
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`101
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`9199-5K
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`19/173
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`23/64
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`Request for examination
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`Technical indications
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`19/177
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`19/173
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`23/64
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`101
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`A
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`Z
`19/094
`Not requested Number of claims 5
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` (15
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`pages in total)
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`(21) Application Number Japanese Patent Application
`No. H7-300582
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`(22) Application Filing Date October 25, 1995
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`(71) Applicant 000004226
`Nippon Telegraph and Telephone Corporation
`19-2, Nishi-shinjuku 3-chome, Shinjuku, Tokyo
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`(72)
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`(72) Inventor Fujii Koji
`1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo
`Nippon Telegraph and Telephone Corporation
` Inventor Urano Masami
`1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo
`Nippon Telegraph and Telephone Corporation
`Patent attorney
` Shinichi Kawakubo
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`(74) Agent
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`(54) (Title of the Invention) Programmable Logic Element
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`PL1: programmable logic element
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`(57) (Abstract)
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`(PROBLEM TO BE SOLVED) The objective is to provide a
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`programmable logic element capable of efficiently realizing a
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`desired logic function by using fewer logic elements and less
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`memory according to the logic function to be realized.
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`(SOLUTION) A plurality of selection circuits in a logic
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`element are connected to different memory circuits, and are
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`divided into a plurality of selection circuits each having a
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`smaller number of inputs than the number of inputs of the
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`logic element, and a plurality of logic functions having inputs
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`less than the number of inputs of the logic element are
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`simultaneously assigned to one logic element.
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`Intel Exhibit 1005
`Intel v. Iida
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`1
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`(Scope of Patent Claims)
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`(Claim 1) A programmable logic element, where at least K input
`signals are input, [the element] is provided with 2K memory circuits,
`outputs at least one output signal, inputs at least one control signal,
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`(2)
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`2
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`Japanese Patent Laid-Open No. H9-121153
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`(0003) FIG. 22 is a diagram showing a configuration example of an
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`FPGA (Field Programmable Gate Array), which is a conventional
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`RAM-type programmable LSI.
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`(0004) In the SRAM type programmable LSI shown in FIG. 22, a
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`and has at least one selection circuit, characterized in that the
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`user can set the function by a signal written in the SRAM cell. In
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`following operations are switched by the above control signal: a first
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`other words, the user divides a desired logic function into logic
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`operation of using the K input signals, among the above input
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`functions that can be realized by programmable logic elements,
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`signals, as the selection signal of the selection circuit, selecting one
`output signal from the output signals from the 2K memory circuits,
`and outputting the selected output signal as an output signal of the
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`programmable logic element; a second operation of selecting one
`output signal from the output signals of the 2Xi memory circuits and
`outputting the selected output signal as an output signal of the
`programmable logic element, by dividing 2K memory circuits into
`plural memory circuit groups, where the sequence from i=1 to i=n of
`the sequence {2Xi} (2Xi≦2Xi+1) is equal to 2K, the memory circuit
`group is composed of 2Xi (i=1, 2, …, n) memory circuits, and Xi
`input signals that do not overlap each other among the input signals
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`are used as selection signals.
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`
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`assigns the divided logic functions to the respective logic elements
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`PL11 arranged in an array, and arranges and routes them. A desired
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`LSI is completed by executing a series of these operations using a
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`CAD tool and writing the program data thus obtained into the
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`SRAM cells.
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`(0005) Although the configuration of the logic element PL11 varies
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`depending on the manufacturer, a circuit element characterized by
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`the number of inputs K called a LUT (Look Up Table) is mainly
`used. The K-input, 1-output LUT is a 2K-word, 1-bit memory, and
`by rewriting the contents of the internal SRAM, it is possible to
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`implement an arbitrary logic function with K inputs and 1 output. On
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`the FPGA, a plurality of LUTs having the same number of inputs are
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`arranged in an array, and the number of inputs of the LUT is often 3-
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`(Claim 2) The programmable logic element according to claim 1,
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`5.
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`characterized in that the second operation is two or more operations
`when the sequence {2Xi} is different from each other, and at least
`three operations, that is, the first operation, and at least two second
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`(0006)
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`(Problem to Be Solved by the Invention) Assume an FPGA in which
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`K-input LUTs are used as programmable logic elements and a
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`operations, are switched by the control signal.
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`plurality of these LUTs are arranged in an array. Each K-input LUT
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`(Claim 3) The programmable logic element according to claim 1,
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`is not necessarily assigned a logic function with K inputs. That is, if
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`characterized in that the second operation is an operation in the case
`where the sequence {2Xi} is of one type, and the two operations, the
`first operation and the second operation, are switched by the control
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`signal.
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`(Claim 4) The programmable logic element according to claim 1,
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`we assign to a K-input LUT a logic function whose actual number of
`inputs i is less than K, only 2i bits of memory are used to store the
`program that implements the above logic function, and therefore, (2K
`-2i) bits of memory remain in the LUT as memory not used for the
`above program (invalid memory).
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`characterized in that input/output terminals are provided by the
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`(0007) FIG. 23 is a block diagram showing an example of a
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`conventional SRAM type programmable logic element, showing an
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`example of a programmable logic element PL11 in which the
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`number of inputs K of the programmable logic element is K=3 and
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`the number of inputs i of the actually assigned logic function is i=2.
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`(0008) In the conventional example shown in FIG. 23, four
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`memories exist as invalid memories, these invalid memories,
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`although occupy a predetermined area, do not contribute to the
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`function of the LSI, so the logic element PL11 having such invalid
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`memories causes a problem of lowering the degree of integration.
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`maximum number of input terminals and output terminals that
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`change with the switching of the operation, and along with the
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`switching of the operation, the switching of the operations is
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`executed while sharing the input/output terminals.
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`(Claim 5) The programmable logic element according to claim 4,
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`characterized in that input/output terminals that are not used for
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`setting logic functions are used as part of the wiring that passes
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`through the programmable logic elements.
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`(Detailed Description of the Invention)
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`(0001)
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`(Technical field to which the invention belongs) The present
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`invention relates to a programmable logic element, which is a unit
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`for implementing logic functions in a programmable LSI whose
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`logic functions can be programmed by a user.
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`(0002)
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`(Conventional Art) A programmable LSI is an LSI whose logic
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`functions can be programmed by a user, consists of logic elements
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`that implement logic functions and wiring areas that interconnect
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`these logic elements, wherein the logic element can be set to a
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`desired logic function by program; and the logical elements can be
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`connected with a desired route.
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`3
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`(3)
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`4
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`(0009) The present invention, when realizing the desired logic
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`(i) a first operation of using the K input signals as the selection
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`function, is to provide a programmable logic element capable of
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`efficiently realizing a desired logic function by using fewer logic
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`elements and less memory according to the logic function to be
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`signal of the selection circuit, selecting one output signal from the
`output signals from 2K memory circuits, and outputting the selected
`output signal as an output signal of the programmable logic element;
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`Japanese Patent Laid-Open No. H9-121153
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`realized.
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`(0010)
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`(Means for Solving the Problem) The present invention is that in
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`which a plurality of selection circuits in a logic element are
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`connected to different memory circuits, and are divided into a
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`plurality of selection circuits each having a smaller number of inputs
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`than the number of inputs of the logic element, and a plurality of
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`logic functions having inputs less than the number of inputs of the
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`logic elements are simultaneously assigned to one logic element.
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`(0011)
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`and
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`(ii) a second operation of selecting one output signal from the output
`signals of the 2Xi memory circuits and outputting the selected output
`signal as an output signal of the programmable logic element, by
`dividing the 2K memory circuits into plural memory circuit groups,
`where the sequence from i=1 to i=n of the sequence {2Xi}
`(2Xi≦2Xi+1) is equal to 2K, the memory circuit group is composed of
`2Xi (i=1, 2, …… n) memory circuits, and Xi input signals that do not
`overlap each other among the input signals are used as selection
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`signals. Note that the programmable logic element PL1 is K=4, with
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`(Embodiments and Examples of the Invention) FIG. 1 is a block
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`16 memory circuits, and the second operation is divided into two
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`diagram showing a programmable logic element PL1, which is the
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`operations; in the first operation in the second operation, n=2, X1=3,
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`first embodiment of the invention.
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`X2=3, in the second operation in the second operation, n=2, X1=3,
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`(0012) The programmable logic element PL1 switches between the
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`X2=2, X3=2. That is, the programmable logic element PL1 switches
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`following operations by two control signals:
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`one operation among three operations, the first operation, the first
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`(i) an operation of selecting one output signal from the output signals
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`operation of the second operation, and the second operation of the
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`of the 16 memory circuits and outputting the selected output signal
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`second operation.
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`as the output signal of the programmable logic element PL1; and
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`(0015) Specifically, the programmable logic element PL1 includes
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`(ii) an operation of outputting the selected output signal of the
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`memory circuits cell 00 to cell 15, selectors x00 to x14, selectors
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`memory circuit as the output signal of the programmable logic
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`x16 to x20, x31, x32, CMOS transfer gates x22, x23, control circuits
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`element PL1 (n=2, X1 =3, X2 =3), where this one memory circuit is
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`x15, x21, and inverters x2 4 to x30.
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`selected from each memory circuit after dividing the 16 memory
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`(0016) FIG. 2 is a circuit diagram showing a concrete example of the
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`circuits into two memory circuit groups each composed of 8 memory
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`selector x16 in the programmable logic element PL1.
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`circuits, selecting 3 input signals and 3 input signals that do not
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`(0017) The selector x16 has one selection signal input terminal S,
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`overlap each other from 7 input signals, and as the selection signal
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`two input terminals in1 and in2, and an output terminal out. Specific
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`examples of other selectors x17 to x20, x31, and x32 are the same as
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`the selector x16.
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`(0018) FIG. 3 is a circuit diagram showing a concrete example of the
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`control circuit x15 in the programmable logic element PL1.
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`(0019) The control circuit x15 is a circuit that renders the
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`input/output terminals of the selector x12 non-conductive regardless
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`of the selection signal. The specific example of the control circuit
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`x21 is the same as the specific example of the control circuit x15,
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`and the control circuit x21 is a circuit that makes the input/output
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`terminal of the selector x14 non-conductive regardless of the
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`selection signal.
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`(0020) FIG. 4 is a circuit diagram showing a specific example in
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`which the selector x00 in the programmable logic element PL1 is
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`composed of CMOS.
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`(0021) The selector x00 has two selection signal input terminals S1
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`and S2, two input terminals in1 and in2, and an output terminal out.
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`for selecting a predetermined memory circuit from each memory
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`circuit group, applying the selected three input signals to each
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`memory circuit group; and
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`(iii) an operation of outputting the output signal of the selected
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`memory circuit as the output signal of the programmable logic
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`element PL1 (n=3, X1 =3, X2 =2), where this one memory circuit is
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`selected from each memory circuit after dividing the 16 memory
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`circuits into three memory circuit groups each composed of 8, 4, and
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`4 memory circuits, selecting 3 input signals, 2 input signals, and 2
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`input signals that do not overlap each other from 7 input signals, and
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`as the selection signal for selecting a predetermined memory circuit
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`from each memory circuit group, applying the selected three, two,
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`two input signals to each memory circuit group.
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`(0013) The programmable logic element PL1 has up to seven input
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`terminals used and up to three output terminals, changes the number
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`of input terminals and output terminals used, by switching between
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`the above three actions, selects, in each operation, the input terminal
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`from seven input terminals and the output terminal from three output
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`terminals, and prevents an increase in the number of terminals by
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`sharing input/output terminals between patterns that do not operate
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`simultaneously.
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`(0014) That is, the programmable logic element PL1 wherein more
`than K input signals are input, [the element] is provided with 2K
`memory circuits, outputs at least one output signal, inputs at least
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`one control signal, and has at
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`least one selection circuit,
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`characterized in that the following operations are switched by the
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`above control signal:
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`5
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`(4)
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`Japanese Patent Laid-Open No. H9-121153
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`6
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`(0022) A specific example of the selectors x01 to x14 constructed of
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`(0030) The output terminal o1 of the control circuit X21 is
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`CMOS is the same as the specific example of the selector x00
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`constructed of CMOS. The selectors x01 to x14 have two selection
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`signal input terminals S1 and S2, two input terminals in1 and in2,
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`and an output terminal out.
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`(0023) FIG. 5 is a circuit diagram showing a specific example when
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`the selector x00 (to x14) in the programmable logic element PL1 is
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`composed of nMOS. A specific example in which the selectors x01
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`to x14 are configured by nMOS is the same as the specific example
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`in which the selector x00 is configured by nMOS.
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`(0024) The selector x16 has its selection signal input terminal S
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`input with a control signal A, and its input terminals in1 and in2
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`input with signals b and d, respectively, with its output terminal out
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`connected to the selection signal input terminal S2 of the selector
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`x09, and further connected to the selection signal input terminal S1
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`of the selector x09 via the inverter x28.
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`(0025) The selector x17 has its selection signal input terminal S
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`input with a control signal A, and its input terminals in1 and in2
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`input with signals a and c, respectively, with its output terminal out
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`connected to the selection signal input terminal S2 of the selector
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`x14, the output terminal o2 is connected to the selection signal input
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`terminal S1 of the selector x14, where the signal d is input to the
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`input terminal in1, and a control signal B is input to the input
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`terminal in2. Also, the input signal b is input to the selection signal
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`input terminal S2 of the selector x08, and is input to the selection
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`signal input terminal S1 via the inverter x27. Also, the input signal a
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`is input to the selection signal input terminal S2 of the selectors x02,
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`x03, and is input to the selection signal input terminal S1 of the
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`selectors x02, x03 via the inverter x25.
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`(0031) The selector x00 has its input terminals in1 and in2 connected
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`to the output terminals of the memory circuits cell00 and cell01,
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`respectively, and its output terminal out connected to the input
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`terminal in1 of the selector x08. The selector x01 has its input
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`terminals in1 and in2 connected to the output terminals of the
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`memory circuits cell02 and cell03, respectively, and its output
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`terminal out connected to the input terminal in2 of the selector x08.
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`connected to the selection signal input terminal S2 of the selector
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`The selector x02 has its input terminals in1 and in2 connected to the
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`x00 and x01, and further connected to the selection signal input
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`output
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`terminals of
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`the memory circuits cell04 and cell05,
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`terminal S1 of the selectors x00 and x01 via the inverter x24.
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`respectively, and its output terminal out connected to the input
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`(0026) The selector x18 has its selection signal input terminal S
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`terminal in1 of the selector x09.
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`input with a control signal B, and its input terminals in1 and in2
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`(0032) The selector x03 has its input terminals in1 and in2 connected
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`input with signals a and e, respectively, with its output terminal out
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`to the output terminals of the memory circuits cell06 and cell07,
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`respectively, and its output terminal out connected to the input
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`terminal in2 of the selector x09. The selector x04 has its input
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`terminals in1 and in2 connected to the output terminals of the
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`memory circuits cell08 and cell09, respectively, and its output
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`terminal out connected to the input terminal in1 of the selector x10.
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`The selector x05 has its input terminals in1 and in2 connected to the
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`output
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`terminals of
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`the memory circuits cell10 and cell11,
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`respectively, and its output terminal out connected to the input
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`terminal in2 of the selector x10.
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`(0033) The selector x06 has its input terminals in1 and in2 connected
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`to the output terminals of the memory circuits cell12 and cell13,
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`respectively, and its output terminal out connected to the input
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`terminal in1 of the selector x11. The selector x07 has its input
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`terminals in1 and in2 connected to the output terminals of the
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`memory circuits cell14 and cell15, respectively, and its output
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`terminal out connected to the input terminal in2 of the selector x11.
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`The output terminal of the selector x08 is connected to the input
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`terminal in1 of the selector x12, and is connected to the input
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`terminal in2 of the selector x31 via the CMOS transfer gate x22.
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`(0034) The output terminal of the selector x09 is connected to the
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`input terminal in2 of the selector x12 and the input terminal in2 of
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`the selector x32, the output terminal of the selector x10 is connected
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`to the input terminal in1 of the selector x13, and the output terminal
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`of the selector x11 is connected to the input terminal in2 of the
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`selector x13. The output terminal of the selector x12 is connected to
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`the input terminal in1 of the selector x14 and to the input terminal
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`in2 of the selector x31. The output terminal of the selector x13 is
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`connected to the input terminal in2 of the selector x14, and further
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`connected to the selection signal input terminal S2 of the selectors
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`x04, x05, x06, x07, and further connected to the selection signal
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`input terminal S1 of the selectors x04, x05, x06, and x07 via the
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`inverter x26.
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`(0027) The selector x19 has its selection signal input terminal S
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`input with a control signal B, and its input terminals in1 and in2
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`input with signals b and f, respectively, with its output terminal out
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`connected to the selection signal input terminal S2 of the selectors
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`x10, x11, and further connected to the selection signal input terminal
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`S1 of the selectors x10, x11 via the inverter x29.
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`(0028) The selector x20 has its selection signal input terminal S
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`input with a control signal B, and its input terminals in1 and in2
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`input with signals c and g, respectively, with its output terminal out
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`connected to the selection signal input terminal S2 of the selector
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`x13, and further connected to the selection signal input terminal S1
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`of the selector x13 via the inverter x30.
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`(0029) The output terminal o1 of the control circuit X15 is
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`connected to the selection signal input terminal S2 of the selector
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`x12, the output terminal o2 is connected to the selection signal input
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`terminal S1 of the selector x12, where the signal c is input to the
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`input terminal in1, and a control signal A is input to the input
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`terminal in2.
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`connected to the output terminal out3 via the CMOS transfer gate
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`x23. The output terminal of the selector x14 is connected to the
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`output terminal out3.
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`(0035) A control signal A is input to the control terminal of the
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`CMOS transfer gate x22, and a control signal B is input to the
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`control terminal of the CMOS transfer gate x23. The selector x31
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`Japanese Patent Laid-Open No. H9-121153
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`8
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`(5)
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`(0040) At this time, the selection circuit composed of the selectors
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`x00 to x14 becomes a 16-1 selector using the signals a, b, c, and d as
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`selection signals, and the output terminal out3 corresponds to the
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`output terminal of a four-input programmable logic element having
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`has its selection signal input terminal S input with the control signal
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`the signals a, b, c, and d as input signals.
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`B, its input terminal in1 input with the signal e, with its input
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`(0041) Here, among the terminals not used as the input/output
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`terminal in2 connected to the output terminal out of the selector x12,
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`terminals of the programmed logic function, the input terminals e
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`and its output terminal out connected to the output terminal out1.
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`and f are connected to the output terminals out1 and out2 by the
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`The selector x32 has its selection signal input terminal S input with
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`selectors x31 and x32, respectively. Therefore, these input terminals
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`the control signal B, its input terminal in1 input with the signal f,
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`e and f and the output terminals out1 and out2 can be used as wiring
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`where its input terminal in2 connected to the output terminal out of
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`elements.
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`the selector x09, and its output terminal out connected to its output
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`(0042) Next, as shown in FIG. 6(3), if the control signals (A, B) are
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`terminal out2. The selection circuit is configured based on a selector
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`(1, 0), the signal a and its negation are selected as selection signals
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`using a transfer gate, and the transfer gate uses the CMOS
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`for the selectors x00, x01, 02 and 03, the signal b and its negation
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`configuration shown in FIG. 4 or the NM0S configuration shown in
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`are selected as selection signals for the selectors x08 and x09, the
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`FIG. 5.
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`signal c and its negation are selected as the selection signal of the
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`(0036) The operation of programmable logic element PL1 will now
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`selector x12, the output terminal of the selector x08 and the output
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`be described.
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`terminal of the selector x12 are separated by a CMOS transfer gate
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`(0037) FIG. 6 is a diagram showing the correspondence between
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`x22, and the selector x13 connects the output terminal of the selector
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`input and output signals in the programmable logic element PL1 and
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`x12 to the output terminal out1. The signal e and its negation are
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`output signals of the memory circuit.
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`selected as the selection signals of the selectors x04, x05, x06 and
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`(0038) In FIG. 6, A and B are control signals for determining the use
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`x07, the signal f and its negation are selected as the selection signals
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`mode of the programmable logic circuit PL1; a, b, c, d, e, f and g are
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`of the selectors x10 and x11, the signal g and its negation are
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`signals to be input; out1 , out2 and out3 indicate output terminals to
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`selected as the selection signal of the selector x13, the output
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`be output, and cell00 to cell15 indicate memory circuits to be used.
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`terminal of the selector x13 and the output terminal out3 are
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`50
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`conducted by a CMOS transfer gate x23. The control circuit x21
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`disconnects the input terminal of the selector x14 from its output
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`terminal.
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`(0043) At this time, the selection circuit constituted by the selectors
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`x00, x01, x02, 03, x08, x09, and x12 becomes an 8-1 selector using
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`the signals a, b, and c as the selection signals, and the output
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`terminal out1 corresponds to the output terminal of a four-input
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`programmable logic element having signals a, b, and c as input
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`signals, and output terminal out1 acts as the output terminal of the
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`four-input programmable logic element.
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`(0044) A selection circuit composed of selectors x04, x05, x06, x07,
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`x10, x11 and x13 is an 8-1 selector using signals e, f and g as
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`selection signals, the output terminal out3 corresponds to the output
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`terminal of the three-input programmable logic element having the
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`signals e, f, and g as input signals, and the output terminal out3 acts
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`as the output terminal of the three-input programmable logic
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`element.
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`(0045) Then, as shown in FIG. 6(2), if the control signals (A, B) are
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`(0, 0), the signal c and its negation are selected as the selection
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`signals of the selectors x00 and x01, the signal b and its negation are
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`selected as the selection signal of the selector x08, and a selection
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`circuit composed of selectors x00, x01, and x08 becomes a 4-1
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`selector using signals b and c as selection signals.
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`(0039) First, as shown in FIG. 6(1), when the control signals (A, B)
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`are (1, 1), signal a and its negation are selected as selection signals
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`for selectors x00, x01, x02, x03, x04, x05, x06, and x07, the signal b
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`and its negation are selected as selection signals for the selectors
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`x08, x09, x10 and x11, the signal c and its negation are selected as
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`selection signals for the selectors x12 and x13, and the signal d and
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`its negation are selected as selection signals for the selector x14. The
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`control circuits x15 and x21 enable the selectors x12 and x14 to
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`operate as selection circuits, respectively. The CMOS transfer gate
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`x22 separates the output terminal of the selector x08 from the output
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`terminal of the selector x12, and the CMOS transfer gate x23
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`separates the output terminal of the selector x13 from the output
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`terminal out 3.
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`9
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`(6)
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`Japanese Patent Laid-Open No. H9-121153
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`10
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`(0046) The signal a and its negation are selected as the selection
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`(0052) In the programmable logic element PL1, the second operation
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`signals of the selectors x02 and x03, the signal d and its negation are
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`is composed of two kinds of operations as shown in FIGS. 6(2) and
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`selected as the selection signal of the selector x09, and a selection
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`circuit composed of selectors x02, x03, and x09 becomes a 4-1
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`selector using signals a and d as selection signals. The signal e and
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`6(3), but it may be composed of at least three operations (at least
`three operations in which the series {2xi} differs from each other).
`(0053) FIG. 8 is a block diagram showing programmable logic
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`its negation are selected as the selection signals of the selectors x04,
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`element PL2, which is the second embodiment of the present
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`x05, x06 and x07, the signal f and its negation are selected as
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`invention.
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`selection signals for the selectors x10 and X11, the signal g and its
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`(0054) The programmable logic element PL2 switches between the
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`negation are selected as selection signals for the selector x13, and a
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`following operations by one control signal:
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`selection circuit composed of selectors x04, x05, x06, x07, x10, x11,
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`(i) an operation of selecting one output signal from the output signals
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`and x13 becomes an 8-1 selector using signals e, f, and g as selection
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`of the 16 memory circuits and outputting the selected output signal
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`signals.
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`as the output signal of the programmable logic element PL2; and
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`(0047) The input terminal and output terminal of the selector x12 are
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`(ii) an operation of outputting the selected output signal of the
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`insulated by a control circuit x15; the output terminal of the selector
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`memory circuit as the output signal of the programmable logic
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`x08 is electrically connected to the output terminal out1 by the
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`element PL2 (n=2, X1 =3, X2 =3), where this one memory circuit is
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`CMOS transfer gate x22 and the selector x31; and the output
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`selected from each memory circuit after dividing the 16 memory
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`terminal of the selector x09 is connected to the output terminal out2
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`circuits into two memory circuit groups each composed of 8 memory
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`by the selector x32. The input terminal and the output terminal of the
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`circuits, selecting 3 input signals and 3 input signals that do not
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`selector x14 are insulated by the control circuit x21, and the output
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`overlap each other from 6 input signals, and as the selection signal
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`terminal of the selector x13 is connected to the output terminal out3
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`for selecting a predetermined memory circuit from each memory
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`by the CMOS transfer gate x23.
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`circuit group, applying the selected three input signals to each
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`(0048) At this time, the output terminal out1 corresponds to the
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`memory circuit group. Note that K=4 and 16 memory circuits in the
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`output of a two-input programmable logic element having the signals
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`programmable logic element PL2.
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`b and c as input signals; the output terminal out2 corresponds to the
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`(0055) The programmable logic element PL2 has up to six input
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`terminals used and up to two output terminals, changes the number
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`of input terminals and output terminals used, by switching between
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`the above two operations, selects, in each operation, the input
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`terminal from six input terminals and the output terminal from two
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`output terminals, and prevents an increase in the number of terminals
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`by sharing input/output terminals between patterns that do not
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`operate simultaneously.
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`(0056) FIG. 9 is a circuit diagram showing a concrete example of the
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`selector x16 in the programmable logic element PL2. A specific
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`example of the selector x16 is the same as the specific example of
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`the selector x16 shown in FIG. 2, and so are the selectors x17, x18,
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`and x26.
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`(0057) FIG. 10 is a circuit diagram showing a concrete example of
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`the control circuit x15 in the programmable logic element PL2.
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`Control circuit x15 in programmable logic element PL2 is the same
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`as the specific example of control circuit x15 shown in FIG. 3.
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`(0058) FIG. 11 is a circuit diagram showing a specific example in
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`which the selector x00 in the programmable logic element PL2 is
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`composed of CMOS. FIG. 12 is a circuit diagram showing a specific
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`example in which the selector x00 in the programmable logic
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`element PL2 is composed of nMOS.
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`output terminal of a two-input programmable logic element having
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`the signals a and d as input signals; and the output terminal out3
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`corresponds to the output of a three-input programmable logic
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`element having signals e, f, and g as input signals.
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`(0049) FIG. 7 is a diagram showing a logical expression of a
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`corresponding output signal when a certain signal is written in the
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`memory circuit in programmable logic element PL1.
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`(0050) When a
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`two-input
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`logic function
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`is assigned
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`to a
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`conventional four-input programmable logic element, the remaining
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`memory circuits other than the 4-bit memory circuit required for
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`programming are unused, which was one of the causes of lowering
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`the degree of integration. In the programmable logic element PL1,
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`however, the remaining memory circuits can also be effectively used
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`for assignment of other logic functions.
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`(0051) That is, the programmable logic element PL1 switches
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`between the first operation and the second operation. The second
`operation in this case is an operation when the sequence {2Xi} is of
`two or m