`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`______________________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`______________________________
`INTEL CORPORATION,
`Petitioner,
`
`v.
`
`MASAHIRO IIDA,
`Patent Owner.
`
`______________________________
`
`Case No. IPR2023-00864
`U.S. Patent No. 6,812,737
`______________________________
`
`
`DECLARATION OF STEPHEN W. MELVIN, PH.D.
`
`
`
`
`1
`
`Intel Ex. 1003
`Intel v. Iida
`
`

`

`
`
`TABLE OF CONTENTS
`
`PERSONAL AND PROFESSIONAL BACKGROUND ................................. 1
`I.
`A.
`Education ............................................................................................... 2
`B.
`Career Synopsis ..................................................................................... 2
`II. MATERIALS REVIEWED AND CONSIDERED ........................................... 4
`III. MY UNDERSTANDING OF PATENT LAW ................................................. 8
`A. Anticipation .........................................................................................10
`B.
`Obviousness .........................................................................................10
`IV. PERSON OF ORDINARY SKILL IN THE ART ..........................................13
`V. BACKGROUND OF PROGRAMMABLE LOGIC DEVICES AND LOOK-
`UP TABLES ..................................................................................................16
`A. Digital Circuits ....................................................................................16
`B.
`Look-Up Tables ...................................................................................19
`C.
`Overview of Programmable Logic Devices ........................................26
`VI. THE ’737 PATENT .........................................................................................31
`A.
`Preferred Embodiments .......................................................................31
`B.
`Prosecution History .............................................................................36
`C.
`The Challenged Claims .......................................................................37
`VII. CLAIM INTERPRETATION ..........................................................................39
`A.
`“look up table of M inputs and N outputs” .........................................41
`B.
`“LUT units” .........................................................................................43
`VIII. GROUND 1 ......................................................................................................44
`A. Overview of Fujii and Betz .................................................................44
`1.
`Fujii (Ex.1005) ..........................................................................44
`2.
`Betz (Ex.1006) ..........................................................................46
`B.
`Independent Claim 1 ...........................................................................47
`1.
`comprising” ...............................................................................47
`2.
`[1A] “a plurality of LUT units; and” ........................................52
`
`[1PRE] “A look up table of M inputs and N outputs,
`
`
`
`i
`
`

`

`[1B] “an internal configuration control circuit controlling an
`
`[1C] “wherein said internal configuration control circuit
`comprises a plurality of selectors selecting I/O signals of said
`
`[1D] [wherein said internal configuration control circuit
`comprises . . . ] “a selector control circuit having a memory,
`controlling said plurality of selectors in accordance with data
`stored in said memory, and defining the internal configuration
`
`[2A] “The look up table as claimed in claim 1, wherein said
`plurality of selectors include: an input signal selector provided
`at an input of at least one of said LUT units to select an input
`
`[2B] [wherein said plurality of selectors include: . . .] “an
`output signal selector provided at an output of said LUT units
`
`[2C] “said input signal selector and said output signal selector
`being controlled in accordance with the data stored in said
`
`3.
`internal configuration of said plurality of LUT units,”.............60
`4.
`plurality of LUT units, and” ......................................................69
`5.
`of said plurality of LUT units.” ................................................73
`Claim 2 ................................................................................................81
`1.
`signal; and” ...............................................................................81
`2.
`selecting an output signal,” .......................................................82
`3.
`memory.” ...................................................................................83
`Claim 3 ................................................................................................84
`1.
`signal; and” ...............................................................................84
`2.
`selecting an output signal,” .......................................................84
`3.
`being controlled in accordance with the input signal.”.............85
`table.”...................................................................................................88
`
`[3A] “The look up table as claimed in claim 1, wherein said
`plurality of selectors include: an input signal selector provided
`at an input of at least one of said LUT units to select an input
`
`[3B] [wherein said plurality of selectors include: . . .] “an
`output signal selector provided at an output of said LUT units
`
`[3C] “said input signal selector and said output signal selector
`
`Claim 4: “The look up table as claimed in claim 1, wherein said look
`up table of M inputs and N outputs is a 6-input 3-output look up
`
`C.
`
`D.
`
`E.
`
`
`
`ii
`
`

`

`F.
`G.
`
`H.
`
`Claim 5: “The look up table as claimed in claim 4, wherein said 6-
`input 3-output look up table comprises eight 3-input 1-output LUT
`
`[7B] “a plurality of routing wires connected to each of said
`
`[7C] “a plurality of switch circuits provided at an intersection
`
`[7D] “a plurality of connection blocks provided between an I/O
`line of each of said logic blocks and each of said routing wires;
`
`[7E] “an I/O block performing an input/output operation with
`
`[7F] “wherein each of said logic blocks has a look up table of
`
`units.”...................................................................................................92
`Independent Claim 7 ...........................................................................95
`1. Motivation to Combine the Fujii-Betz PL1 with Betz’s FPGA
`Architecture ...............................................................................95
`2.
`[7PRE] “A programmable logic circuit device comprising:” ...98
`3.
`[7A] “a plurality of logic blocks;” ............................................99
`4.
`logic blocks;” ..........................................................................101
`5.
`of each of said routing wires;” ................................................102
`6.
`and” .........................................................................................103
`7.
`external equipment,” ...............................................................104
`8.
`M inputs and N outputs, comprising:” ....................................106
`9.
`[7G] “a plurality of LUT units; and” ......................................108
`10.
`internal configuration of said plurality of LUT units,”...........108
`11.
`plurality of LUT units, and” ....................................................108
`12.
`plurality of LUT units.” ..........................................................108
`Claim 8 ..............................................................................................108
`1.
`units to select an input signal; and” ........................................108
`
`[7H] “an internal configuration control circuit controlling an
`
`[7I] “wherein said internal configuration control circuit
`comprises a plurality of selectors selecting I/O signals of said
`
`[7J] “a selector control circuit having a memory, controlling
`said plurality of selectors in accordance with data stored in said
`memory, and defining the internal configuration of said
`
`[8A] “The programmable logic circuit device as claimed in
`claim 7, wherein said plurality of selectors include: an input
`signal selector provided at an input of at least one of said LUT
`
`
`
`iii
`
`

`

`[8B] “an output signal selector provided at an output of said
`
`[8C] “said input signal selector and said output signal selector
`being controlled in accordance with the data stored in said
`
`[9A] “The programmable logic circuit device as claimed
`in claim 7, wherein said plurality of selectors include: an input
`signal selector provided at an input of at least one of said LUT
`
`[9B] “an output signal selector provided at an output of said
`
`[9C] “said input signal selector and said output signal selector
`
`Claim 10: “The programmable logic circuit device as claimed in claim
`7, wherein said look up table of M inputs and N outputs is a 6-input 3-
`
`Claim 11: “The programmable logic circuit device as claimed in claim
`10, wherein said 6-input 3-output look up table comprises eight 3-
`
`[13PRE] “A method of configuring a look up table of M inputs
`
`I.
`
`J.
`K.
`L.
`
`2.
`LUT units selecting an output signal,” ...................................109
`3.
`memory.” .................................................................................109
`Claim 9 ..............................................................................................109
`1.
`units to select an input signal; and” ........................................109
`2.
`LUT units selecting an output signal,” ...................................109
`3.
`being controlled in accordance with the input signal.”...........109
`output look up table.” ........................................................................110
`input 1-output LUT units.” ................................................................110
`Independent Claim 13 .......................................................................110
`1.
`and N outputs, comprising:” ...................................................110
`2.
`[13A] “providing a plurality of LUT units, and” ....................111
`3.
`configuration.” ........................................................................111
`M. Claim 14: “The method of configuring a look up table as claimed in
`corresponding look up table.” ...........................................................111
`N.
`table.”.................................................................................................112
`
`Claim 15: “The method of configuring a look up table as claimed in
`claim 13, wherein an input signal input to at least one of said LUT
`units and an output signal output from said LUT units are selectively
`controlled in accordance with data stored in the orresponding look up
`
`[13B] “selectively controlling I/O signals of said plurality of
`LUT units to set a predetermined mode of an internal
`
`claim 13, wherein the I/O signals of said plurality of LUT units are
`selectively controlled in accordance with data stored in the
`
`
`
`iv
`
`

`

`Claim 16: “The method of configuring a look up table as claimed in
`claim 13, wherein an input signal input to at least one of said LUT
`units and an output signal output from said LUT units are selectively
`controlled in accordance with a predetermined function of the input
`
`O.
`signal.” ...............................................................................................114
`IX. GROUND 2 ....................................................................................................115
`A.
`units.”.................................................................................................115
`B.
`2-output LUT units.” .........................................................................119
`X. GROUND 3 AND GROUND 4 .....................................................................120
`XI. CONCLUSION ..............................................................................................121
`XII. APPENDIX: CLAIM LISTING ....................................................................123
`
`Claim 6: “The look up table as claimed in claim 4, wherein said 6-
`input 3-output look up table comprises four 3-input 2-output LUT
`
`Claim 12: “The programmable logic circuit device as claimed in claim
`10, wherein said 6-input 3-output look up table comprises four 3-input
`
`
`
`
`
`v
`
`

`

`I, Stephen W. Melvin, do hereby declare as follows:
`I have been retained by Munger, Tolles & Olson LLP as counsel for
`1.
`
`Petitioner Intel Corporation to assess claims 1-16 (the “challenged claims”) of U.S.
`
`Patent No. 6,812,737 (“the ’737 patent”). My employer, Exponent, Inc., is being
`
`compensated for my time at my standard rate of $650 per hour, plus actual
`
`expenses. My compensation is not dependent in any way upon any outcome in the
`
`above-captioned proceeding, or any other proceeding, concerning the ’737 patent.
`
`I.
`
`PERSONAL AND PROFESSIONAL BACKGROUND
`2. My qualifications for forming the opinions set forth in this declaration
`
`are summarized below and explained in more detail in my current curriculum vitae,
`
`provided as Exhibit 1004, which also includes a list of my publications and patents.
`
`3.
`
`During my career I have designed and developed Very Large Scale
`
`Integration (“VLSI”) technology, which has included the use of field
`
`programmable gate arrays (“FPGAs”) for prototyping, and I have developed and
`
`deployed embedded systems, which has included the use of programmable logic
`
`circuit devices or programmable logic devices (“PLDs”). As such, I have acquired
`
`expertise and am an expert in the area of PLDs, including those having look-up
`
`table architectures and methods.
`
`
`
`1
`
`

`

`A. Education
`
`4.
`
`In 1982, I obtained a bachelor’s degree in Electrical Engineering and
`
`Computer Science from the University of California, Berkeley. In 1991, I obtained
`
`a Doctor of Philosophy (Ph.D.) degree in Computer Science, also from the
`
`University of California, Berkeley. My dissertation, titled “Performance
`
`Enhancement Through Dynamic Scheduling and Large Execution Atomic Units in
`
`Single Instruction Stream Processors,” related to a high-performance processor
`
`design that exploited fine-grained parallelism in general-purpose programs.
`
`B. Career Synopsis
`
`5.
`
`After obtaining my Ph.D., I led an architecture team designing a
`
`network processor at Clearwater Networks (formerly XStream Logic, Inc.) from
`
`2000-2001. I also co-founded a network processor startup called Flowstorm, Inc.,
`
`(later Consentry Networks) in 2001. Both of those professional experiences
`
`required an understanding of PLDs, as they involved studying the use of PLDs
`
`during prototyping phases.
`
`6.
`
`From 2001-2002, I was a Visiting Scholar at the University of Texas
`
`at Austin, where I conducted research on high performance microprocessor design.
`
`I also served as General Chair of the 45th Annual Symposium in Microarchitecture
`
`in Vancouver, British Columbia, in December 2012.
`
`
`
`2
`
`

`

`7. My practical experience regarding PLDs includes designing and
`
`building numerous real-time embedded systems that have been commercially
`
`deployed, including machine vision systems used in the automotive industry and
`
`voice processing systems.
`
`8.
`
`I am a named inventor of over 40 United States patents in the
`
`computer science field, including patents related to integrated circuits, and I am a
`
`registered patent agent before the United States Patent and Trademark Office.
`
`9.
`
`In addition, on several occasions, I have served as an expert witness in
`
`matters where PLD (including FPGA) design, architecture, and technology
`
`analysis were required to render an opinion. These matters include Mentor
`
`Graphics Corp. v. EVE-USA, Inc., Nos. 3:10-cv-00954, 3:12-01500, 3:13-cv-
`
`00579 (D. Or.), Pact XPP Technologies, AG v. Xilinx, Inc., No. 2:07-cv-563 (E.D.
`
`Tex.), and others.
`
`10.
`
`I am currently employed as a Principal with Exponent, Inc., which is
`
`an international multidisciplinary engineering and scientific consulting firm.
`
`11.
`
`I am a member of The Institute of Electrical and Electronics
`
`Engineers (IEEE) and the Association for Computing Machinery (ACM), the two
`
`largest professional organizations in the field of computer science and electrical
`
`engineering.
`
`
`
`3
`
`

`

`12.
`
`In summary, I have extensive familiarity with the field of PLDs and
`
`FPGAs, including those with look-up tables. As I have been studying and working
`
`in this field since 1982, I am familiar with what the state of this field was at the
`
`effective filing date of the ’737 patent and before.
`
`II. MATERIALS REVIEWED AND CONSIDERED
`13. My findings, as explained below, are based on my years of education,
`
`research, experience, and background in the field of PLDs, as well as my
`
`investigation and study of relevant materials for this declaration. When developing
`
`the opinions set forth in this declaration, I have assumed the perspective of a
`
`person having ordinary skill in the art (“POSA”), as set forth in Section IV below.
`
`In forming my opinions, I have studied and considered the materials identified in
`
`the list below.
`
`Exhibit
`No.
`1001
`1002
`1005
`
`1006
`
`1007
`1008
`1009
`
`Description
`U.S. Patent No. 6,812,737
`Prosecution History of U.S. Patent No. 6,812,737
`Japanese Unexamined Patent Application Publication No. H09-121153A
`(“Fujii”), certified translation, and declaration of translator
`Vaughn Betz et al., Architecture and CAD for Deep-Submicron FPGAs
`(Kluwer Academic Publishers 1999) (“Betz”)
`U.S. Patent No. 6,097,212 (“Agrawal”)
`U.S. Patent No. 5,926,036 (“Cliff”)
`Declaration of Agnes O. Villero Regarding Betz, Brown-FPGA,
`Trimberger, and Bhat
`
`
`
`4
`
`

`

`Exhibit
`No.
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`1018
`
`1019
`
`Description
`Prosecution History of Japanese Patent Application No. 2001-199644
`(which issued as Japanese Patent No. 3580785B2), certified translation,
`and declaration of translator
`Stephen D. Brown et al., Field-Programmable Gate Arrays (Kluwer
`Academic Publishers 1992) (“Brown-FPGA”)
`Stephen M. Trimberger et al., Field-Programmable Gate Array
`Technology (Springer Science+Business Media New York 1994)
`(“Trimberger”)
`Stephen Brown & Jonathan Rose, “FPGA and CPLD Architectures: A
`Tutorial,” IEEE Design and Test of Computers, vol. 13, no. 2, 42-57
`(Dec. 1996) (“Brown-Rose”) (from pages 4-19 of Declaration of Gordon
`MacPherson at Ex.1014)
`Declaration of Gordon MacPherson regarding Stephen Brown &
`Jonathan Rose, “FPGA and CPLD Architectures: A Tutorial,” IEEE
`Design and Test of Computers, vol. 13, no. 2, 42-57 (Dec. 1996)
`Jianshe He & Jonathan Rose, “Advantages of Heterogeneous Logic
`Block Architectures for FPGAs,” Proceedings of IEEE Custom
`Integrated Circuits Conference - CICC ’93 (1993) (“He”) (from pages 4-
`8 of Declaration of Gordon MacPherson at Ex.1016)
`Declaration of Gordon MacPherson regarding Jianshe He & Jonathan
`Rose, “Advantages of Heterogeneous Logic Block Architectures for
`FPGAs,” Proceedings of IEEE Custom Integrated Circuits Conference -
`CICC ’93 (1993) (from pages 4-8 of Declaration of Gordon
`MacPherson)
`Jonathan Rose et al., “Architecture of Field-Programmable Gate
`Arrays,” Proceedings of the IEEE, vol. 81, no. 7, 1013-29 (July 1993)
`(“Rose”) (from pages 4-20 of Declaration of Gordon MacPherson at
`Ex.1018)
`Declaration of Gordon MacPherson regarding Jonathan Rose et al.,
`“Architecture of Field-Programmable Gate Arrays,” Proceedings of the
`IEEE, vol. 81, no. 7, 1013-29 (July 1993)
`Satwant Singh et al., The Effect of Logic Block Architecture on FPGA
`Performance, IEEE Journal of Solid-State Circuits, vol. 27, no. 3, 281-
`
`
`
`5
`
`

`

`Exhibit
`No.
`
`1020
`
`1021
`
`1022
`
`1023
`
`1024
`
`1025
`1026
`
`1027
`
`1028
`
`1029
`
`Description
`87 (Mar. 1992) (“Singh”) (from pages 4-10 of Declaration of Gordon
`MacPherson at Ex.1020)
`Declaration of Gordon MacPherson regarding Satwant Singh et al., The
`Effect of Logic Block Architecture on FPGA Performance, IEEE Journal
`of Solid-State Circuits, vol. 27, no. 3, 281-87 (Mar. 1992)
`Narasimha B. Bhat, “Novel Techniques for High Performance Field
`Programmable Logic Devices,” Technical Report no. UCB/ERL
`M93/80, Electronic Research Laboratory, University of California,
`Berkeley (Nov. 1993) (“Bhat”)
`Donald W. Cherepacha, Master’s Thesis, A Field-Programmable Gate
`Array Architecture Optimized for Datapaths, Department of Electrical
`and Computer Engineering, University of Toronto (1994)
`(“Cherepacha”)
`Paul Chow et al., “The Design of a SRAM-Based Field-Programmable
`Gate Array—Part II: Circuit Design and layout,” in IEEE Transactions
`on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 3, pp. 321-
`330, Sept. 1999 (“Chow”) (from pages 4-13 of Declaration of Gordon
`MacPherson at Ex.1024)
`Declaration of Gordon MacPherson regarding Paul Chow et al., “The
`Design of a SRAM-Based Field-Programmable Gate Array—Part II:
`Circuit Design and layout,” in IEEE Transactions on Very Large Scale
`Integration (VLSI) Systems, vol. 7, no. 3, pp. 321-330, Sept. 1999
`U.S. Patent No. 5,905,385 (“Sharpe-Geisler”)
`Excerpt of Tom M. Apostol, Calculus, Volume 1 (Wiley 1967)
`(“Apostol”)
`Principles and Structures of FPGAs (Hideharu Amano, ed., Springer
`2018) (“Amano”)
`Jason Cong et al., “Technology Mapping For k/m-Macrocell Based
`FPGAs,” in Proceedings of the 2000 ACM/SIGDA 8th Int’l Symposium
`on Field Programmable Gate Arrays, 51-59 (Feb. 2000) (“Cong”)
`Plaintiff’s Preliminary Infringement Contentions in Iida v. Intel Corp.,
`No. 6:22-cv-00662-ADA (W.D. Tex.)
`
`
`
`6
`
`

`

`Exhibit
`No.
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`1036
`
`1040
`
`1041
`
`1043
`
`1044
`
`
`
`
`
`Description
`Complaint in Masahiro Iida v. Intel Corporation and Intel K.K., filed
`July 4, 2022, in the Department of Intellectual Property Rights, Tokyo
`District Court, certified translation, and declaration of translator
`Intel’s Opening Claim Construction Brief in Iida v. Intel Corp., No.
`6:22-cv-00662-ADA (W.D. Tex.)
`Iida’s Responsive Claim Construction Brief in Iida v. Intel Corp., No.
`6:22-cv-00662-ADA (W.D. Tex.)
`Declaration of Dr. Marwan Hassoun in support of Professor Masahiro
`Iida’s Responsive Claim Construction Brief in Iida v. Intel Corp., No.
`6:22-cv-00662-ADA (W.D. Tex.)
`Intel’s Reply Claim Construction Brief in Iida v. Intel Corp., No. 6:22-
`cv-00662-ADA (W.D. Tex.)
`Iida’s Sur-Reply Claim Construction Brief in Iida v. Intel Corp., No.
`6:22-cv-00662-ADA (W.D. Tex.)
`Joint Claim Construction Statement in Iida v. Intel Corp., No. 6:22-cv-
`00662-ADA (W.D. Tex.)
`Japanese Patent No. 3580785B2, certified translation, and declaration of
`translator
`Iida’s Brief filed March 20, 2023, in Masahiro Iida v. Intel Corporation
`and Intel K.K., filed July 4, 2022, in the Department of Intellectual
`Property Rights, Tokyo District Court, certified translation, and
`declaration of translator, certified translation, and declaration of
`translator
`Andrew S. Tanenbaum, Structured Computer Organization (2d ed.
`1984) (“Tanenbaum”)
`Neil H.E. Weste & Kamran Eshraghian, Principles of CMOS VLSI
`Design: A Systems Perspective (1985) (“Weste”)
`
`7
`
`

`

`14. While I have organized the information presented in this declaration
`
`into sections and/or divisions, my opinions are supported by the information in the
`
`declaration in its entirety.
`
`15. Unless otherwise noted, all emphases in any quoted material has been
`
`added.
`
`III. MY UNDERSTANDING OF PATENT LAW
`I am not an attorney. In developing my opinions, I discussed various
`16.
`
`relevant legal principles with Petitioner’s attorneys. My understanding in this
`
`respect is as follows.
`
`17.
`
`I understand that “inter partes review” (“IPR”) is a proceeding before
`
`the United States Patent and Trademark Office (“PTO”) for evaluating the
`
`patentability of an issued patent’s claims based on prior art patents and printed
`
`publications.
`
`18.
`
`I understand that, in this proceeding, Petitioner has the burden of
`
`proving that the challenged claims of the ’737 patent are unpatentable by a
`
`preponderance of the evidence. I understand that “preponderance of the evidence”
`
`means that a fact or conclusion is more likely true than not true.
`
`19.
`
`I understand that, in IPR proceedings, claim terms in a patent are
`
`given their plain-and-ordinary meaning as understood by a POSA in the context of
`
`the entire patent and the prosecution history pertaining to the patent. If the
`
`
`
`8
`
`

`

`specification and/or prosecution history provides a special definition for a claim
`
`term that differs from the meaning the term would otherwise possess, that special
`
`definition controls. I have applied these standards in preparing the opinions in this
`
`declaration.
`
`20.
`
`I understand that determining whether a particular patent or printed
`
`publication constitutes prior art to a challenged patent claim can require
`
`determining the effective filing date (also known as the priority date) to which the
`
`challenged claim is entitled. I understand that for a patent claim to be entitled to
`
`the benefit of the filing date of an earlier application to which the patent claims
`
`priority, the earlier application must have described the claimed invention in
`
`sufficient detail to convey with reasonable clarity to a POSA that the inventor had
`
`possession of the claimed invention as of the earlier application’s filing date. I
`
`understand that a disclosure that merely renders the claimed invention obvious is
`
`not sufficient written description for the claim to be entitled to the benefit of the
`
`filing date of the application containing that disclosure.
`
`21.
`
`I understand that for an invention claimed in a patent to be patentable,
`
`it must be, among other things, novel (i.e., not anticipated) and not obvious from
`
`the prior art. My understanding of these two legal standards is set forth below.
`
`
`
`9
`
`

`

`A. Anticipation
`
`22.
`
`I understand that, for a patent claim to be “anticipated” by the prior art
`
`(and therefore not novel), each and every limitation of the claim must be found,
`
`expressly or inherently, in a single prior art reference. I understand that a claim
`
`limitation is disclosed for the purpose of anticipation if a POSA would have
`
`understood the reference to disclose the limitation based on inferences that a POSA
`
`would reasonably be expected to draw from the explicit teachings in the reference
`
`when read in light of the POSA’s knowledge and experience.
`
`23.
`
`I understand that a claim limitation is inherent in a prior art reference
`
`if that limitation is necessarily present when practicing the teachings of the
`
`reference, regardless of whether a person of ordinary skill recognized the presence
`
`of that limitation in the prior art.
`
`B. Obviousness
`
`24.
`
`I understand that a patent claim may be unpatentable if it would have
`
`been obvious in view of a single prior art reference or a combination of prior art
`
`references.
`
`25.
`
`I understand that a patent claim is obvious if the differences between
`
`the subject matter of the claim and the prior art are such that the subject matter as a
`
`whole would have been obvious to a person of ordinary skill in the relevant field at
`
`
`
`10
`
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`the time the invention was made. Specifically, I understand that the obviousness
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`question involves a consideration of:
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`• the scope and content of the prior art;
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`• the differences between the prior art and the claims at issue;
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`• the knowledge of a person of ordinary skill in the pertinent art; and
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`• if present, objective factors indicative of non-obviousness, sometimes
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`referred to as “secondary considerations.” To my knowledge, the Patent
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`Owner has not asserted any such secondary considerations with respect to
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`the ’737 patent.
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`26.
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`I understand that in order for a claimed invention to be considered
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`obvious, a POSA must have had a reason for combining teachings from multiple
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`prior art references (or for modifying a single prior art reference or implementing
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`its teachings in a given manner, in the case of obviousness in view of a single
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`reference) in the fashion proposed.
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`27.
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`I further understand that in determining whether a prior art reference
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`would have been combined with other prior art or with other information within
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`the knowledge of a POSA, the following are examples of approaches and
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`rationales that may be considered:
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`• combining prior art elements according to known methods to yield
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`predictable results;
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`• simple substitution of one known element for another to obtain
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`predictable results;
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`• use of a known technique to improve similar devices in the same way;
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`• applying a known technique to a known device ready for improvement to
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`yield predictable results;
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`• applying a technique or approach that would have been “obvious to try,”
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`i.e., choosing from a finite number of identified, predictable solutions,
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`with a reasonable expectation of success;
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`• known work in one field of endeavor may prompt variations of it for use
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`in either the same field or a different one based on design incentives or
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`other market forces if the variations would have been predictable to one
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`of ordinary skill in the art; and
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`• some teaching, suggestion, or motivation in the prior art that would have
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`led one of ordinary skill to modify the prior art reference, to implement it
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`in a given way, or to combine prior art reference teachings to arrive at the
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`claimed invention. I understand that this teaching, suggestion or
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`motivation may come from a prior art reference or from the knowledge or
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`common sense of one of ordinary skill in the art.
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`28.
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`I understand that for a single reference or a combination of references
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`to render the claimed invention obvious, a POSA must have been able to arrive at
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`the claimed invention by modifying, implementing, and/or combining the
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`teachings of the applied references.
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`IV. PERSON OF ORDINARY SKILL IN THE ART
`I have been informed and understand that for purposes of assessing
`29.
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`whether prior art references disclose every element of a patent claim (thus
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`“anticipating” the claim) and/or would have rendered the claim obvious, the patent
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`and the prior art references must be assessed from the perspective of a POSA,
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`based on the understanding of that person at the time of the patent claim’s priority
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`date. I have been informed and understand that a POSA is presumed to be aware of
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`all pertinent prior art and the conventional wisdom in the art and is a person of
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`ordinary creativity. I have applied this standard throughout my declaration.
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`30. The ’737 patent involves technology in the field of PLDs, specifically
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`the use of look-up tables with internally configurable “LUT units” to implement
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`logic functions in PLDs. I have been asked to provide my opinions as to the state
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`of the art in these areas by June 2001. I use this timeframe because the face of the
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`’737 patent indicates an earliest effective filing date of June 29, 2001. I also
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`understand that the Patent Owner has identified June 29, 2001, as his alleged
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`priority date for the ’737 patent in patent infringement litigation against Petitioner.
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`See Ex.1029, 5. Whenever I offer an opinion in this declaration about the
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`knowledge of a POSA, the manner in which a POSA would have understood the
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`claims of the ’737 patent or its description, the manner in which a POSA would
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`have understood the prior art, or what a POSA would have been led to do based on
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`the prior art, I am referencing the 2001 timeframe, even if I do not say so
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`specifically in each case. Demonstrating that the ’737 patent’s claims were
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`anticipated or would have been obvious in 2001 demonstrates that they remained
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`so any time after 2001, because a POSA as of a later date would possess the same
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`or more knowledge.
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`31.
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`I understand that the Patent Owner might attempt to prove that the
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`alleged invention recited in the challenged claims was conceived at some time
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`prior to the earliest effective filing date on the face of the patent. At the time of this
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`declaration, I am unaware of any evidence produced by the Patent Owner to
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`establish any earlier conception date.
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`32.
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`I understand there are multiple factors relevant to determining the
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`level of ordinary skill in the pertinent art, including (1) the levels of education and
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`experience of persons working in the field at the time of the invention, (2) the
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`sophistic